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51. 再颁专利

USRE34295E Signal processing circuit 失效
公开(公告)号：USRE34295E
公开(公告)日：1993-06-29
申请号：US486389
申请日：1990-02-28
申请人： Toshifumi Shibuya , Hiroshi Endoh , Yoshimi Iso , Takao Arai , Hiroo Okamoto
发明人： Toshifumi Shibuya , Hiroshi Endoh , Yoshimi Iso , Takao Arai , Hiroo Okamoto
IPC分类号： H03M1/00
CPC分类号： H03M1/504 , H03M1/822
摘要： An integration type D/A and A/D converter having improved linearity and low power consumption. Logic circuits such as ECL counters consuming a major part of power of the D/A and A/D converters are realized through CMOS process. Current source circuits, current switch circuit and comparator circuit of the integration type A/D converter are realized in IC through bipolar process ensuring high accuracy and low noise. Logic parts such as counter is realized through CMOS process.

52. 发明授权

US5084788A PCM signal reproducing/recording apparatus 失效
标题翻译： PCM信号再生/记录装置
公开(公告)号：US5084788A
公开(公告)日：1992-01-28
申请号：US231001
申请日：1988-08-11
申请人： Yuuji Hatanaka , Hiroo Okamoto , Takao Arai , Shin-ichi Wakumura , Ichiro Miyake , Shunichiro Sakamoto
发明人： Yuuji Hatanaka , Hiroo Okamoto , Takao Arai , Shin-ichi Wakumura , Ichiro Miyake , Shunichiro Sakamoto
IPC分类号： G11B20/10 , G11B27/032 , G11B27/30
CPC分类号： G11B27/3063 , G11B20/10527 , G11B27/032 , G11B27/3027 , G11B2220/90 , G11B2220/913
摘要： Disclosed is a PCM signal reproducing/recording apparatus which comprises a reproducing device for reproducing a recording medium carrying PCM data and sub-code data recorded thereon, the sub-code data having sub-data and sub-ID for adding auxiliary information to the PCM data, and a recording device for recording the PCM data and sub-code data transmitted from the reproducing device onto a recording medium. The recording device is arranged to selectively record the sub-code data judged to be correct, onto a recording medium, of those sub-code data transmitted from the reproducing device.

53. 发明授权

US4965867A Offset compensation circuit 失效
标题翻译：偏移补偿电路
公开(公告)号：US4965867A
公开(公告)日：1990-10-23
申请号：US234874
申请日：1988-08-22
申请人： Masami Tsuchida , Ichiro Miyake , Tokihiro Takahashi , Shinichi Wakumura , Yoshimi Iso , Takao Arai , Hiroo Okamoto
发明人： Masami Tsuchida , Ichiro Miyake , Tokihiro Takahashi , Shinichi Wakumura , Yoshimi Iso , Takao Arai , Hiroo Okamoto
IPC分类号： H03M1/02 , H03M1/06 , H03M1/10 , H04L25/06
CPC分类号： H03M1/1023 , H03M1/0607 , H04L25/067 , H03M1/02
摘要： An offset compensation circuit for compensating a DC offset which occurs in a circuit line including an A/D converter or an A/D and D/A converter in which not only the polarity bit of digital data but also information concerning the amplitude of an analog input signal are applied to an integrator to precisely compensate an offset voltage in a circuit line. The level of a proper offset compensation voltage is provided even when an input analog signal such as a music signal is absent, and when an A/D and D/A converter is provided which can perform both A/D conversion and D/A conversion the DC offset can be precisely compensated shortly after the change of the mode from D/A conversion to A/D conversion.
摘要翻译：一种偏移补偿电路，用于补偿在包括A / D转换器或A / D和D / A转换器的电路线中发生的DC偏移，其中不仅数字数据的极性位，而且还涉及与模拟输入信号被施加到积分器以精确地补偿电路线路中的偏移电压。即使没有诸如音乐信号的输入模拟信号，并且当提供可以执行A / D转换和D / A转换的A / D和D / A转换器时，也提供适当的偏移补偿电压的电平在将模式从D / A转换改变为A / D转换之后，DC偏移可以很快精确地补偿。

54. 发明授权

US4646170A Method and apparatus for recording and reproducing a digital signal with a stationary head 失效
标题翻译：用固定头记录和再现数字信号的方法和装置
公开(公告)号：US4646170A
公开(公告)日：1987-02-24
申请号：US757448
申请日：1985-07-22
申请人： Masaharu Kobayashi , Hiroo Okamoto , Takao Arai
发明人： Masaharu Kobayashi , Hiroo Okamoto , Takao Arai
IPC分类号： G11B20/12 , G11B5/09 , G11B20/18 , G11B5/02 , G06F11/10
CPC分类号： G11B20/1809
摘要： In a stationary head type PCM recorder having an A/D converter for sampling an analog signal and converting the analog signal to a digital signal, a signal processing circuit including data delay means for adding an error detection and correction code and a predetermined signal to the digital signal for each error correction group of a predetermined number of samples, and a multi-track head for recording an output of the signal processing circuit on a plurality of tracks of a magnetic record medium and reproducing the signals recorded on the magnetic record medium; incorrectability of the error detection and correction code for a burst error in the output analog signal due to a burst error in the reproduced output is reduced by delaying parity data by the error detection and correction code and the digital signal data by different delay times such that the digital signal data are dispersely recorded in a track direction and a tape transport direction, and allotting the delayed data to the multi-track head such that the data of the adjacent sample points are spaced from each other by at least the distribution length of the parity data and the parity data is arranged between the distributed adjacent data.
摘要翻译：在具有用于对模拟信号进行采样并将模拟信号转换为数字信号的A / D转换器的静态磁头型PCM记录器中，包括数据延迟装置的信号处理电路，用于将误差检测和校正码以及预定信号加到数字信号，以及用于在磁记录介质的多个轨道上记录信号处理电路的输出并再现记录在磁记录介质上的信号的多轨头; 由于错误检测和校正码以及数字信号数据通过不同的延迟时间来延迟奇偶校验数据，所以减少了由于再现输出中的脉冲串错误导致的输出模拟信号中的脉冲串错误的错误检测和校正码的不正确性，数字信号数据被分散地记录在轨道方向和磁带传输方向上，并且将延迟的数据分配给多磁道磁头，使得相邻采样点的数据彼此间隔至少为奇偶校验数据和奇偶校验数据被布置在分布的相邻数据之间。

55. 发明授权

US4583074A Expansion circuit for digital signals 失效
标题翻译：数字信号扩展电路
公开(公告)号：US4583074A
公开(公告)日：1986-04-15
申请号：US527358
申请日：1983-08-29
申请人： Hiroo Okamoto , Tsutomu Noda , Takao Arai
发明人： Hiroo Okamoto , Tsutomu Noda , Takao Arai
IPC分类号： H04B1/64 , G11B3/00 , G11B7/00 , G11B20/10 , H03G7/00 , H03M7/50 , H04B14/04
CPC分类号： H03M7/50 , H03G7/007 , H04B14/048
摘要： A PCM signal processor which converts an analog signal into a digital signal to transmit or record the digital signal. When the PCM signal processor receives a PCM signal whose data has been compressed in such a manner that one or more lower bits are cut off from a plurality of bits for forming the PCM signal and indicating the signal level of the analog signal, in accordance with the signal level of the analog signal, one or more bits corresponding to the number of bits having been cut off are added in the processor to the compressed PCM signal at the position following the least significant bit of the compressed PCM signal. Correction data indicating about one half the largest one of numerical values that can be expressed by the added bit or bits, is given to the added bit or bits.
摘要翻译： PCM信号处理器，其将模拟信号转换为数字信号以传送或记录数字信号。当PCM信号处理器接收到其数据已经被压缩的PCM信号，使得从用于形成PCM信号的多个比特中切出一个或多个低位并指示模拟信号的信号电平时，根据模拟信号的信号电平，对应于被切断的位数的一个或多个比特在处理器中被加到在压缩PCM信号的最低有效位之后的位置处的压缩PCM信号。指示相加位或数位可表示的数值中最大值数字的大约一半的校正数据。

56. 发明授权

US4746900A Signal processing circuit 失效
标题翻译：信号处理电路
公开(公告)号：US4746900A
公开(公告)日：1988-05-24
申请号：US938965
申请日：1986-12-08
申请人： Toshifumi Shibuya , Hiroshi Endoh , Yoshimi Iso , Takao Arai , Hiroo Okamoto
发明人： Toshifumi Shibuya , Hiroshi Endoh , Yoshimi Iso , Takao Arai , Hiroo Okamoto
IPC分类号： H03M1/00 , H03M1/50
CPC分类号： H03M1/504 , H03M1/822
摘要： An integration type D/A and A/D converter having improved linearity and low power consumption. Logic circuits such as ECL counters consuming a major part of power of the D/A and A/D converters are realized through CMOS process. Current source circuits, current switch circuit and comparator circuit of the integration type A/D converter are realized in IC through bipolar process ensuring high accuracy and low noise. Logic parts such as counter is realized through CMOS process.
摘要翻译：具有改善的线性度和低功耗的积分型D / A和A / D转换器。通过CMOS工艺实现了消耗D / A和A / D转换器大部分功耗的ECL计数器的逻辑电路。集成型A / D转换器的电流源电路，电流开关电路和比较电路通过双极工艺在IC中实现，确保了高精度和低噪声。逻辑部件如计数器通过CMOS工艺实现。

57. 发明授权

US4682152A Digital data companding 失效
标题翻译：数字数据压扩
公开(公告)号：US4682152A
公开(公告)日：1987-07-21
申请号：US368868
申请日：1982-04-15
申请人： Hiroo Okamoto , Takao Arai , Takashi Hoshino
发明人： Hiroo Okamoto , Takao Arai , Takashi Hoshino
IPC分类号： H03G7/00 , H03M7/50
CPC分类号： H03G7/007 , H03M7/50
摘要： Digital companding without range bits involves comparison of a digital input with predetermined boundaries separating a plurality of numerical ranges, detection of a numerical range to which the digital input belongs, generation of an off-set unique to each numerical range, bit-shifting of the digital input, and addition of the bit-shifted input with the generated off-set to provide a companded digital output which is in one-to-one correspondence to the digital input. The off-set values are stored in a memory.
摘要翻译：没有范围位的数字压扩包括将数字输入与划分多个数字范围的预定边界进行比较，数字输入所属的数值范围的检测，每个数值范围唯一的偏移的产生，位移数字输入以及将所产生的偏移量与位移输入相加以提供与数字输入一一对应的压缩数字输出。偏移值存储在存储器中。

58. 发明授权

US5585933A Recording and/or reproducing apparatus for recording and/or reproducing image data compressed according to different compressing methods 失效
标题翻译：用于记录和/或再现根据不同压缩方法压缩的图像数据的记录和/或再现装置
公开(公告)号：US5585933A
公开(公告)日：1996-12-17
申请号：US357156
申请日：1994-12-15
申请人： Kenji Ichige , Takao Arai , Masuo Oku , Hiroo Okamoto
发明人： Kenji Ichige , Takao Arai , Masuo Oku , Hiroo Okamoto
IPC分类号： H04N5/92 , H04N5/926 , H04N5/94 , H04N19/50 , H04N19/65 , H04N19/89 , H04N19/895 , H04N19/91 , H04N5/76
CPC分类号： H04N5/9264 , H04N5/94
摘要： A recording and/or reproducing apparatus for recording and/or reproducing image signals compressed according to different compressing methods. This recording and/or reproducing apparatus includes a compressing circuit for compressing first image data according to a first image data compressing method, a selecting circuit supplied with the first image data thus compressed and encoded by the compressing circuit and second image data compressed and encoded according to a second image data compressing method and selecting any one of the first and second compressed image data, and a first error correction encoding circuit for error correction encoding the selected compressed image data. The recording and/or reproducing apparatus further includes a recording and/or reproducing circuit for recording and/or reproducing the error correction encoded data on and/or from a recording medium, a first error correction decoding circuit for error correction decoding the compressed image data reproduced by the recording and/or reproducing circuit, an image data expanding circuit for expanding the compressed image data that has been error-corrected by the error correction decoding circuit, and an output circuit for outputting the first image data expanded by the image data expanding circuit. The second image data has a bit rate not greater than that of the first image data.
摘要翻译：一种用于记录和/或再现根据不同压缩方法压缩的图像信号的记录和/或再现装置。该记录和/或再现装置包括用于根据第一图像数据压缩方法压缩第一图像数据的压缩电路，提供有由压缩电路压缩和编码的第一图像数据的选择电路和根据第二图像数据压缩方法，并且选择第一和第二压缩图像数据中的任何一个，以及用于对所选择的压缩图像数据进行纠错编码的第一纠错编码电路。记录和/或再现装置还包括用于在记录介质上和/或从记录介质记录和/或再现纠错编码数据的记录和/或再现电路，用于对压缩图像数据进行纠错解码的第一纠错解码电路由记录和/或再现电路再现的图像数据扩展电路，用于扩展由纠错解码电路进行了纠错的压缩图像数据，以及输出电路，用于输出由图像数据扩展扩展的第一图像数据电路。第二图像数据具有不大于第一图像数据的比特率。

59. 发明授权

US5182678A PCM signal reproducing/recording apparatus 失效
标题翻译： PCM信号再现/记录装置
公开(公告)号：US5182678A
公开(公告)日：1993-01-26
申请号：US829570
申请日：1992-02-05
申请人： Yuuji Hatanaka , Hiroo Okamoto , Takao Arai , Shin-ichi Wakumura , Ichiro Miyake , Shunichiro Sakamoto
发明人： Yuuji Hatanaka , Hiroo Okamoto , Takao Arai , Shin-ichi Wakumura , Ichiro Miyake , Shunichiro Sakamoto
IPC分类号： G11B20/10 , G11B27/032 , G11B27/30
CPC分类号： G11B20/10527 , G11B27/032 , G11B27/3027 , G11B27/3063 , G11B2220/90 , G11B2220/913
摘要： Disclosed is a PCM signal reproducing/recording apparatus which comprises a reproducing device for reproducing a recording medium carrying PCM data and sub-code data recorded thereon, the sub-code data having sub-data and sub-ID for adding auxiliary information to the PCM data, and a recording device for recording the PCM data and sub-code data transmitted from the reproducing device onto a recording medium. The recording device is arranged to selectively record the sub-code data judged to be correct, onto a recording medium, of those sub-code data transmitted from the reproducing device.
摘要翻译：公开了一种PCM信号再现/记录装置，其包括用于再现携带PCM数据和记录在其上的子代码数据的记录介质的再现装置，具有用于将辅助信息添加到PCM的子数据和子ID的子代码数据数据和用于将从再现装置发送的PCM数据和子代码数据记录到记录介质上的记录装置。记录装置被配置为将从判定为正确的子代码数据选择性地记录到从再现装置发送的那些子代码数据到记录介质上。

60. 发明授权

US08232623B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08232623B2
公开(公告)日：2012-07-31
申请号：US12333418
申请日：2008-12-12
申请人： Keiji Mita , Masao Takahashi , Takao Arai
发明人： Keiji Mita , Masao Takahashi , Takao Arai
IPC分类号： H01L27/102
CPC分类号： H01L29/7322 , H01L29/735 , H01L29/8618
摘要： A conventional semiconductor device has a problem that, when a vertical PNP transistor as a power semiconductor element is used in a saturation region, a leakage current into a substrate is generated. In a semiconductor device of the present invention, two P type diffusion layers as a collector region are formed around an N type diffusion layer as a base region. One of the P type diffusion layers is formed to have a lower impurity concentration and a narrower diffusion width than the other P type diffusion layer. In this structure, when a vertical PNP transistor is turned on, a region where the former P type diffusion layer is formed mainly serves as a parasite current path. Thus, a parasitic transistor constituted of a substrate, an N type buried layer and a P type buried layer is prevented from turning on, and a leakage current into the substrate is prevented.
摘要翻译：常规的半导体器件具有以下问题：当在饱和区域中使用作为功率半导体元件的垂直PNP晶体管时，产生进入衬底的漏电流。在本发明的半导体器件中，以N型扩散层为基底形成作为集电极区域的2个P型扩散层。 P型扩散层中的一个形成为具有比其他P型扩散层更低的杂质浓度和更窄的扩散宽度。在这种结构中，当垂直PNP晶体管导通时，形成前者P型扩散层的区域主要用作寄生电流路径。因此，防止由衬底，N型掩埋层和P型掩埋层构成的寄生晶体管导通，并且防止了进入衬底的漏电流。

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