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51. 发明申请

US20120237400A1 REAGENT PREPARATION APPARATUS AND SAMPLE PROCESSING APPARATUS 有权
标题翻译：试剂制备装置和样品加工装置
公开(公告)号：US20120237400A1
公开(公告)日：2012-09-20
申请号：US13417886
申请日：2012-03-12
申请人： Yutaka Ikeda , Noriyuki Nakanishi
发明人： Yutaka Ikeda , Noriyuki Nakanishi
IPC分类号： G01N1/28 , G01N27/00
CPC分类号： G01N35/00663 , G01N35/00613 , G01N35/00712 , G01N2035/00673 , Y10T436/12 , Y10T436/25
摘要： The present invention is a reagent preparation apparatus, comprising: a reagent preparation unit configured to prepare a reagent for processing a sample; a measuring unit configured to measure a property of the reagent prepared by the reagent preparation unit; a waste section configured to discard the prepared reagent when a measurement result by the measuring unit does not meet a predetermined condition; and a controller configured to control a reagent preparation operation of the reagent preparation unit, wherein the controller controls the reagent preparation unit to stop the reagent preparation operation when a number of times of discarding a reagent has reached a predetermined plurality of times.
摘要翻译：本发明是一种试剂调制装置，其特征在于，包括：试剂调制单元，其被配置为制备用于处理样品的试剂; 测量单元，被配置为测量由所述试剂调制单元制备的试剂的性质; 当所述测量单元的测量结果不满足预定条件时，废弃部分被配置为丢弃所述准备的试剂; 以及控制器，其被配置为控制所述试剂调制单元的试剂调制操作，其中，所述控制器控制所述试剂调制单元停止试剂准备操作，所述试剂停留次数达到预定次数。

52. 发明申请

US20100082137A1 CONTENT SETTING VALUE INFORMATION ACQUIRING DEVICE, CONTENT OUTPUT SYSTEM, CONTENT SETTING VALUE INFORMATION ACQUIRING METHOD, ITS PROGRAM, AND RECORDING MEDIUM ON WHICH ITS PROGRAM IS RECORDED 审中-公开
标题翻译：内容设置值信息获取设备，内容输出系统，内容设置值信息获取方法，其程序和记录其记录的记录介质
公开(公告)号：US20100082137A1
公开(公告)日：2010-04-01
申请号：US12532749
申请日：2007-03-27
申请人： Masahiro Suzuki , Osamu Santou , Kazunori Ochiai , Yutaka Ikeda , Kenji Okumichi , Masakatsu Fujimoto
发明人： Masahiro Suzuki , Osamu Santou , Kazunori Ochiai , Yutaka Ikeda , Kenji Okumichi , Masakatsu Fujimoto
IPC分类号： G06F15/16 , G06F17/00
CPC分类号： H04N7/17354 , H04N7/17318 , H04N21/21 , H04N21/23 , H04N21/252 , H04N21/258 , H04N21/25808 , H04N21/2662 , H04N21/485 , H04N21/6582
摘要： A server of a content output system acquires a user parameter registration information including a user name of a display and a title of a request content. When an image-quality and sound-quality optimum parameter is included, the server acquires the image-quality and sound-quality optimum parameter as a user's user setting information. When the server cannot acquire the user's user setting information, the server retrieves a user parameter registration information including a user name of another person and the title of the request content. When the image-quality and sound-quality optimum parameter is included in the user parameter registration information and an image-quality and sound-quality optimum parameter relating to other contents corresponds to an image-quality and sound-quality optimum parameter relating to other contents of a user requesting an image-quality and sound-quality optimum parameter, the server acquires an image-quality and sound-quality optimum parameter of the another person relating to the request content as an another person's user setting information. Then, the server transmits the user's user setting information or another person's user setting information to the display.
摘要翻译：内容输出系统的服务器获取包括显示的用户名和请求内容的标题的用户参数登记信息。当包括图像质量和声音质量最优参数时，服务器获取图像质量和声音质量最优参数作为用户的用户设置信息。当服务器不能获取用户的用户设置信息时，服务器检索包括另一个人的用户名和请求内容的标题的用户参数注册信息。当图像质量和声音质量最佳参数被包括在用户参数登记信息中，并且与其它内容相关的图像质量和声音质量最佳参数对应于与其它内容相关的图像质量和声音质量最佳参数请求图像质量和声音质量最佳参数的用户，服务器获取与请求内容相关的另一个人的图像质量和声音质量最佳参数作为另一个人的用户设置信息。然后，服务器将用户的用户设置信息或其他人的用户设置信息发送到显示器。

53. 发明申请

US20090106050A1 Bioinformation input/output device, bioinformation presenting device, bioinformation input/output method, and computer program 审中-公开
标题翻译：生物信息输入/输出设备，生物信息呈现设备，生物信息输入/输出方法和计算机程序
公开(公告)号：US20090106050A1
公开(公告)日：2009-04-23
申请号：US11921662
申请日：2007-04-04
申请人： Yutaka Ikeda , Hiroaki Niwamoto , Katsuya Nakagawa
发明人： Yutaka Ikeda , Hiroaki Niwamoto , Katsuya Nakagawa
IPC分类号： G06Q50/00
CPC分类号： G06F19/3418 , G06Q50/24 , G16H40/63
摘要： A bioinformation input/output apparatus comprises bioinformation storage means for storing bioinformation in association with a user or users, device information storage means for storing a device(s) in association with the user or users, and bioinformation output means for reading bioinformation stored in the bioinformation storage means and outputting the bioinformation to a device. The bioinformation output means outputs the bioinformation to the device according to the user associated with the device. With this, the bioinformation input/output apparatus outputs bioinformation according to the device.
摘要翻译：生物信息输入/输出设备包括用于与用户或用户相关联地存储生物信息的生物信息存储装置，用于存储与用户或用户相关联的设备的设备信息存储装置和用于读取存储在用户或用户中的生物信息的生物信息输出装置生物信息存储装置并将生物信息输出到装置。生物信息输出装置根据与设备相关联的用户将生物信息输出到设备。由此，生物信息输入输出装置根据装置输出生物信息。

54. 发明授权

US07391185B2 Battery pack protection circuit with plural protective means, and battery pack including the protection circuit 有权
标题翻译：具有多个保护装置的电池组保护电路，以及包括保护电路的电池组
公开(公告)号：US07391185B2
公开(公告)日：2008-06-24
申请号：US11612107
申请日：2006-12-18
申请人： Shuji Tsubaki , Kazuto Miyagawa , Yutaka Ikeda
发明人： Shuji Tsubaki , Kazuto Miyagawa , Yutaka Ikeda
IPC分类号： H01M10/46
CPC分类号： H02J7/0031 , H02H3/085 , H02H5/042 , H02H7/18
摘要： A battery pack includes a first switching element which shuts off a discharging current flowing to a battery cell and a second switching element which shuts off a charging current. A positive temperature coefficient thermistor is inserted between a gate control terminal of a protective control circuit and a gate of at least one of the switching elements, and a resistor is connected between the gate and a source of the switching element. The positive temperature coefficient thermistor is thermally connected to one or more of the first and second switching elements and/or to the battery cell. Thus, an abnormally overheated state of one or more of the switching elements or the battery cell leads to an increase in the resistance of the positive temperature coefficient thermistor causing shut-off of the switching element thereby protecting the battery pack.
摘要翻译：电池组包括切断流向电池单元的放电电流的第一开关元件和关闭充电电流的第二开关元件。正温度系数热敏电阻插入到保护控制电路的栅极控制端子和至少一个开关元件的栅极之间，并且电阻器连接在开关元件的栅极和源极之间。正温度系数热敏电阻热连接到第一和第二开关元件和/或电池单元中的一个或多个。因此，一个或多个开关元件或电池单元的异常过热状态导致正温度系数热敏电阻的电阻增加，导致开关元件截止从而保护电池组。

55. 发明授权

US06654300B2 Semiconductor memory device having internal circuit screening function 失效
标题翻译：具有内部电路筛选功能的半导体存储器件
公开(公告)号：US06654300B2
公开(公告)日：2003-11-25
申请号：US10216751
申请日：2002-08-13
申请人： Yutaka Ikeda
发明人： Yutaka Ikeda
IPC分类号： G11C700
CPC分类号： G11C29/028 , G11C29/12 , G11C29/12005
摘要： A semiconductor memory device includes an internal voltage generation circuit controlling an internal voltage supplied to an internal circuit in accordance with a reference voltage, a reference voltage generation circuit generating the reference voltage, a plurality of signal terminals for transmitting and receiving a signal to and from an outside of the semiconductor memory device, and a reference voltage change indication circuit for indicating a change of the reference voltage on the basis of a binary input signal to each of the signal terminals with respect to the reference voltage generation circuit during a test.
摘要翻译：半导体存储器件包括：内部电压产生电路，其根据参考电压控制提供给内部电路的内部电压;产生参考电压的参考电压产生电路;用于发送和接收信号的多个信号端子; 在半导体存储器件的外部，以及参考电压变化指示电路，用于在测试期间基于对于每个信号端子的二进制输入信号相对于参考电压产生电路指示参考电压的变化。

56. 发明授权

US06373782B1 Semiconductor device with reduced error operation caused by threshold voltage variation 失效
标题翻译：具有由阈值电压变化引起的误差操作降低的半导体器件
公开(公告)号：US06373782B1
公开(公告)日：2002-04-16
申请号：US09778783
申请日：2001-02-08
申请人： Yutaka Ikeda
发明人： Yutaka Ikeda
IPC分类号： G11C806
CPC分类号： G11C7/1084 , G11C7/1078 , G11C8/10 , H03K19/00384
摘要： An output circuit is driven by a first differential amplification circuit having an N-channel differential amplification stage that compares a reference voltage VREF with an input signal IN, and a second differential amplification circuit having a P-channel differential stage. An output of the first differential amplification circuit is given as the gate voltage of P-channel MOS transistors in the output circuit, and an output of the second differential amplification circuit is given as the gate voltage of N-channel MOS transistors in the output circuit. This realizes an input buffer with reduced error operations even under threshold voltage variations caused by process variations and others.
摘要翻译：输出电路由具有将参考电压VREF与输入信号IN进行比较的N沟道差分放大级的第一差分放大电路和具有P沟道差分级的第二差分放大电路驱动。第一差分放大电路的输出作为输出电路中的P沟道MOS晶体管的栅极电压，第二差分放大电路的输出作为输出电路中的N沟道MOS晶体管的栅极电压。即使在由过程变化等引起的阈值电压变化的情况下，也可以实现具有减少的误差运算的输入缓冲器。

57. 发明授权

US5894229A Input circuit of semiconductor memory device for generating an internal signal in accordance with an external signal and for applying it to an internal circuitry 失效
标题翻译：用于根据外部信号产生内部信号并将其施加到内部电路的半导体存储器件的输入电路
公开(公告)号：US5894229A
公开(公告)日：1999-04-13
申请号：US755813
申请日：1996-11-26
申请人： Shigeru Yamaoka , Yutaka Ikeda
发明人： Shigeru Yamaoka , Yutaka Ikeda
IPC分类号： G11C11/409 , G11C7/10 , G11C11/4096 , H03K3/356 , H03K19/003 , H03K19/017 , H03K19/0175 , H03K19/0185
CPC分类号： G11C7/1051 , G11C11/4096 , H03K19/00384 , H03K19/01742 , H03K3/356113
摘要： In a DRAM, first and second P channel MOS transistors are connected in series between an output node of an NOR gate of an input buffer and a power supply line. The first P channel MOS transistor receives at its gate an external signal /EXT and the second P channel MOS transistor receives at its gate an inverted signal of an output enable signal OEM. In a data output period, the signal OEM attains to the "H" level and the second P channel MOS transistor is rendered conductive, and therefore, even when power supply potential Vcc lowers in the data output period, the output node can be sufficiently charged, and an internal signal /INT can be generated stably.
摘要翻译：在DRAM中，第一和第二P沟道MOS晶体管串联连接在输入缓冲器的或非门的输出节点和电源线之间。第一P沟道MOS晶体管在其栅极接收外部信号/ EXT，第二P沟道MOS晶体管在其栅极接收输出使能信号OEM的反相信号。在数据输出期间，信号OEM达到“H”电平，第二P沟道MOS晶体管导通，因此即使电源电位Vcc在数据输出期间下降，输出节点也可以充分充电并且可以稳定地生成内部信号/ INT。

58. 发明授权

US5812021A Semiconductor integrated circuit device having an internal power supply circuit capable of stably maintaining output level against load fluctuation 失效
标题翻译：具有内部电源电路的半导体集成电路装置能够稳定地保持与负载波动的输出电平
公开(公告)号：US5812021A
公开(公告)日：1998-09-22
申请号：US962074
申请日：1997-10-31
申请人： Yutaka Ikeda
发明人： Yutaka Ikeda
IPC分类号： G11C11/407 , G05F1/46 , G05F3/24 , G11C5/14 , G11C11/413 , H01L21/822 , H01L27/04 , H01L27/10 , G05F1/10
CPC分类号： G11C5/147 , G05F1/465
摘要： An object is to provide a semiconductor device having an internal power supply circuit capable of supplying stable internal power supply voltage while not increasing layout area. A differential amplifying circuit in a voltage down converter controls potential level V.sub.OUT of the drain of transistor P14 such that it attains the reference potential V.sub.REF. If the potential V.sub.OUT increases, the gate potential of transistor N12 increases because of coupling function of a capacitance C2, and the transistor is rendered conductive. Thus the potential level V.sub.OUT is pulled down. By contrast, if the potential level V.sub.OUT lowers, transistor P12 is rendered conductive, and the potential level V.sub.OUT is pulled up.
摘要翻译：本发明的目的是提供一种具有内部电源电路的半导体器件，其能够在不增加布局面积的同时提供稳定的内部电源电压。降压转换器中的差分放大电路控制晶体管P14的漏极的电位VOUT，使其达到参考电位VREF。如果电位VOUT增加，则晶体管N12的栅极电位由于电容C2的耦合功能而增加，并且晶体管导通。因此，电位电平VOUT被拉低。相反，如果电位电平VOUT降低，晶体管P12导通，并且电位电平VOUT被上拉。

59. 发明授权

US5715130A Demagnetization circuit and components therefor 失效
标题翻译：退磁电路及其组件
公开(公告)号：US5715130A
公开(公告)日：1998-02-03
申请号：US789423
申请日：1997-01-29
申请人： Yutaka Ikeda
发明人： Yutaka Ikeda
IPC分类号： H04N9/29 , H01F13/00
CPC分类号： H04N9/29
摘要： A demagnetization circuit controls a demagnetization current to its demagnetization coil by means of a PTC thermistor with positive characteristic. The PTC thermistor is connected in series with and thermally coupled to a heat-sensitive switch. An NTC thermistor with negative characteristic for suppressing rush current of the voltage source is also thermally coupled to the heat-sensitive switch. After a power switch is closed, the heat-sensitive switch is opened by the heat emitted from the PTC thermistor and remains open by the heat from the NTC thermistor. The two thermistors and the heat-sensitive switch are contained in a case for easy handling and to make the component compact.
摘要翻译：退磁电路通过具有正特性的PTC热敏电阻控制到其去磁线圈的去磁电流。 PTC热敏电阻与热敏开关串联并热耦合。具有用于抑制电压源的冲击电流的负特性的NTC热敏电阻也热耦合到热敏开关。电源开关关闭后，热敏开关由PTC热敏电阻发出的热量打开，并通过NTC热敏电阻的热量保持开启状态。两个热敏电阻和热敏开关被包含在容易处理的壳体中并使组件紧凑。

60. 发明授权

US5490119A Semiconductor device including signal generating circuit with level converting function and with reduced area of occupation 失效
标题翻译：半导体器件包括具有电平转换功能的信号发生电路和占用面积减少
公开(公告)号：US5490119A
公开(公告)日：1996-02-06
申请号：US229274
申请日：1994-04-18
申请人： Mikio Sakurai , Kenji Tokami , Kazuhiro Sakemi , Yutaka Ikeda , Yoshinori Inoue , Takeshi Kajimoto
发明人： Mikio Sakurai , Kenji Tokami , Kazuhiro Sakemi , Yutaka Ikeda , Yoshinori Inoue , Takeshi Kajimoto
IPC分类号： G11C11/418 , G11C8/08 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/408 , G11C8/00
CPC分类号： G11C8/12 , G11C8/08
摘要： A semiconductor memory device includes a pull up circuit (811) for pulling up a potential of a first node (812), a pull down circuit (813) for pulling down the potential of the first node, an inverter circuit (814b) having its input connected to a first input node (814a) connected to the first node (812) and its output connected to a first output node (814c) and operating with a boosted potential Vpp, and a p channel MOS transistor (814d) connected between a boosted potential node (50c) and the first input node (814a), with its gate electrode connected to the first output node (814c). The memory device provides a signal having a higher level than the supply potential with smaller area of layout.
摘要翻译：半导体存储器件包括用于提升第一节点（812）的电位的上拉电路（811），用于下拉第一节点的电位的下拉电路（813），具有其的连接到连接到第一节点（812）的第一输入节点（814a）的输入端，并且其输出端连接到第一输出节点（814c）并且用升压电位Vpp操作，以及连接在升压的电压Vpp之间的ap沟道MOS晶体管（814d）电势节点（50c）和第一输入节点（814a），其栅电极连接到第一输出节点（814c）。存储器件提供具有比电源电位更高的电平的信号，具有较小的布局面积。

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