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51. 发明授权

US06378080B1 Clock distribution circuit 有权
标题翻译：时钟分配电路
公开(公告)号：US06378080B1
公开(公告)日：2002-04-23
申请号：US09472843
申请日：1999-12-28
申请人： Kenichiro Anjo , Masayuki Mizuno
发明人： Kenichiro Anjo , Masayuki Mizuno
IPC分类号： G06F104
CPC分类号： G06F1/10
摘要： A clock distribution circuit is provided with a plurality of blocks each having a plurality of circuits, a first clock driver which distributes a clock signal to each of the blocks, and second clock drivers each provided in one of the blocks. Each second clock drivers distributes the clock signal to each of the circuits in the block. A first wiring is connected between the first clock driver and each of the second clock drivers so that the clock signal arrives at each of the second clock drivers in the same phase. A plurality of second wirings are connected between the second clock drivers and each of the circuits in the block. The second wirings may consist of transmission lines. The second wirings have a maximum length equal to or smaller than a product of clock skew allowable and a propagation velocity of an electromagnetic wave propagating through the second wirings.
摘要翻译：时钟分配电路具有多个块，每个块具有多个电路，将时钟信号分配给每个块的第一时钟驱动器和分别设置在其中一个块中的第二时钟驱动器。每个第二个时钟驱动器将时钟信号分配给块中的每个电路。第一布线连接在第一时钟驱动器和每个第二时钟驱动器之间，使得时钟信号以相同的相位到达每个第二时钟驱动器。多个第二布线连接在第二时钟驱动器和块中的每个电路之间。第二条布线可以由传输线组成。第二配线的最大长度等于或小于允许的时钟偏移乘积和通过第二配线传播的电磁波的传播速度的乘积。

52. 发明授权

US06366616B1 Motion vector estimating apparatus with high speed and method of estimating motion vector 有权
标题翻译：高速运动矢量估计装置和估计运动矢量的方法
公开(公告)号：US06366616B1
公开(公告)日：2002-04-02
申请号：US09652135
申请日：2000-08-31
申请人： Masayuki Mizuno , Yasushi Ooi
发明人： Masayuki Mizuno , Yasushi Ooi
IPC分类号： H04N712
CPC分类号： H04N5/145 , G06T7/223 , G06T7/238 , G06T2207/10016 , H04N19/51 , H04N19/56
摘要： In a motion vector estimating apparatus, a current picture storage unit stores image data of a current picture, and a reference-picture storage unit stores image data of a reference picture. A search window determining unit determines estimation history from previously estimated motion vectors, and determines a search window based on the estimation history. At least one of a shape, size and position of the search window is determined based on the estimation history. The search window is composed of rectangular reference regions. A block matching circuit for performing a block matching process to a current block and each of reference blocks of the search window to determine a motion vector. The search window may be limited in units of pixels, or a load of the apparatus, a power supply voltage or a temperature of the block matching circuit.
摘要翻译：在运动矢量估计装置中，当前图像存储单元存储当前图像的图像数据，并且参考图像存储单元存储参考图像的图像数据。搜索窗口确定单元从先前估计的运动矢量确定估计历史，并且基于估计历史来确定搜索窗口。基于估计历史来确定搜索窗口的形状，大小和位置中的至少一个。搜索窗口由矩形参考区域组成。一种块匹配电路，用于对当前块和搜索窗口的每个参考块执行块匹配处理以确定运动矢量。搜索窗口可以以像素的单位，装置的负载，电源电压或块匹配电路的温度来限制。

53. 发明授权

US6078618A Motion vector estimation system 失效
标题翻译：运动矢量估计系统
公开(公告)号：US6078618A
公开(公告)日：2000-06-20
申请号：US34583
申请日：1998-03-04
申请人： Yutaka Yokoyama , Shu-Yu Zhu , Masayuki Mizuno
发明人： Yutaka Yokoyama , Shu-Yu Zhu , Masayuki Mizuno
IPC分类号： H04N19/50 , H04N5/14 , H04N19/105 , H04N19/134 , H04N19/139 , H04N19/172 , H04N19/196 , H04N19/423 , H04N19/503 , H04N19/51 , H04N19/527 , H04N19/57 , H04N19/573 , H04N19/85 , H04N7/12
CPC分类号： H04N5/145 , H04N19/51
摘要： A reference picture storing section 101 stores reference picture data referred in a motion vector estimation. A current picture storing section 102 stores a current picture data for the motion vector estimation. A motion vector estimating section 103 takes matching between the current picture data and the reference picture data to estimate a motion vector having the minimum difference. A motion vector statistics processing section 104 calculates an average value and a histogram from each picture of an estimated motion vector. A shift vector setting section 105 calculates a shift vector of a motion vector search window based on the average value and histogram in each of coded pictures. A search window designating section 106 designates a motion vector to be searched according to the calculated shift vector so as to cause the motion vector estimating section 103 to estimate the motion vector.
摘要翻译：参考图像存储部分101存储以运动矢量估计参考的参考图像数据。当前图像存储部分102存储用于运动矢量估计的当前图像数据。运动矢量估计部分103获取当前图像数据和参考图像数据之间的匹配，以估计具有最小差异的运动矢量。运动矢量统计处理部分104从估计运动矢量的每个图像计算平均值和直方图。移动矢量设定单元105根据各编码图像中的平均值和直方图，计算运动矢量搜索窗口的移动矢量。搜索窗口指定部分106根据所计算的移位矢量指定要搜索的运动矢量，以使得运动矢量估计部分103估计运动矢量。

54. 发明授权

US6051448A Method of manufacturing an electronic component 失效
标题翻译：电子部件的制造方法
公开(公告)号：US6051448A
公开(公告)日：2000-04-18
申请号：US870344
申请日：1997-06-06
申请人： Masaaki Hayama , Noboru Mouri , Tetsu Murakawa , Hayami Matsunaga , Masayuki Mizuno
发明人： Masaaki Hayama , Noboru Mouri , Tetsu Murakawa , Hayami Matsunaga , Masayuki Mizuno
IPC分类号： H01F17/00 , H01F41/04 , H01L21/48 , H05K1/03 , H05K1/16 , H05K3/12 , H05K3/20 , H05K3/46 , H01L21/483 , H01L21/56 , H01L21/58 , H01L21/60
CPC分类号： H01F41/043 , H01L21/4857 , H01L21/4867 , H05K3/207 , H01L2924/0002 , H05K1/0306 , H05K1/165 , H05K2203/0113 , H05K3/4667 , Y10S438/977
摘要： In a method of manufacturing an electronic component for forming a conductor pattern on an insulating substrate by transfer method employing intaglio printing technique, this manufacturing method comprises a step of fabricating an intaglio 20 made of flexible resin forming an insulating layer 23 on a groove 21, a step of filling the groove 21 with Ag paste 24 and drying, a step of overlaying the intaglio 20 on an insulating substrate 2 having a water-soluble resin 28 formed on the surface by pressing a pressing portion 26, freezing, peeling off the intaglio 20 and insulating substrate 2, and transferring the pattern of the Ag paste 24, and a step of firing it and forming a conductor pattern.
摘要翻译：在通过使用凹版印刷技术的转印方法制造用于在绝缘基板上形成导体图案的电子部件的方法中，该制造方法包括在槽21上形成由柔性树脂制成的绝缘层23的凹版20的步骤，用Ag浆料24填充槽21并干燥的步骤，通过按压按压部26将凹版20覆盖在具有形成在表面上的水溶性树脂28的绝缘基板2上，从而将凹版剥离 20和绝缘基板2，并且转印Ag浆料24的图案，以及烧制步骤和形成导体图案。

55. 发明授权

US5889928A Output gradation adjustment method in image output apparatus 失效
标题翻译：图像输出装置中的输出灰度调整方法
公开(公告)号：US5889928A
公开(公告)日：1999-03-30
申请号：US804830
申请日：1997-02-24
申请人： Koji Nakamura , Masayuki Mizuno , Ryuichi Okumura
发明人： Koji Nakamura , Masayuki Mizuno , Ryuichi Okumura
IPC分类号： H04N1/407 , H04N1/50 , H04N1/60
CPC分类号： H04N1/4078
摘要： Method of automating at least a portion of an output gradation adjustment job for an image output apparatus. Test image data are corrected according to an initial gradation correction curve, and a test image is formed according to the image data thus corrected. The test image is read by a scanner to obtain read data. Based on the read data thus obtained, test image data are newly formed. Based on the newly formed test image data, a test image is again formed. The second-time test image thus formed is read by the scanner to obtain read data. Based on the read data obtained by reading the second-time test image, the initial gradation correction curve and a predetermined reference output curve, candidate point data are obtained. Based on the candidate point data, a gradation correction curve is formed and set.
摘要翻译：自动化图像输出装置的输出灰度调整作业的至少一部分的方法。根据初始灰度校正曲线校正测试图像数据，并根据如此校正的图像数据形成测试图像。测试图像由扫描仪读取以获得读取数据。基于这样获得的读取数据，新形成测试图像数据。基于新形成的测试图像数据，再次形成测试图像。由扫描器读取由此形成的第二次测试图像以获得读取数据。基于通过读取第二次测试图像获得的读取数据，获得初始灰度校正曲线和预定参考输出曲线，获得候选点数据。基于候选点数据，形成并设置灰度校正曲线。

56. 发明授权

US5726562A Semiconductor device and power supply controller for same 失效
标题翻译：半导体器件和电源控制器相同
公开(公告)号：US5726562A
公开(公告)日：1998-03-10
申请号：US711110
申请日：1996-09-09
申请人： Masayuki Mizuno
发明人： Masayuki Mizuno
IPC分类号： G11C11/413 , G11C11/412 , G05F3/04
CPC分类号： G11C11/412
摘要： A semiconductor device includes a first power supply line of a high potential, a second power supply line of a low potential, a third power supply line which is alternatively set to a potential equal to that of the first power supply line or to a potential lower than that of the first power supply line by some degree, and a fourth power supply line which is alternatively set to a potential equal to that of the second power supply line or to a potential higher than that of the second power supply line by some degree. A substrate bias terminal of each of pMOS transistors included in a static memory cell is connected to the first power supply line, and a source of each pMOS transistor is connected to the third power supply line. A substrate bias terminal of each of nMOS transistors included in a static memory cell is connected to the second power supply line, and a source of each pMOS transistor is connected to the fourth power supply line. In an operating condition, the third and fourth power supply lines are brought to the same potential as that of the first and second power supply lines, respectively. In a standby condition, the third and fourth power supply lines are brought to a potential lower and higher than that of the first and second power supply lines, respectively.
摘要翻译：半导体器件包括高电位的第一电源线，低电位的第二电源线，或者替代地设置为与第一电源线的电位相等的电位的第三电源线或者电位下降的电位与第一电源线的电位相比有一定程度的第四电源线，或者与第二电源线的电位相当的电位或比第二电源线的电位高一些的第四电源线。包括在静态存储单元中的每个pMOS晶体管的衬底偏置端子连接到第一电源线，并且每个pMOS晶体管的源极连接到第三电源线。包括在静态存储单元中的每个nMOS晶体管的衬底偏置端子连接到第二电源线，并且每个pMOS晶体管的源极连接到第四电源线。在工作状态下，分别使第三和第四电源线达到与第一和第二电源线相同的电位。在待机状态下，分别使第三和第四电源线的电位分别比第一和第二电源线低。

57. 发明授权

US5670903A Clock signal distribution circuit having a small clock skew 失效
标题翻译：时钟信号分配电路具有小的时钟偏移
公开(公告)号：US5670903A
公开(公告)日：1997-09-23
申请号：US521433
申请日：1995-08-30
申请人： Masayuki Mizuno
发明人： Masayuki Mizuno
IPC分类号： G06F1/10 , H03K5/00 , H03K5/13 , H03L7/06 , H03L7/07 , H03L7/081
CPC分类号： H03L7/0812 , G06F1/10 , H03K5/133 , H03L7/07 , H03K2005/00045
摘要： A clock signal distribution circuit provides a synchronized clock signal to a plurality of chips implementing an integrated circuit. The clock signal distribution circuit has a first and a second phase lock loop, a series of voltage controlled delay circuits and a pair of transmission lines formed between the chips. The input clock signal is transmitted from the first chip to the second chip through a transmission line, the end of which is a node supplying the output clock signal to the internal circuit of the second chip. The clock signal is then returned from the output node through the second transmission line. The first phase lock loop controls the series of voltage controlled delay circuits such that the signal at a midpoint reference node has a phase equal to the phase of the output clock signal. The second phase lock loop controls the first voltage controlled delay circuit such that the signal at the first output node has a phase synchronized with the phase of the input clock signal. A plurality of transmission lines with differing delay lengths may be accommodated by bypassing a number of voltage controlled delay circuits, proportional to the delay length of the transmission lines, split equally before the clock output and after the return input.
摘要翻译：时钟信号分配电路为实现集成电路的多个芯片提供同步的时钟信号。时钟信号分配电路具有第一和第二锁相环，一系列电压控制延迟电路和在芯片之间形成的一对传输线。输入时钟信号通过传输线从第一芯片发送到第二芯片，传输线路的末端是向第二芯片的内部电路提供输出时钟信号的节点。时钟信号然后通过第二传输线从输出节点返回。第一锁相环控制一系列电压控制延迟电路，使得中点参考节点处的信号的相位等于输出时钟信号的相位。第二锁相环控制第一电压控制延迟电路，使得第一输出节点处的信号具有与输入时钟信号的相位同步的相位。具有不同延迟长度的多个传输线可以通过绕过与时钟输出之前和在返回输入之后相等地分配的传输线的延迟长度成比例的多个电压控制延迟电路来适应。

58. 发明授权

US5629651A Phase lock loop having a reduced synchronization transfer period 失效
标题翻译：相位锁定循环具有减小的同步传送周期
公开(公告)号：US5629651A
公开(公告)日：1997-05-13
申请号：US510860
申请日：1995-08-03
申请人： Masayuki Mizuno
发明人： Masayuki Mizuno
IPC分类号： H03L7/099 , G06F1/04 , H03L7/081 , H03L7/089 , H03L7/095 , H03L7/10
CPC分类号： H03L7/0816 , G06F1/04 , H03L7/0995 , H03L7/10 , Y10S331/02
摘要： A phase lock loop has a lock detection circuit, a phase comparator, a charge pump circuit, a low-pass filter, a variable delay circuit and a frequency divider. The lock detection circuit generates a lock detection signal when a phase difference between an input reference clock and an output of the variable delay circuit is smaller than a predetermined value in a first stage of the synchronization operation. The input and output of the variable delay circuit are connected in a loop responding to the lock detection signal to form a voltage controlled oscillator (VCO) and shift the phase lock loop into a second stage of the synchronization operation. An initial control signal for controlling the VCO in the second stage is obtained as a value of the variable delay circuit in the first stage before generation of the lock detection signal, thereby obtaining a higher-speed synchronization operation and low jitters in the output clock.
摘要翻译：锁相环具有锁定检测电路，相位比较器，电荷泵电路，低通滤波器，可变延迟电路和分频器。当在同步操作的第一阶段当输入参考时钟和可变延迟电路的输出之间的相位差小于预定值时，锁定检测电路产生锁定检测信号。可变延迟电路的输入和输出以响应于锁定检测信号的环路连接以形成压控振荡器（VCO），并将锁相环转移到同步操作的第二阶段。在产生锁定检测信号之前，获得用于控制第二级中的VCO的初始控制信号作为第一级中的可变延迟电路的值，从而获得高速同步操作和输出时钟中的低抖动。

59. 发明授权

US5585754A Integrated digital circuit 失效
标题翻译：集成数字电路
公开(公告)号：US5585754A
公开(公告)日：1996-12-17
申请号：US222279
申请日：1994-04-04
申请人： Masakazu Yamashina , Masayuki Mizuno
发明人： Masakazu Yamashina , Masayuki Mizuno
IPC分类号： H03K3/0231 , H03K5/13 , H03L7/081 , H03L7/099 , H03L7/18
CPC分类号： H03L7/0805 , H03K3/0231 , H03K5/133 , H03L7/0812 , H03L7/0995 , H03L7/18
摘要： An integrated digital circuit includes an oscillation circuit comprising basic gate circuits having the number of stages proportional to the number of gates existing in the critical path of a synchronized circuit network and capable of controlling an oscillating frequency by at least one control signal line. A synchronized circuit network constructed with basic gate circuits capable of controlling the delay time by at least one control signal line operates synchronously by an oscillation signal transfer line. A control circuit controls the oscillation circuit and the synchronized circuit network using the control signal line so that the frequency of signal input from an externally input signal line is equalized with the frequency of signal from the oscillation circuit. Thus, the synchronized circuit network can be always operated at the frequency obtained from the oscillation signal transfer line even though the delay time of the basic gate circuit varied by variations of the device characteristics and the like.
摘要翻译：集成数字电路包括振荡电路，其包括具有与存在于同步电路网络的关键路径中的门数成比例的级数的基本门电路，并且能够通过至少一个控制信号线来控制振荡频率。由能够通过至少一个控制信号线控制延迟时间的基本门电路构成的同步电路网络由振荡信号传输线同步操作。控制电路使用控制信号线控制振荡电路和同步电路网络，使得从外部输入信号线输入的信号的频率与来自振荡电路的信号的频率相等。因此，即使基本门电路的延迟时间由设备特性等的变化而变化，同步电路网络也可以始终以从振荡信号传输线获得的频率进行工作。

60. 发明授权

US5442466A Plate sheet conveying mechanism having integrally formed sheet guide 失效
标题翻译：具有一体形成的片材引导件的片材输送机构
公开(公告)号：US5442466A
公开(公告)日：1995-08-15
申请号：US88387
申请日：1993-07-09
申请人： Shinji Kameyama , Takeo Yoshihiro , Yoshiki Aoyama , Kazuo Nakamura , Shuichi Akedo , Masayuki Mizuno
发明人： Shinji Kameyama , Takeo Yoshihiro , Yoshiki Aoyama , Kazuo Nakamura , Shuichi Akedo , Masayuki Mizuno
IPC分类号： H04N1/00 , H04N1/12 , H04N1/193 , H04N1/04
CPC分类号： H04N1/00588 , H04N1/00519 , H04N1/0057 , H04N1/00591 , H04N1/00602 , H04N1/121 , H04N1/193 , H04N2201/02404
摘要： In one of aspects of the invention, an automatic sheet conveying mechanism comprises upper and lower casings mutually coupling sheet conveying paths in a releasable state, and a sheet guide plate for partitioning the sheet conveying paths together with the lower casing, guiding the lower surface of the sheet being conveyed, and defining the projecting extent of the functional parts supported by the lower casing into the sheet conveying path, in which the sheet guide plate is formed integrally with the lower casing.
摘要翻译：在本发明的一个方面，自动片材输送机构包括上下壳体，其相互联接片材输送路径处于可释放状态;以及片材引导板，用于将片材输送路径与下壳体一起分隔，引导下表面片材被输送，并且将由下壳体支撑的功能部件的突出范围限定为片材输送路径，其中片材引导板与下壳体一体地形成。

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