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51. 发明授权

US07691701B1 Method of forming gate stack and structure thereof 失效
标题翻译：形成栅极叠层的方法及其结构
公开(公告)号：US07691701B1
公开(公告)日：2010-04-06
申请号：US12348332
申请日：2009-01-05
申请人： Michael P. Belyansky , Siddarth A. Krishnan , Unoh Kwon , Naim Moumen , Ravikumar Ramachandran , James Kenyon Schaeffer , Richard Wise , Keith Kwong Hon Wong , Hongwen Yan
发明人： Michael P. Belyansky , Siddarth A. Krishnan , Unoh Kwon , Naim Moumen , Ravikumar Ramachandran , James Kenyon Schaeffer , Richard Wise , Keith Kwong Hon Wong , Hongwen Yan
IPC分类号： H01L21/00
CPC分类号： H01L21/823842 , H01L21/823857
摘要： Embodiments of the present invention provide a method of forming gate stacks for field-effect-transistors. The method includes forming a metal-containing layer directly on a first titanium-nitride (TiN) layer, the first TiN layer covering areas of a semiconductor substrate designated for first and second types of field-effect-transistors; forming a capping layer of a second TiN layer on top of the metal-containing layer; patterning the second TiN layer and the metal-containing layer to cover only a first portion of the first TiN layer, the first portion of the first TiN layer covering an area designated for the first type of field-effect-transistors; etching away a second portion of the first TiN layer exposed by the patterning while protecting the first portion of the first TiN layer, from the etching, through covering with at least a portion of thickness of the patterned metal-containing layer; and forming a third TiN layer covering an areas of the semiconductor substrate designated for the second type of field-effect-transistors.
摘要翻译：本发明的实施例提供了一种形成场效应晶体管的栅叠层的方法。该方法包括直接在第一氮化钛（TiN）层上形成含金属层，第一TiN层覆盖用于第一和第二类场效应晶体管的半导体衬底的区域; 在所述含金属层的顶部上形成第二TiN层的覆盖层; 图案化第二TiN层和含金属层以仅覆盖第一TiN层的第一部分，第一TiN层的第一部分覆盖指定用于第一类型的场效应晶体管的区域; 蚀刻通过图案化暴露的第一TiN层的第二部分，同时通过覆盖图案化的含金属层的厚度的至少一部分来保护第一TiN层的第一部分免受蚀刻; 以及形成覆盖指定用于第二类场效应晶体管的半导体衬底的区域的第三TiN层。

52. 发明申请

US20090250760A1 METHODS OF FORMING HIGH-K/METAL GATES FOR NFETS AND PFETS 审中-公开
标题翻译：形成用于NFET和PFET的高K /金属栅的方法
公开(公告)号：US20090250760A1
公开(公告)日：2009-10-08
申请号：US12061081
申请日：2008-04-02
申请人： Michael P. Chudzik , William K. Henson , Naim Moumen , Dae-Gyu Park , Hongwen Yan
发明人： Michael P. Chudzik , William K. Henson , Naim Moumen , Dae-Gyu Park , Hongwen Yan
IPC分类号： H01L27/088 , H01L21/4763
CPC分类号： H01L21/84 , H01L21/823842 , H01L21/823857
摘要： Methods of forming high-k/metal gates for an NFET and PFET and a related structure are disclosed. One method includes recessing a PFET region; forming a first high-k dielectric layer and a first metal layer over the substrate; removing the first high-k dielectric layer and the first metal over the NFET region using a mask; forming a forming a second high-k dielectric layer and a second metal layer over the substrate, the first high-k dielectric layer being different then the second high-k dielectric layer and the first metal being different than the second metal; removing the second high-k dielectric layer and the second metal over the PFET region using a mask; depositing a polysilicon over the substrate; and forming a gate over the NFET region and the PFET region by simultaneously etching the polysilicon, the first high-k dielectric layer, the first metal, the second high-k dielectric layer and the second metal.
摘要翻译：公开了形成用于NFET和PFET的高k /金属栅极和相关结构的方法。一种方法包括使PFET区域凹陷; 在所述衬底上形成第一高k电介质层和第一金属层; 使用掩模在NFET区域上去除第一高k电介质层和第一金属; 在所述衬底上形成第二高k电介质层和第二金属层，所述第一高k电介质层与所述第二高k电介质层不同，所述第一金属与所述第二金属不同; 使用掩模在PFET区域上去除第二高k电介质层和第二金属; 在衬底上沉积多晶硅; 以及通过同时蚀刻多晶硅，第一高k电介质层，第一金属，第二高k电介质层和第二金属，在NFET区域和PFET区域上形成栅极。

53. 发明申请

US20090212376A1 SEMICONDUCTOR TRANSISTORS HAVING HIGH-K GATE DIELECTRIC LAYERS AND METAL GATE ELECTRODES 失效
标题翻译：具有高K栅电介质层和金属栅极电极的半导体晶体管
公开(公告)号：US20090212376A1
公开(公告)日：2009-08-27
申请号：US12038195
申请日：2008-02-27
申请人： James William Adkisson , Michael Patrick Chudzik , Jeffrey Peter Gambino , Hongwen Yan
发明人： James William Adkisson , Michael Patrick Chudzik , Jeffrey Peter Gambino , Hongwen Yan
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/1037 , H01L21/28194 , H01L21/28202 , H01L29/42368 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A semiconductor structure and a method for forming the same. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate dielectric corner region. The final gate dielectric region (i) includes a first dielectric material, and (ii) is disposed between and in direct physical contact with the channel region and the final gate electrode region. The first gate dielectric corner region (i) includes a second dielectric material that is different from the first dielectric material, (ii) is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, (iii) is not in direct physical contact with the final gate electrode region, and (iv) overlaps the final gate electrode region in a reference direction.
摘要翻译：半导体结构及其形成方法。半导体结构包括（i）半导体衬底，其包括沟道区，（ii）半导体衬底上的第一和第二源极/漏极区，（iii）最终栅极电介质区，（iv）最终栅电极区和（v）第一栅介质角区域。最后的栅介质区域（i）包括第一电介质材料，和（ii）设置在沟道区域和最终栅电极区域之间并与其直接物理接触。第一栅介质角区域（i）包括与第一介电材料不同的第二电介质材料，（ii）设置在第一源极/漏极区域和最终栅极电介质区域之间并与之直接物理接触;（iii））不与最终栅电极区域直接物理接触，并且（iv）在参考方向上与最终栅电极区域重叠。

54. 发明申请

US20090098737A1 METHOD OF PATTERNING MULTILAYER METAL GATE STRUCTURES FOR CMOS DEVICES 有权
标题翻译：用于CMOS器件的多层金属栅结构的方法
公开(公告)号：US20090098737A1
公开(公告)日：2009-04-16
申请号：US11870577
申请日：2007-10-11
申请人： Bruce B. Doris , Richard S. Wise , Hongwen Yan , Ying Zhang
发明人： Bruce B. Doris , Richard S. Wise , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/461
CPC分类号： H01L21/28088 , H01L21/32136 , H01L21/823828 , H01L29/4966 , H01L29/51
摘要： A method of forming patterning multilayer metal gate structures for complementary metal oxide semiconductor (CMOS) devices includes performing a first etch process to remove exposed portions of a polysilicon layer included within a gate stack, the polysilicon layer formed on a metal layer also included within the gate stack; oxidizing an exposed top portion of the metal layer following the first etch process so as to create an metal oxide layer having an etch selectivity with respect to the polysilicon layer; removing the metal oxide layer through a combination of a physical ion bombardment thereof, and the introduction of an isotropic chemical component thereto so as to prevent oxide material at bottom corners of the polysilicon layer; and performing a second etch process to remove exposed portions of the metal layer.
摘要翻译：形成用于互补金属氧化物半导体（CMOS）器件的图案化多层金属栅极结构的方法包括执行第一蚀刻工艺以去除包括在栅极堆叠内的多晶硅层的暴露部分，形成在也包括在栅极堆叠内的金属层上的多晶硅层门堆在第一蚀刻工艺之后氧化暴露的金属层的顶部部分，以便产生相对于多晶硅层具有蚀刻选择性的金属氧化物层; 通过物理离子轰击的组合除去金属氧化物层，并向其中引入各向同性化学成分，以防止多晶硅层底角的氧化物质; 以及执行第二蚀刻工艺以去除所述金属层的暴露部分。

55. 发明授权

US07438822B2 Apparatus and method for shielding a wafer from charged particles during plasma etching 失效
标题翻译：在等离子体蚀刻期间屏蔽晶片与带电粒子的装置和方法
公开(公告)号：US07438822B2
公开(公告)日：2008-10-21
申请号：US11260375
申请日：2005-10-28
申请人： Hongwen Yan , Brian L. Ji , Siddhartha Panda , Richard Wise , Bomy A. Chen
发明人： Hongwen Yan , Brian L. Ji , Siddhartha Panda , Richard Wise , Bomy A. Chen
IPC分类号： C23F1/00
CPC分类号： H01J37/32623 , H01J37/3266
摘要： A plasma etching system having a wafer chuck with a magnet that applies a magnetic field over a wafer to shield the wafer from charged particles. The magnetic field is parallel with the wafer, and is strongest near the wafer surface. The magnetic field may be straight, or circular. In operation, electrons are deflected from the wafer by the Lorentz force, the wafer acquires a positive charge, and ions are deflected by electrostatic repulsion. Neutral species are allowed through the magnetic field, and they collide with the wafer. Neutral species generally provide more isotropic and material-selective etching than charged particles, so the present magnetic field tends to increase etch isotropy and material selectivity. Also, the magnetic field can protect the wafer from seasoning processes designed to clean unwanted films from the chamber surface as seasoning processes typically rely on etching by charged particles.
摘要翻译：一种等离子体蚀刻系统，其具有带有磁体的晶片卡盘，该磁体在晶片上施加磁场以将晶片免受带电粒子的影响。磁场与晶片平行，并且在晶片表面附近最强。磁场可以是直的或圆形的。在操作中，电子通过洛伦兹力从晶片偏转，晶片获得正电荷，离子被静电排斥偏转。允许中性物质通过磁场，并且它们与晶片碰撞。中性物质通常提供比带电粒子更多的各向同性和材料选择性蚀刻，因此目前的磁场倾向于增加蚀刻各向同性和材料选择性。此外，由于调味过程通常依赖于带电粒子的蚀刻，所以磁场可以保护晶片免受调节过程的调节过程，以便从室表面清洁不需要的膜。

56. 发明申请

US20060166416A1 ADDITION OF BALLAST HYDROCARBON GAS TO DOPED POLYSILICON ETCH MASKED BY RESIST 审中-公开
标题翻译：添加沉积物中的多氯硅烷蚀刻阻垢剂
公开(公告)号：US20060166416A1
公开(公告)日：2006-07-27
申请号：US10905938
申请日：2005-01-27
申请人： Timothy Dalton , Wesley Natzle , Paul Pastel , Richard Wise , Hongwen Yan , Ying Zhang
发明人： Timothy Dalton , Wesley Natzle , Paul Pastel , Richard Wise , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L21/32139 , H01L21/32137 , Y10S438/909
摘要： A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar to, or the equivalent of, a gaseous byproduct generated within the processing chamber. The ballast gas is added in either an overload amount, or in an amount sufficient to compensate for varying pattern factor changes across the water. This etchant and added ballast gas form a substantially homogeneous etchant across the entire wafer, thereby accommodating for or compensating for these pattern factor differences. When etching the wafer using this homogeneous etchant, a passivation layer is formed on exposed wafer surfaces. The passivation layer protects the lateral sidewalls of the gate stacks during etch to result in straighter gate stacks.
摘要翻译：一种用于在半导体晶片上提供均匀且一致的栅叠层蚀刻的化学组成和方法，由此所述组合物包括添加的蚀刻剂和添加的压载气体。使用这种组合的蚀刻剂和压载气组合物形成栅堆叠。压载气体可以类似于或等同于在处理室内产生的气态副产物。压载气体以过载量或足以补偿横跨水的变化因子变化的量加入。这种蚀刻剂和添加的压载气体在整个晶片上形成基本均匀的蚀刻剂，从而适应或补偿这些图案因子差异。当使用这种均匀的蚀刻剂蚀刻晶片时，在暴露的晶片表面上形成钝化层。钝化层在蚀刻期间保护栅极堆叠的侧壁以产生更直的栅叠层。

57. 发明申请

US20060154184A1 METHOD FOR REDUCING FEATURE LINE EDGE ROUGHNESS 审中-公开
标题翻译：减少特征线边缘粗糙度的方法
公开(公告)号：US20060154184A1
公开(公告)日：2006-07-13
申请号：US10905596
申请日：2005-01-12
申请人： Arpan Mahorowala , Scott Bell , S. Dakshina Murthy , Stacy Rasgon , Hongwen Yan , Chih-Yuh Yang
发明人： Arpan Mahorowala , Scott Bell , S. Dakshina Murthy , Stacy Rasgon , Hongwen Yan , Chih-Yuh Yang
IPC分类号： G03F7/00
CPC分类号： G03F7/40 , H01L21/0274 , H01L21/31058 , H01L21/31144
摘要： A method of patterning a feature in a substrate to reduce edge roughness comprises forming a resist layer overlying a substrate, exposing the resist layer to create an image of a feature, and developing the exposed resist layer to leave a portion of the resist layer that creates the image of the feature. The method then includes treating the exposed resist layer with a plasma to cure the portion of the resist layer creating the feature image. The plasma treatment has an ion bombardment level insufficient to substantially etch the underlying substrate. The method then includes etching the underlying substrate to create the feature.
摘要翻译：图案化衬底中的特征以减少边缘粗糙度的方法包括形成覆盖衬底的抗蚀剂层，暴露抗蚀剂层以产生特征的图像，以及显影曝光的抗蚀剂层以留下产生的抗蚀剂层的一部分功能的图像。该方法然后包括用等离子体处理曝光的抗蚀剂层以固化形成特征图像的抗蚀剂层的部分。等离子体处理具有不足以基本上蚀刻下面的衬底的离子轰击水平。该方法然后包括蚀刻下面的基底以产生特征。

58. 发明申请

US20060084243A1 Oxidation sidewall image transfer patterning method 审中-公开
标题翻译：氧化侧壁图像转印图案化方法
公开(公告)号：US20060084243A1
公开(公告)日：2006-04-20
申请号：US10969466
申请日：2004-10-20
申请人： Ying Zhang , Hongwen Yan , Oingyun Yang
发明人： Ying Zhang , Hongwen Yan , Oingyun Yang
IPC分类号： H01L21/20
CPC分类号： H01L21/28132 , H01L21/0337 , H01L21/0338 , H01L21/31116 , H01L21/32137 , H01L21/32139
摘要： A method is presented for patterning a MOSFET gate which includes the steps of: forming a layer of gate material over a gate dielectric, depositing an amorphous Si layer over the gate material, depositing a nitride cap-layer on top of the amorphous Si layer, patterning the nitride cap-layer and the amorphous Si layer which results in exposed sidewalls on the amorphous Si layer, growing oxide strips on the sidewalls, removing the patterned nitride cap-layer and the amorphous Si layer while leaving the oxide strips in place, and using the oxide strips as masks in the patterning of the gate material.
摘要翻译：提出了一种用于图案化MOSFET栅极的方法，其包括以下步骤：在栅极电介质上形成栅极材料层，在栅极材料上沉积非晶Si层，在非晶Si层的顶部上沉积氮化物盖层，图案化氮化物盖层和非晶Si层，其导致非晶Si层上的暴露的侧壁，在侧壁上生长氧化物条，去除图案化的氮化物盖层和非晶Si层，同时将氧化物条留在原位;以及在栅极材料的图案化中使用氧化物条作为掩模。

59. 发明申请

US20060035460A1 Wiring structure for integrated circuit with reduced intralevel capacitance 有权
标题翻译：具有降低的体积电容的集成电路的接线结构
公开(公告)号：US20060035460A1
公开(公告)日：2006-02-16
申请号：US11203944
申请日：2005-08-15
申请人： Richard Wise , Bomy Chen , Mark Hakey , Hongwen Yan
发明人： Richard Wise , Bomy Chen , Mark Hakey , Hongwen Yan
IPC分类号： H01L21/4763
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/53295 , H01L2221/1057 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated from the sidewalls by the spacers. The spacers are then removed, forming air gaps at the sidewalls so that the conductors are separated from the sidewalls by the air gaps. Dielectric layers above and below the conductors may be low-k dielectrics having a dielectric constant less than that of the dielectric between the conductors. A cross-section of each of the conductors has a bottom in contact with the a low-k dielectric layer, a top in contact with another low-k dielectric, and sides in contact only with the air gaps. The air gaps serve to reduce the intralevel capacitance.
摘要翻译：形成用于集成电路的布线结构的方法包括以下步骤：在介电材料层中形成多个特征，以及在特征的侧壁上形成间隔物。然后在特征中形成导体，通过间隔件与侧壁分离。然后去除间隔物，在侧壁处形成气隙，使得导体通过气隙与侧壁分离。导体之上和之下的介电层可以是具有比导体之间的电介质的介电常数小的介电常数的低k电介质。每个导体的横截面具有与低k电介质层接触的底部，与另一低k电介质接触的顶部和仅与气隙接触的侧面。气隙用于降低电容值。

60. 发明申请

US20050098091A1 Etch selectivity enhancement for tunable etch resistant anti-reflective layer 失效
标题翻译：可蚀刻耐腐蚀抗反射层的蚀刻选择性增强
公开(公告)号：US20050098091A1
公开(公告)日：2005-05-12
申请号：US10705577
申请日：2003-11-10
申请人： Katherina Babich , Scott Halle , David Horak , Arpan Mahorowala , Wesley Natzle , Dirk Pfeiffer , Hongwen Yan
发明人： Katherina Babich , Scott Halle , David Horak , Arpan Mahorowala , Wesley Natzle , Dirk Pfeiffer , Hongwen Yan
IPC分类号： C30B1/00 , C30B3/00 , C30B5/00 , C30B28/02 , H01L21/027 , H01L21/311 , H01L21/3213
CPC分类号： H01L21/0275 , H01L21/31144 , H01L21/32139 , Y10T428/24843
摘要： Methods for generating a nanostructure and for enhancing etch selectivity, and a nanostructure are disclosed. The invention implements a tunable etch-resistant anti-reflective (TERA) material integration scheme which gives high etch selectivity for both etching pattern transfer through the TERA layer (used as an ARC and/or hardmask) with etch selectivity to the patterned photoresist, and etching to pattern transfer through a dielectric layer of nitride. This is accomplished by oxidizing a TERA layer after etching pattern transfer through the TERA layer to form an oxidized TERA layer having chemical properties similar to oxide. The methods provide all of the advantages of the TERA material and allows for high etch selectivity (approximately 5-10:1) for etching to pattern transfer through nitride. In addition, the methodology reduces LER and allows for trimming despite reduced photoresist thickness.
摘要翻译：公开了产生纳米结构和提高蚀刻选择性的方法，以及纳米结构。本发明实现了可调谐抗蚀抗反射（TERA）材料集成方案，其对蚀刻图案转移通过TERA层（用作ARC和/或硬掩模）提供了高蚀刻选择性，具有对图案化光致抗蚀剂的蚀刻选择性，以及蚀刻到通过氮化物的介电层的图案转移。这是通过在通过TERA层蚀刻图案转移之后氧化TERA层来实现的，以形成具有与氧化物相似的化学性质的氧化TERA层。这些方法提供了TERA材料的所有优点，并且允许高蚀刻选择性（约5-10:1）蚀刻到通过氮化物的图案转移。此外，该方法减少LER，并允许尽管减少光致抗蚀剂厚度的修剪。

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