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51. 发明授权

US06629291B1 Integrated power solution for system on chip applications 有权
标题翻译：集成电源解决方案，用于片上系统应用
公开(公告)号：US06629291B1
公开(公告)日：2003-09-30
申请号：US09668977
申请日：2000-09-25
申请人： Russell J. Houghton , Joni C. Hsu , Louis L. Hsu , Li-Kong Wang
发明人： Russell J. Houghton , Joni C. Hsu , Louis L. Hsu , Li-Kong Wang
IPC分类号： G06F1750
CPC分类号： G06F1/28 , G06F17/5045 , G11C5/14
摘要： A centralized power supply system for a multi-system on chip device includes: an external power supply for supplying power to the device; a centralized DC generator macro having generator components for receiving the external power supplied and generating therefrom one or more power supply voltages for use by surrounding system macros provided on the multi-system chip, the centralized DC generator macro further distributing the generated power supply voltages to respective system macros. A noise blocking structure is provided that surrounds the centralized DC generator system and isolates the centralized DC generator system from the surrounding system macros.
摘要翻译：一种用于多系统片上设备的集中供电系统包括：用于向设备供电的外部电源; 集中式DC发电机宏，其具有用于接收所提供的外部电力并由其产生的一个或多个电源电压，用于由多系统芯片上提供的周围系统宏使用的发电机组件，集中式DC发电机宏进一步将生成的电源电压分配到各自的系统宏。提供了围绕集中式DC发电机系统的隔离结构，并将集中式DC发电机系统与周围系统宏隔离开来。

52. 发明授权

US06614714B2 Semiconductor memory system having a data clock system for reliable high-speed data transfers 失效
标题翻译：具有用于可靠的高速数据传输的数据时钟系统的半导体存储器系统
公开(公告)号：US06614714B2
公开(公告)日：2003-09-02
申请号：US10055149
申请日：2002-01-22
申请人： Louis L. Hsu , Jeremy K. Stephens , Daniel W. Storaska , Li-Kong Wang
发明人： Louis L. Hsu , Jeremy K. Stephens , Daniel W. Storaska , Li-Kong Wang
IPC分类号： G11C818
CPC分类号： G11C7/222 , G11C7/1006 , G11C7/1072 , G11C2207/104
摘要： A data clock system for a semiconductor memory system is provided for performing reliable high-speed data transfers. The semiconductor memory system includes a plurality of data banks configured for storing data, the plurality of data banks in operative communication with a plurality of first data paths, each first data path in operative communication with a second data path. The data clock system includes a first clock path receiving a clock signal during a data transfer operation for transferring data between one data bank of the plurality of data banks and the second data path via one of the plurality of first data paths; and a second clock path receiving the clock signal from the first clock path and propagating the clock signal along therethrough, the second clock path including at least one clock driver. The transfer of data between the one of the plurality of first data paths and the second data path occurs upon receipt of the clock signal by the at least one clock driver. A method for propagating a clock signal in a semiconductor memory system is also provided for performing reliable high-speed data transfers. In the inventive system and method the clock signal is delayed during propagation along the first clock path and the second clock path by approximately the same amount of time regardless if the at least one clock driver is positioned proximate a far end of the second clock path or the at least one clock driver is positioned proximate a near end of the second clock path.
摘要翻译：提供了一种用于半导体存储器系统的数据时钟系统，用于执行可靠的高速数据传输。半导体存储器系统包括被配置为存储数据的多个数据库，所述多个数据库与多个第一数据路径可操作地通信，每个第一数据路径与第二数据路径可操作地通信。数据时钟系统包括在数据传输操作期间接收时钟信号的第一时钟路径，用于经由多个第一数据路径中的一个数据路径在多个数据库的一个数据组和第二数据路径之间传送数据; 以及第二时钟路径，从第一时钟路径接收时钟信号并且沿着其传播时钟信号，第二时钟路径包括至少一个时钟驱动器。在所述至少一个时钟驱动器接收到所述时钟信号之后，发生所述多个第一数据路径中的一个数据路径和所述第二数据路径之间的数据传送。还提供了用于在半导体存储器系统中传播时钟信号的方法，用于执行可靠的高速数据传输。在本发明的系统和方法中，时钟信号在沿着第一时钟路径和第二时钟路径传播期间被延迟大约相同的时间量，而不管至少一个时钟驱动器位于第二时钟路径的远端附近，至少一个时钟驱动器位于第二时钟路径的近端附近。

53. 发明授权

US06400619B1 Micro-cell redundancy scheme for high performance eDRAM 有权
标题翻译：用于高性能eDRAM的微单元冗余方案
公开(公告)号：US06400619B1
公开(公告)日：2002-06-04
申请号：US09841950
申请日：2001-04-25
申请人： Louis L. Hsu , Li-Kong Wang
发明人： Louis L. Hsu , Li-Kong Wang
IPC分类号： G11C700
CPC分类号： G11C29/808 , G11C29/24 , G11C2207/104
摘要： A new micro-cell redundancy scheme for a wide bandwidth embedded DRAM having a SRAM cache interface. For each bank of micro-cell array units comprising the eDRAM, at least one micro-cell unit is prepared as the redundancy to replace a defected micro-cell within the bank. After array testing, any defective micro-cell inside the bank is replaced with a redundancy micro-cell for that bank. A fuse bank structure implementing a look-up table is established for recording each redundant micro-cell address and its corresponding repaired micro-cell address. In order to allow simultaneous multi-bank operation, the redundant micro-cells may only replace the defective micro-cells within the same bank. When reading data from eDRAM, or writing data to eDRAM, the micro-cell array address is checked against the look-up table to determine whether that data is to be read from or written to the original micro-cell, or the redundant micro-cell. The micro-cell redundancy scheme is a flexible and reliable method for high-performance eDRAM applications.
摘要翻译：一种用于具有SRAM缓存接口的宽带宽嵌入式DRAM的新型微小区冗余方案。对于包括eDRAM的每个微单元阵列单元组，至少一个微单元单元被准备为冗余以替代该单元内的缺陷微单元。在阵列测试之后，银行内的任何有缺陷的微单元被该银行的冗余微单元替代。建立实现查找表的熔丝库结构，用于记录每个冗余微小区地址及其对应的修复的微小区地址。为了允许同时多行操作，冗余微单元可以仅替换同一个存储体内的有缺陷的微单元。当从eDRAM读取数据或将数据写入eDRAM时，将针对查找表检查微单元阵列地址，以确定该数据是从原始微单元读取还是写入原始微单元，细胞。微单元冗余方案是高性能eDRAM应用的灵活可靠的方法。

54. 发明授权

US06355531B1 Method for fabricating semiconductor devices with different properties using maskless process 失效
标题翻译：使用无掩模工艺制造具有不同特性的半导体器件的方法
公开(公告)号：US06355531B1
公开(公告)日：2002-03-12
申请号：US09634225
申请日：2000-08-09
申请人： Jack A. Mandelman , Louis L. Hsu , Carl J. Radens , William R. Tonti , Li-Kong Wang
发明人： Jack A. Mandelman , Louis L. Hsu , Carl J. Radens , William R. Tonti , Li-Kong Wang
IPC分类号： H01L218236
CPC分类号： H01L21/823892 , H01L21/823807 , H01L21/82385 , Y10S438/981
摘要： A method is provided for fabricating semiconductor devices having different properties on a common semiconductor substrate. The method includes the steps of (a) forming N openings on the semiconductor substrate, wherein each opening is corresponding to a channel region of each semiconductor device, (b) forming oxide layers of an ith type on surfaces of the N openings, (c) depositing gate conductor material of an ith type over structure of the semiconductor devices, the gate conductor material of the ith type having a gate conductor work-function of an ith type, (d) removing the gate conductor material of the ith type such that a predetermined amount of the gate conductor material of the ith type remains in an ith opening to form a gate conductor material layer of the ith type on top surface in the ith opening and the gate conductor material of the ith type deposited in the structure other than the ith opening is removed, (e) removing the oxide layers of the ith type from openings other than the ith opening, (f) repeating the steps of (a) through (e) from “i=1” to “i=N”, and (g) forming at least one layer on surface of each of N gate conductor material layers in the N openings to form a gate conductor, whereby the N semiconductor devices have N gate conductors, respectively, wherein the N gate conductors have N types of gate conductor work-functions. The semiconductor devices also have channel regions of which doping levels are different from each other by implanting the channel regions with different types of implants.
摘要翻译：提供了一种在公共半导体衬底上制造具有不同特性的半导体器件的方法。该方法包括以下步骤：（a）在半导体衬底上形成N个开口，其中每个开口对应于每个半导体器件的沟道区，（b）在N个开口的表面上形成第i个类型的氧化物层，（c ）沉积所述半导体器件的第i型结构的栅极导体材料，所述第i型栅极导体材料具有第i类型的栅极导体功函数，（d）去除所述第i种类型的栅极导体材料，使得第i个类型的栅极导体材料的预定量保持在第i个开口中，以在第i个开口的顶表面上形成第i型的栅极导体材料层，并且沉积在除第除去第i个开口，（e）从第i个开口以外的开口除去第i个类型的氧化物层，（f）重复步骤（a）至（e）从“i = 1”到“i = N “，（g）在其上形成至少一层在N个开口中的N个栅极导体材料层中的每一个的表面形成栅极导体，由此N个半导体器件分别具有N个栅极导体，其中N个栅极导体具有N种类型的栅极导体功函数。半导体器件还具有通过用不同类型的植入物植入沟道区域而使掺杂水平彼此不同的沟道区域。

55. 发明授权

US07191371B2 System and method for sequential testing of high speed serial link core 有权
标题翻译：高速串行连接核心序列测试系统及方法
公开(公告)号：US07191371B2
公开(公告)日：2007-03-13
申请号：US10118751
申请日：2002-04-09
申请人： Louis L. Hsu , Li-Kong Wang
发明人： Louis L. Hsu , Li-Kong Wang
IPC分类号： G01R31/28
CPC分类号： H04L1/243
摘要： A testing circuit for testing a series of at least three alternating transmitter and receiver links. The testing circuit including a built-in-self-test (BIST.) macro for generating test data and transmitting the test data to a first link of the series of transmitter and receiver links, and for receiving processed test data from a last link of the series of transmitter receiver links; and at least one test transmission line for transmitting test data received by a link of the series of transmitter and receiver links to a next link of the series of transmitter and receiver links, wherein the at least one test transmission line connects the at least three transmitter and receiver links. A method for testing a series of links having at least three alternating transmitter and receiver links of a plurality of transmitter and receiver links in a SerDes core including generating at least one test data signal; transmitting the at least one test data signal sequentially through the transmitter and receiver links of the series of links; receiving the at least one test data signal from a last link of the series of transmitter and receiver links; and checking the at least one test data signal received.
摘要翻译：用于测试一系列至少三个交替发射机和接收机链路的测试电路。所述测试电路包括用于产生测试数据并将所述测试数据发送到所述一系列发射机和接收机链路的第一链路的内置自测试（BIST）宏，以及从所述一系列发射机和接收机链路的第一链路接收经处理的测试数据一系列发射机接收器链路; 以及至少一个测试传输线，用于将由所述一系列发射机和接收机链路的链路接收的测试数据发射到所述一系列发射机和接收机链路中的下一个链路，其中所述至少一个测试传输线路将所述至少三个发射机和接收器链接。一种用于测试一系列链路的方法，所述链路具有至少三个在SerDes核心中的多个发射机和接收机链路的交替发射机和接收机链路，包括生成至少一个测试数据信号; 通过所述一系列链路的所述发射机和接收机链路顺序地传送所述至少一个测试数据信号; 从所述一系列发射机和接收机链路的最后一个链路接收所述至少一个测试数据信号; 以及检查所接收的至少一个测试数据信号。

56. 发明授权

US07023528B2 Hybrid electronic mask 有权
标题翻译：混合电子面具
公开(公告)号：US07023528B2
公开(公告)日：2006-04-04
申请号：US10167327
申请日：2002-06-10
申请人： Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
发明人： Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
IPC分类号： G03B27/72 , G03B27/54 , G03B27/42
CPC分类号： G03F1/26 , G03F7/2014 , G03F7/70291
摘要： An electronically programmable mask for lithography has an array of individually controllable light sources aligned with an array of individually controllable liquid crystals, so that individual pixels may be turned on or off and phase-shifted to provide a desired light intensity distribution on a wafer. The mask may be used in a contact printing mode or in a reduction projection mode.
摘要翻译：用于光刻的电子可编程掩模具有与独立可控液晶阵列对准的独立可控光源的阵列，使得各个像素可以被导通或截止并相移以在晶片上提供期望的光强分布。掩模可以以接触印刷模式或缩小投影模式使用。

57. 发明授权

US06941414B2 High speed embedded DRAM with SRAM-like interface 有权
标题翻译：高速嵌入式DRAM，具有类SRAM接口
公开(公告)号：US06941414B2
公开(公告)日：2005-09-06
申请号：US09855240
申请日：2001-05-15
申请人： Louis L. Hsu , William Wu Shen , Li-Kong Wang
发明人： Louis L. Hsu , William Wu Shen , Li-Kong Wang
IPC分类号： G06F12/08 , G06F13/42 , G11C7/10 , G11C11/4093 , G11C11/4096 , G06F12/00
CPC分类号： G11C7/106 , G06F12/0893 , G06F13/4243 , G06F2212/3042 , G11C7/1006 , G11C7/1012 , G11C7/1039 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C11/4093 , G11C11/4096 , G11C2207/104 , G11C2207/2245
摘要： The invention provides a simple interface circuit between a large capacity, high speed DRAM and a single port SRAM cache to achieve fast-cycle memory performance. The interface circuit provides wider bandwidth internal communications than external data transfers. The interface circuit schedules parallel pipeline operations so that one set of data buses can be shared in cycles by several data flows to save chip area and alleviate data congestion. A flexible design is provided that can be used for a range of bandwidths of data transfer and generally any size bandwidth ranging from 32 to 4096 bits wide can use this same approach.
摘要翻译：本发明提供了在大容量，高速DRAM和单端口SRAM缓存之间的简单接口电路，以实现快速周期的存储器性能。接口电路提供比外部数据传输更宽的带宽内部通信。接口电路调度并行流水线操作，使得一组数据总线可以通过几个数据流循环共享，以节省芯片面积并减轻数据拥塞。提供了灵活的设计，可以用于数据传输的一系列带宽，一般来说，从32到4096位宽的任何大小的带宽可以使用这种相同的方法。

58. 发明授权

US06825534B2 Semiconductor device on a combination bulk silicon and silicon-on-insulator (SOI) substrate 有权
标题翻译：组合体硅和绝缘体上硅（SOI）衬底上的半导体器件
公开(公告)号：US06825534B2
公开(公告)日：2004-11-30
申请号：US09748256
申请日：2000-12-27
申请人： Howard H. Chen , Louis L. Hsu , Li-Kong Wang
发明人： Howard H. Chen , Louis L. Hsu , Li-Kong Wang
IPC分类号： H01L2701
CPC分类号： H01L21/76264 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02675 , H01L21/02689 , H01L21/2022 , H01L21/76283 , H01L21/84
摘要： A semiconductor device includes a combination substrate having a bulk silicon region, and a silicon-on-insulator (SOI) region. The SOI region includes a crystallized silicon layer formed by annealing amorphous silicon and having isolation trenches formed therein so as to remove defective regions, and isolation oxides formed in the isolation trenches.
摘要翻译：半导体器件包括具有体硅区域和绝缘体上硅（SOI）区域的组合衬底。 SOI区域包括由非晶硅退火形成的结晶硅层，并且在其中形成有隔离沟槽，以去除不良区域，以及在隔离沟槽中形成隔离氧化物。

59. 发明授权

US06751151B2 Ultra high-speed DDP-SRAM cache 有权
标题翻译：超高速DDP-SRAM缓存
公开(公告)号：US06751151B2
公开(公告)日：2004-06-15
申请号：US09827073
申请日：2001-04-05
申请人： Louis L. Hsu , Toshiaki K. Kirihata , Li-Kong Wang , Robert C. Wong
发明人： Louis L. Hsu , Toshiaki K. Kirihata , Li-Kong Wang , Robert C. Wong
IPC分类号： G11C800
CPC分类号： G06F12/0853 , G11C8/16 , H01L27/1104
摘要： An ultra high-speed DDP-SRAM (Dual Dual-Port Static Random Access Memory) cache having a cache speed in approximately the GHz range. This is accomplished by (1) a specially designed dual-port SRAM whose size is slightly larger than that of a conventional single port SRAM, and (2) the use of a dual dual-port SRAM architecture which doubles its speed by interleaved read and write operations. A first embodiment provides a 6-T (transistor) all nMOS dual-port SRAM cell. A second embodiment provides a dual port 7T-SRAM cell which has only one port for write, and both ports for read.
摘要翻译：具有大约GHz范围内的高速缓存的超高速DDP-SRAM（双重双端口静态随机存取存储器）缓存。这通过（1）专门设计的双端口SRAM（其尺寸略大于常规单端口SRAM）的实现来实现，以及（2）使用双重双端口SRAM架构，其通过交错读取将其速度加倍，写操作。第一实施例提供了6T（晶体管）全部nMOS双端口SRAM单元。第二实施例提供了一个双端口7T-SRAM单元，其仅具有一个用于写入的端口，以及用于读取的两个端口。

60. 发明授权

US06670234B2 Method of integrating volatile and non-volatile memory cells on the same substrate and a semiconductor memory device thereof 失效
标题翻译：将易失性和非易失性存储单元集成在同一衬底上的方法及其半导体存储器件
公开(公告)号：US06670234B2
公开(公告)日：2003-12-30
申请号：US09887403
申请日：2001-06-22
申请人： Louis L. Hsu , Carl J. Radens , Li-Kong Wang
发明人： Louis L. Hsu , Carl J. Radens , Li-Kong Wang
IPC分类号： H01L2100
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/10861 , H01L27/10894 , H01L27/11546
摘要： A method for fabricating DRAM and flash memory cells on a single chip includes providing a silicon substrate, forming a trench capacitor for each of the DRAM cells in the silicon substrate, forming isolation regions in the silicon substrate which are electrically isolated from each other, forming first type wells for DRAM and flash memory cells at first predetermined regions of the silicon substrate by implanting a first type impurity in the first predetermined regions, forming second type wells for DRAM and flash memory cells at second predetermined regions in the first type wells by implanting a second type impurity in the second predetermined regions, forming oxide layers for DRAM and flash memory cells on the second type wells, forming gate electrodes for DRAM and flash memory cells on the oxide layers for DRAM and flash memory cells, and forming source and drain regions for DRAM and flash memory cells in the respective second type wells for DRAM and flash memory cells, in which the source and drain regions are associated with each of the gate electrodes for DRAM and flash memory cells.
摘要翻译：在单个芯片上制造DRAM和闪存单元的方法包括提供硅衬底，为硅衬底中的每个DRAM单元形成沟槽电容器，形成硅衬底中彼此电隔离的隔离区域，形成通过在第一预定区域中注入第一种类型的杂质，在第一种类型的阱中的第二预定区域形成用于DRAM和闪速存储单元的第二类型阱，通过植入在第二预定区域中形成第二类型杂质，在第二类型阱上形成用于DRAM和闪存单元的氧化物层，在DRAM和闪存单元的氧化物层上形成用于DRAM的闪存存储单元的栅电极，以及形成源极和漏极用于DRAM和闪速存储器单元的相应的第二类型阱中的用于DRAM和闪存单元的区域 e源极和漏极区域与用于DRAM和闪存单元的每个栅电极相关联。

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