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51. 发明授权

US5151614A Circuit having charge compensation and an operation method of the same 失效
标题翻译：具有电荷补偿的电路及其操作方法
公开(公告)号：US5151614A
公开(公告)日：1992-09-29
申请号：US725037
申请日：1991-07-03
申请人： Akira Yamazaki , Masaki Kumanoya , Yasuhiro Konishi , Katsumi Dosaka
发明人： Akira Yamazaki , Masaki Kumanoya , Yasuhiro Konishi , Katsumi Dosaka
IPC分类号： H01L27/04 , H01L21/822 , H03K3/356 , H03K17/22
CPC分类号： H03K3/356008 , H03K17/223 , H01L2924/0002
摘要： A residual charge removing circuit connected to a node in a power-on reset pulse generating circuit for removing positive charges which remain in this node when a power supply is turned off is disclosed. This residual charge removing circuit is formed of two N-channel MOS transistors connected in series between the node and the ground, and one capacitor. Out of the two N-channel MOS transistors, the transistor near the node has a grounded gate. The capacitor is connected between a gate of the transistor, out of the two N-channel MOS transistors, which is distant from the node, and a power supply. The gate of the transistor distant from the node is connected to a connection point between the two N-channel MOS transistors. Therefore, when a supply potential lowers below a threshold voltage Vth of the MOS transistors due to the power-off, the transistor distant from the node is turned off, so that a potential of the connection point becomes -Vth owing to a discharge of negative charges from the capacitor. This turns on the transistor near the node, so that the residual charges in the node are offset by the negative charges in the connection point.
摘要翻译：公开了一种连接到上电复位脉冲发生电路中的节点的剩余电荷去除电路，用于去除当电源关闭时保留在该节点中的正电荷。该剩余电荷去除电路由串联在节点和地之间的两个N沟道MOS晶体管和一个电容器组成。在两个N沟道MOS晶体管中，节点附近的晶体管具有接地栅极。电容器连接在离节点的两个N沟道MOS晶体管中的晶体管的栅极和电源之间。远离节点的晶体管的栅极连接到两个N沟道MOS晶体管之间的连接点。因此，当电源电压由于断电而降低到MOS晶体管的阈值电压Vth以下时，远离节点的晶体管截止，使得由于放电为负的连接点的电位变为-Vth 从电容器充电。这使得节点附近的晶体管导通，使得节点中的剩余电荷被连接点中的负电荷抵消。

52. 发明授权

US5097440A Semiconductor memory device comprising a plurality of memory arrays with improved peripheral circuit location and interconnection arrangement 失效
标题翻译：包含改进的外围电路位置和互连布置的多个存储器阵列的半导体存储器件
公开(公告)号：US5097440A
公开(公告)日：1992-03-17
申请号：US437867
申请日：1989-11-17
申请人： Yasuhiro Konishi , Masaki Kumanoya , Katsumi Dosaka , Takahiro Komatsu , Yoshinori Inoue
发明人： Yasuhiro Konishi , Masaki Kumanoya , Katsumi Dosaka , Takahiro Komatsu , Yoshinori Inoue
IPC分类号： G11C11/401 , G11C11/4091 , G11C11/4097
CPC分类号： G11C11/4091 , G11C11/4097
摘要： A semiconductor memory device comprises eight memory arrays (b 10a, 10b) arranged in one column. A peripheral circuit (60) is arranged in the central portion of the eight memory arrays (10a, 10b), two column decoders (51, 52) being arranged with the peripheral circuit (60) interposed therebetween. Each of the eight memory arrays (10a, 10b) is provided with a row decoder (20). A plurality of first column selecting lines (CL1) are provided so as to cross the three memory arrays (10a, 10b) arranged on one side of the peripheral circuit (60) from the column decoder (51). In addition, a plurality of second column selecting lines (CL2) are provided so as to intersect with the three memory arrays (10a, 10b) arranged on the other side of the peripheral circuit (60) from the column decoder (52).
摘要翻译：半导体存储器件包括布置在一列中的八个存储器阵列（b 10a，10b）。外围电路（60）布置在八个存储器阵列（10a，10b）的中心部分中，两个列解码器（51,52）被布置在外围电路（60）之间。八个存储器阵列（10a，10b）中的每一个都具有行解码器（20）。多列第一列选择线（CL1）被设置为跨越从列解码器（51）排列在外围电路（60）一侧的三个存储器阵列（10a，10b）。另外，多列第二列选择线（CL2）被设置成与从列解码器（52）配置在外围电路（60）的另一侧的三个存储器阵列（10a，10b）相交。

53. 发明授权

US4896297A Circuit for generating a boosted signal for a word line 失效
标题翻译：用于产生用于字线的升压信号的电路
公开(公告)号：US4896297A
公开(公告)日：1990-01-23
申请号：US112034
申请日：1987-10-23
申请人： Hideshi Miyatake , Kazuyasu Fujishima , Masaki Kumanoya , Hideto Hidaka , Katsumi Dosaka , Yasuhiro Konishi
发明人： Hideshi Miyatake , Kazuyasu Fujishima , Masaki Kumanoya , Hideto Hidaka , Katsumi Dosaka , Yasuhiro Konishi
IPC分类号： G11C8/08
CPC分类号： G11C8/08
摘要： A circuit for generating a boosted signal for a word line, coupled to a word line driving signal line for transmitting a voltage signal to the word line, coupled to a first power supply, and coupled to a second power supply for providing a voltage higher than the voltage of the first power supply, can supply a compensating voltage for the word line from the second power supply through the word line driving signal line when a voltage of the word line is decreased.
摘要翻译：一种用于产生用于字线的升压信号的电路，耦合到字线驱动信号线，用于将电压信号传输到字线，耦合到第一电源，并耦合到第二电源，以提供高于当字线的电压减小时，第一电源的电压可以通过字线驱动信号线从第二电源提供用于字线的补偿电压。

54. 发明申请

US20130173106A1 VEHICLE 有权
标题翻译：车辆
公开(公告)号：US20130173106A1
公开(公告)日：2013-07-04
申请号：US13811976
申请日：2011-07-25
申请人： Yasuhiro Konishi
发明人： Yasuhiro Konishi
IPC分类号： B60W20/00 , B60W10/08 , B60W10/06
CPC分类号： B60W20/11 , B60K6/46 , B60L3/12 , B60L11/005 , B60L11/123 , B60L11/1816 , B60L2210/30 , B60L2210/40 , B60L2250/10 , B60L2250/16 , B60W10/06 , B60W10/08 , B60W20/00 , B60W20/18 , B60W50/0097 , B60W50/14 , B60W2050/146 , B60W2510/0623 , B60W2550/402 , B60W2560/02 , B60W2560/04 , F02D29/02 , F02M37/0076 , Y02T10/6217 , Y02T10/6269 , Y02T10/7005 , Y02T10/7022 , Y02T10/7072 , Y02T10/7077 , Y02T10/7241 , Y02T90/127 , Y02T90/14 , Y10S903/93
摘要： The present invention concerns a vehicle including a fuel tank, an engine to which fuel is supplied from the fuel tank, and a control device. The control device is characterized by notifying a refueling instruction corresponding to a use history of the vehicle. According to the present invention, the supply of extra fuel that can be degraded in the fuel tank can be prevented since a necessary refueling instruction is notified in accordance with the use history of the vehicle.
摘要翻译：本发明涉及一种包括燃料箱，从燃料箱供给燃料的发动机和控制装置的车辆。控制装置的特征在于通知与车辆的使用历史对应的加油指令。根据本发明，由于根据车辆的使用历史来通知必要的加油指示，因此能够防止在燃料箱中劣化的额外燃料的供给。

55. 发明授权

US08319617B2 Vehicle surroundings monitoring apparatus 有权
标题翻译：车辆周边监控装置
公开(公告)号：US08319617B2
公开(公告)日：2012-11-27
申请号：US12584869
申请日：2009-09-14
申请人： Kenichi Ohshima , Shigenobu Saigusa , Yasuhiro Konishi
发明人： Kenichi Ohshima , Shigenobu Saigusa , Yasuhiro Konishi
IPC分类号： B60Q1/00
CPC分类号： B60R1/12 , B60R1/00 , B60R2001/1253 , B60R2300/102 , B60R2300/105
摘要： A vehicle surroundings monitoring apparatus includes: a plurality of imaging units which capture an external region of a present-vehicle and output images; a display unit which is installed in an interior of the present-vehicle; a selector which selects an image to be displayed on the display unit from the images output from the imaging units; and a display control unit which displays the images output from the imaging units on the display unit so as to be switched in accordance with a selection by the selector and displays an image indicator display indicating a display region in the external region of the present-vehicle corresponding to the images so as to be switched by the selector on the display unit.
摘要翻译：车辆周边监视装置包括：多个成像单元，其捕获本车辆的外部区域并输出图像; 安装在本车内部的显示单元; 选择器，其从从所述成像单元输出的图像中选择要在所述显示单元上显示的图像; 以及显示控制单元，其将根据所述选择器的选择切换的所述成像单元输出的图像显示在所述显示单元上，并且在所述当前车辆的外部区域中显示指示显示区域的图像指示符显示器对应于图像，以便由显示单元上的选择器切换。

56. 发明授权

US07787475B2 Apparatus for processing a received signal in a communication network 失效
标题翻译：用于在通信网络中处理接收信号的装置
公开(公告)号：US07787475B2
公开(公告)日：2010-08-31
申请号：US11885942
申请日：2006-03-20
申请人： Shu Hagiwara , Suguru Nishio , Shingo Tsunoda , Yasuhiro Konishi , Masateru Gohno
发明人： Shu Hagiwara , Suguru Nishio , Shingo Tsunoda , Yasuhiro Konishi , Masateru Gohno
IPC分类号： H04L12/56
CPC分类号： H04W16/14 , H04L45/24 , H04W28/06 , H04W28/14 , H04W74/08 , H04W88/04
摘要： A communication apparatus having a temporary managing portion for controlling a temporary memory, a main managing portion for controlling a main memory and an operation control portion. The operation control portion causes the temporary managing portion and the main managing portion to utilize the state information or the history and state information for obtaining probability of deletion or transmission and probability of delay with regard to each data frame of framed data for discharge and to control, on the basis of the obtained probability of deletion or transmission and the obtained probability of delay, deletion or transmission of the data frame of the framed data for discharge and delay for transmission of the data frame of the framed data for discharge on the occasion of the transmission thereof.
摘要翻译：具有用于控制临时存储器的临时管理部分，用于控制主存储器的主管理部分和操作控制部分的通信装置。操作控制部分使得临时管理部分和主管理部分利用状态信息或历史和状态信息来获取关于用于放电的成帧数据的每个数据帧的删除或传输的概率和延迟的概率，并且控制基于所获得的删除或传输的概率以及获得的用于放电的成帧数据的数据帧的延迟，删除或传输的概率，以及用于发送用于放电的成帧数据的数据帧的延迟，其传输。

57. 发明申请

US20100070139A1 Vehicle maneuver assistance device 有权
标题翻译：车辆操纵辅助装置
公开(公告)号：US20100070139A1
公开(公告)日：2010-03-18
申请号：US12584734
申请日：2009-09-11
申请人： Kenichi Ohshima , Yukihiro Fujiwara , Yoshitaka Katashima , Hiroyuki Kawagoe , Shigenobu Saigusa , Yasushi Shoda , Manabu Shimizu , Yasuhiro Konishi
发明人： Kenichi Ohshima , Yukihiro Fujiwara , Yoshitaka Katashima , Hiroyuki Kawagoe , Shigenobu Saigusa , Yasushi Shoda , Manabu Shimizu , Yasuhiro Konishi
IPC分类号： G06F7/00
CPC分类号： B62D15/0275 , B60R1/00 , B60R2300/105 , B60R2300/303 , B60R2300/305 , B60R2300/607 , B60R2300/806 , B62D15/028
摘要： The vehicle maneuver assistance device includes: a plurality of external environment imaging units; a converter that performs a view point conversion; a display unit provided in an interior of the present-vehicle; a steering angle status value detector which detects status values of the steering angle representing an actual steering angle of the present-vehicle, and outputs a steering angle status value; a display controller that causes the display unit to display the converted image, and, overlaid thereon, a guidance display which assists a parking maneuver of the present-vehicle, wherein the display controller controls the guidance display according to the steering angle status value, so that the guidance display includes: an initial positioning guide line representing an initial location of the present-vehicle at the beginning of the parking maneuver; and a steering-switching start positioning guide line representing a starting location of a quick steering direction switching.
摘要翻译：车辆操纵辅助装置包括：多个外部环境成像单元; 执行视点转换的转换器; 设置在本车内部的显示单元; 转向角状态值检测器，其检测表示本车辆的实际转向角的转向角的状态值，并输出转向角状态值; 显示控制器，其使显示单元显示转换的图像，并且覆盖有辅助本车的停车操作的引导显示，其中显示控制器根据转向角状态值来控制引导显示，因此，引导显示包括：在停车操作开始时代表当前车辆的初始位置的初始定位引导线; 以及表示快速转向方向切换的起始位置的转向切换开始定位引导线。

58. 发明授权

US06434661B1 Synchronous semiconductor memory including register for storing data input and output mode information 失效
标题翻译：同步半导体存储器包括用于存储数据输入和输出模式信息的寄存器
公开(公告)号：US06434661B1
公开(公告)日：2002-08-13
申请号：US09640518
申请日：2000-08-17
申请人： Yasuhiro Konishi , Katsumi Dosaka , Kouji Hayano , Masaki Kumanoya , Akira Yamazaki , Hisashi Iwamoto
发明人： Yasuhiro Konishi , Katsumi Dosaka , Kouji Hayano , Masaki Kumanoya , Akira Yamazaki , Hisashi Iwamoto
IPC分类号： G06F1300
CPC分类号： G11C7/1006 , G06F12/0893 , G11C7/103 , G11C7/1045 , G11C11/005 , G11C2207/2254
摘要： A semiconductor memory device is provided with a static random access memory (SRAM) serving as a cache memory and a dynamic random access memory (DRAM) serving as a main memory. A bi-directional data transfer circuit is arranged for transfer of data blocks between the SRAM and the DRAM. A command register is provided for holding command data to set operation modes such as a data output mode of the memory device. The data output mode may include a transparent mode, a latched mode and a registered mode selected depending on a data combination at data input terminals of the memory device. An output circuit for providing a selected data output mode includes an output latch circuit for latching data on read data buses in response to clock signals, and an output buffer for outputting data from the output latches to a data output terminal. The latch circuit provides data at a first clock cycle of a clock signal when the command data has a first value and provides data at a second clock cycle of the clock signal, which is later than the first clock cycle, when the command data has a second value.
摘要翻译：半导体存储器件具有用作高速缓冲存储器的静态随机存取存储器（SRAM）和用作主存储器的动态随机存取存储器（DRAM）。双向数据传输电路被布置用于在SRAM和DRAM之间传送数据块。提供了一个命令寄存器来保存命令数据以设置诸如存储器件的数据输出模式的操作模式。数据输出模式可以包括根据存储器件的数据输入端子处的数据组合选择的透明模式，锁存模式和注册模式。用于提供选择的数据输出模式的输出电路包括用于响应于时钟信号在读取数据总线上锁存数据的输出锁存电路，以及用于将数据从输出锁存器输出到数据输出端的输出缓冲器。当命令数据具有第一值时，锁存电路以时钟信号的第一时钟周期提供数据，并且当命令数据具有第一时钟周期时，提供比第一时钟周期晚的时钟信号的第二时钟周期的数据第二个值。

59. 发明授权

US06356484B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06356484B2
公开(公告)日：2002-03-12
申请号：US09480006
申请日：2000-01-10
申请人： Katsumi Dosaka , Masaki Kumanoya , Yasuhiro Konishi , Katsumitsu Himukashi , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Ishizuka , Tsukasa Saika
发明人： Katsumi Dosaka , Masaki Kumanoya , Yasuhiro Konishi , Katsumitsu Himukashi , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Ishizuka , Tsukasa Saika
IPC分类号： G11C1100
CPC分类号： G11C8/00 , G06F12/0893 , G11C7/10 , G11C7/1018 , G11C7/1045 , G11C7/22 , G11C8/12 , G11C11/005 , G11C11/4076 , G11C11/4097 , G11C11/413 , G11C2207/002 , G11C2207/2227 , G11C2207/2245 , Y02D10/13
摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.
摘要翻译：半导体存储器件包括DRAM，SRAM和设置在SRAM和DRAM之间的双向传输门电路。 SRAM阵列包括多组字线。在SRAM阵列的每行中提供每组，并且每组中的每个字线连接到相关行的不同组的存储单元。 SRAM的地址信号和DRAM的地址信号分别应用于地址缓冲器。半导体存储器件还包括用于实现突发模式和睡眠模式的附加功能控制电路。从DRAM到SRAM的数据传输路径以及从SRAM到DRAM的数据传输路径分别设置在双向传输门电路中。数据写入路径和数据读取路径分别设置在DRAM阵列中。通过上述结构，在睡眠模式中停止缓冲电路的动作，降低功耗。由于数据写入路径和数据读取路径分别设置在DRAM阵列中，所以可以以非多路复用的方式应用DRAM阵列的地址，从而数据可以从DRAM阵列以高速传输到SRAM阵列，使得能够高高速运行即使在缓存未命中。

60. 发明授权

US5731727A Voltage control type delay circuit and internal clock generation circuit using the same 失效
标题翻译：电压控制型延迟电路和内部时钟发生电路使用相同
公开(公告)号：US5731727A
公开(公告)日：1998-03-24
申请号：US527968
申请日：1995-09-14
申请人： Hisashi Iwamoto , Yasuhiro Konishi
发明人： Hisashi Iwamoto , Yasuhiro Konishi
IPC分类号： G11C11/407 , G11C11/4076 , H03K5/13 , H03K19/096 , H03L7/081 , H03K5/14 , H03L1/00
CPC分类号： H03L7/081 , H03K5/133
摘要： A control transistor is connected in parallel with an input transistor of a bias generation circuit in a voltage control delay circuit. A power supply potential Vcc is divided by voltage divider resistors to be applied to the gate of the control transistor. Reduction in the power supply potential Vcc causes reduction in a current Ib flowing to the control transistor, and a current Ic=Ia+Ib flowing to a delay time variable element. When the power supply potential Vcc is reduced, the factor of a delay time period of delay time variable elements becoming shorter due to a smaller amplitude of a clock signal is canceled with the factor of the delay time period of the delay time variable elements become longer due to a smaller current Ic flowing thereto. Therefore, variation in the delay time period can be suppressed to a low level.
摘要翻译：控制晶体管与电压控制延迟电路中的偏置产生电路的输入晶体管并联连接。电源电位Vcc由施加到控制晶体管的栅极的分压电阻器分压。电源电位Vcc的降低导致流向控制晶体管的电流Ib的减少，流入延迟时间可变元件的电流Ic = Ia + Ib。当电源电位Vcc减小时，延迟时间可变元件由于时钟信号的较小振幅而变短的延迟时间的因子被延迟时间可变元件的延迟时间的因数变得更长由于流过其的较小的电流Ic。因此，可以将延迟时间段的变化抑制到低水平。

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