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51. 发明授权

US07710160B2 Stacked inverter delay chain 有权
标题翻译：堆叠变频器延时链
公开(公告)号：US07710160B2
公开(公告)日：2010-05-04
申请号：US12037884
申请日：2008-02-26
申请人： Robert P. Masleid , James B. Burr
发明人： Robert P. Masleid , James B. Burr
IPC分类号： H03K19/094
CPC分类号： H03K5/1252 , H03K5/133 , H03K17/6872 , H03K19/00361
摘要： Stacked inverter delay chains. In accordance with a first embodiment of the present invention, a series stack of two p-type devices is coupled to a series stack of three n-type devices, forming a stacked inverter comprising desirable delay, die area and power characteristics. Two stacked inverters are coupled together to form a stacked inverter delay chain that is more efficient in terms of die area, active and passive power consumption than conventional delay chains comprising conventional inverters.
摘要翻译：堆叠式逆变器延时链。根据本发明的第一实施例，两个p型器件的串联堆叠耦合到三个n型器件的串联堆叠，形成堆叠的反相器，其包括期望的延迟，管芯面积和功率特性。两个堆叠的反相器耦合在一起以形成堆叠的反相器延迟链，其在与常规逆变器的常规延迟链相比在管芯面积，主动和无源功耗方面更有效。

52. 发明授权

US07645664B1 Layout pattern for deep well region to facilitate routing body-bias voltage 有权
标题翻译：用于深井区域的布局图，以方便路偏偏置电压
公开(公告)号：US07645664B1
公开(公告)日：2010-01-12
申请号：US11449952
申请日：2006-06-08
申请人： Mike Pelham , James B. Burr
发明人： Mike Pelham , James B. Burr
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L29/0646 , G11C5/146 , H01L21/823493 , H01L21/823892 , H01L23/481 , H01L27/0203 , H01L27/0222 , H01L27/0928 , H01L29/1095 , H01L2924/0002 , H01L2924/00
摘要： Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh structure, an axial sub-surface mesh structure, a diagonal sub-surface strip structure, and an axial sub-surface strip structure. A particular layout pattern is selected for an area of the semiconductor device according to several factors.
摘要翻译：提供并描述了深阱区域的布局图案，以便于在半导体器件中布置体偏置电压。布局图案包括对角子表面网格结构，轴向子表面网格结构，对角子表面条带结构和轴向子表面条带结构。根据几个因素，为半导体器件的区域选择特定的布局图案。

53. 发明申请

US20090313591A1 METHOD FOR GENERATING A DEEP N-WELL PATTERN FOR AN INTEGRATED CIRCUIT DESIGN 失效
标题翻译：用于生成用于集成电路设计的深层N阱图案的方法
公开(公告)号：US20090313591A1
公开(公告)日：2009-12-17
申请号：US12544149
申请日：2009-08-19
申请人： Michael Pelham , James B. Burr
发明人： Michael Pelham , James B. Burr
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for the design and layout for a patterned deep N-well. A tile is specified as a fundamental building block for the deep N-well pattern. The tile comprises a first element on a first layer and may comprise a second element on a second layer. A two dimensional region is covered with an array of contiguous tiles, with the elements on each layer connecting with elements of adjacent tiles to form extended shapes. The array may be converted to a collection of sub-arrays through the removal of tiles. The array or collection of sub-arrays may be merged to produce a first layer pattern and second layer pattern. Design rule checks may be applied to verify the pattern. The first layer shapes and second layer shapes may be edited. The first layer shapes and the second layer shapes may then be combined to produce a deep N-well pattern.
摘要翻译：一种用于图案化深N阱的设计和布局的方法。将瓷砖指定为深N型图案的基本构建块。瓦片包括在第一层上的第一元件，并且可以包括在第二层上的第二元件。二维区域覆盖有连续瓦片阵列，每层上的元素与相邻瓦片的元素连接以形成延伸形状。阵列可以通过去除瓦片而转换为子阵列的集合。子阵列的阵列或集合可以被合并以产生第一层图案和第二层图案。可以应用设计规则检查来验证模式。可以编辑第一层形状和第二层形状。然后可以组合第一层形状和第二层形状以产生深N阱图案。

54. 发明授权

US07579221B1 Conversion of an SOI design layout to a bulk design layout 有权
标题翻译：将SOI设计布局转换为批量设计布局
公开(公告)号：US07579221B1
公开(公告)日：2009-08-25
申请号：US11393555
申请日：2006-03-29
申请人： David R. Ditzel , James B. Burr , Robert P. Masleid
发明人： David R. Ditzel , James B. Burr , Robert P. Masleid
IPC分类号： H01L21/00 , H01L21/84 , H01L21/20 , H01L21/36
CPC分类号： H01L27/0207 , H01L21/823878 , H01L21/84 , H01L27/0617 , H01L27/1203
摘要： An SOI design layout is converted to a bulk design layout. According to a method of converting a first semiconductor design layout based on an Silicon-on-Insulator (SOI) process to a second semiconductor design layout based on a bulk process, an insulator layer of the SOI process beneath active devices in the first semiconductor design layout is removed. A conductive sub-surface structure for routing voltage is added to the first semiconductor design layout. Further, the active devices from the SOI process are converted to the bulk process to form the second semiconductor design layout without requiring a relayout of the first semiconductor design layout on a semiconductor surface. The bulk design layout is utilized to fabricate a semiconductor device having a plurality of active devices.
摘要翻译： SOI设计布局被转换为散装设计布局。根据基于体积工艺将基于绝缘体上硅（SOI）工艺的第一半导体设计布局转换为第二半导体设计布局的方法，在第一半导体设计中的有源器件下方的SOI工艺的绝缘体层布局被删除。用于路由电压的导电子表面结构被添加到第一半导体设计布局。此外，来自SOI工艺的有源器件被转换为本体处理以形成第二半导体设计布局，而不需要在半导体表面上重新布置第一半导体设计布局。本体设计布局用于制造具有多个有源器件的半导体器件。

55. 发明申请

US20080246110A1 STRUCTURE FOR SPANNING GAP IN BODY-BIAS VOLTAGE ROUTING STRUCTURE 有权
标题翻译： BODY-BIAS电压路由结构中的扫描缝隙结构
公开(公告)号：US20080246110A1
公开(公告)日：2008-10-09
申请号：US12140197
申请日：2008-06-16
申请人： Robert P. Masleid , James B. Burr , Michael Pelham
发明人： Robert P. Masleid , James B. Burr , Michael Pelham
IPC分类号： H01L23/52
CPC分类号： H01L23/535 , H01L23/52 , H01L23/585 , H01L27/0218 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： Structures for spanning gap in body-bias voltage routing structure. In an embodiment, a structure is comprised of at least one metal wire.
摘要翻译：体偏电压布线结构跨越间隙的结构。在一个实施例中，结构由至少一根金属线构成。

56. 发明授权

US07334198B2 Software controlled transistor body bias 有权
标题翻译：软件控制晶体管体偏置
公开(公告)号：US07334198B2
公开(公告)日：2008-02-19
申请号：US10334638
申请日：2002-12-31
申请人： David R. Ditzel , James B. Burr
发明人： David R. Ditzel , James B. Burr
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Software controlled body bias. A target frequency is accessed. Using software, transistor body-biasing values are determined for the target frequency in order to enhance a characteristic of a circuit. The bodies of the transistors are biased based on the body-biasing values, wherein the characteristic is optimized.
摘要翻译：软件控制体偏。访问目标频率。使用软件，为了提高电路的特性，确定了目标频率的晶体管体偏置值。晶体管的主体基于身体偏置值被偏置，其中特性被优化。

57. 发明授权

US07211478B1 Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions 有权
标题翻译：对角深井区，用于在表面井区域中为MOSFETs布置体偏置电压
公开(公告)号：US07211478B1
公开(公告)日：2007-05-01
申请号：US11199896
申请日：2005-08-08
申请人： Mike Pelham , James B. Burr
发明人： Mike Pelham , James B. Burr
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L21/8234 , H01L21/337 , H01L31/119
CPC分类号： H01L29/0646 , G11C5/146 , H01L21/823493 , H01L21/823892 , H01L23/481 , H01L27/0203 , H01L27/0222 , H01L27/0928 , H01L29/1095 , H01L2924/0002 , H01L2924/00
摘要： Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described.
摘要翻译：提供和描述了用于在表面阱区域中用于路由MOSFETS的体偏置的对角深阱区域。

58. 发明授权

US07174528B1 Method and apparatus for optimizing body bias connections in CMOS circuits using a deep n-well grid structure 失效
标题翻译：使用深n阱格栅结构优化CMOS电路中的体偏置连接的方法和装置
公开(公告)号：US07174528B1
公开(公告)日：2007-02-06
申请号：US10683961
申请日：2003-10-10
申请人： James B. Burr , William N. Schnaitter
发明人： James B. Burr , William N. Schnaitter
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method and apparatus for optimizing body bias connections to NFETs and PFETs using a deep n-well grid structure. A deep n-well is formed below the surface of a CMOS substrate supporting a plurality of NFETs and PFETs having a nominal gate length of less than 0.2 microns. The deep n-well is a grid structure with a regular array of apertures providing electrical continuity between the bottom of the substrate and the NFETs. At least some of the PFETs reside in surface n-wells that are continuous with the buried n-well grid structure. The grid and n-well layout is performed on the basis of the functionality of the PFETs contained in the n-wells.
摘要翻译：一种用于优化使用深n阱栅格结构的NFET和PFET的体偏置连接的方法和装置。在支撑多个NFET和具有小于0.2微米的标称栅极长度的PFET的CMOS衬底的表面下方形成深n阱。深n阱是具有规则的孔阵列的栅格结构，其在衬底的底部和NFET之间提供电连续性。至少一些PFET存在于与埋置的n阱栅格结构连续的表面n阱中。栅极和n阱布局基于n阱中包含的PFET的功能进行。

59. 发明授权

US06957318B2 Method and apparatus for controlling a massively parallel processing environment 有权
标题翻译：用于控制大规模并行处理环境的方法和装置
公开(公告)号：US06957318B2
公开(公告)日：2005-10-18
申请号：US10112118
申请日：2002-03-28
申请人： David R. Emberson , Jeffrey M. Broughton , James B. Burr , Derek E. Pappas
发明人： David R. Emberson , Jeffrey M. Broughton , James B. Burr , Derek E. Pappas
IPC分类号： G06F17/50 , G06F3/00
CPC分类号： G06F17/5022
摘要： A method for controlling a processor array by a host computer involves creating a graph of a plurality of nodes using a data connection component, configuring a broadcast tree from a spanning tree of the graph, propagating a first command from the host computer to a member of the processor array using the broadcast tree, configuring a reply tree from a spanning tree of the graph, transmitting a response from the member of the processor array to the host computer using the reply tree, and configuring the data connection component to send at least one message selected from the first command and the response on at least one run mode communication path.
摘要翻译：用于由主计算机控制处理器阵列的方法包括使用数据连接组件创建多个节点的图形，从图表的生成树配置广播树，将第一命令从主计算机传播到主机的成员使用所述广播树的所述处理器阵列，从所述图的生成树配置回复树，使用所述答复树将所述处理器阵列的成员的响应发送到所述主计算机，以及配置所述数据连接组件以发送至少一个从第一命令中选择的消息和至少一个运行模式通信路径上的响应。

60. 发明授权

US06784726B2 Method and structure for supply gated electronic components 有权
标题翻译：供应门控电子元件的方法和结构
公开(公告)号：US06784726B2
公开(公告)日：2004-08-31
申请号：US10425772
申请日：2003-04-28
申请人： James B. Burr
发明人： James B. Burr
IPC分类号： G05F302
CPC分类号： G05F3/24
摘要： A method and structure for supply gating low power electronic components uses low threshold gating transistors. The low power components operate at supply voltages of less than one volt and typically in the range of 150 to 400 millivolts. Using low threshold gating transistors, the leakage current of the devices, and therefore the standby power dissipation, can be minimized by using any one, or a combination of, four methods including: overdriving the low threshold gating transistors on; overdriving the low threshold gating transistors off; combining very low threshold device transistors with low threshold gating transistors; and providing the low threshold gating transistors with back bias.
摘要翻译：供电门控低功率电子元件的方法和结构使用低阈值门控晶体管。低功率组件的工作电压小于1伏特，通常在150至400毫伏的范围内。使用低门限门控晶体管，可以通过使用以下四种方法中的任何一种或其组合来最小化器件的漏电流以及因此的待机功率耗散，包括：过载驱动低阈值门控晶体管; 过驱动低门限门控晶体管关闭; 将极低阈值器件晶体管与低阈值门控晶体管相结合; 以及提供具有反偏压的低阈值选通晶体管。

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