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51. 发明授权

US07941636B2 RISC microprocessor architecture implementing multiple typed register sets 失效
标题翻译： RISC微处理器架构实现多种类型的寄存器集
公开(公告)号：US07941636B2
公开(公告)日：2011-05-10
申请号：US12650998
申请日：2009-12-31
申请人： Sanjiv Garg , Derek J. Lentz , Le Trong Nguyen , Sho Long Chen
发明人： Sanjiv Garg , Derek J. Lentz , Le Trong Nguyen , Sho Long Chen
IPC分类号： G06F15/00
CPC分类号： G06F9/30029 , G06F9/30036 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30138 , G06F9/30167 , G06F9/30189 , G06F9/3851
摘要： Disclosed herein is an apparatus that implements multiple typed register sets, and applications thereof. The apparatus includes an execution unit and a register file. The execution unit is configured to execute instructions including one or more fields. The register file is configured to store operands defined by the one or more fields and is configured to store results of execution of the instructions in a destination defined by the one or more fields. The register file includes (i) a first register set having a register configured to store data of a single data type and (ii) a second register set having a register configured to store data of a plurality of data types. The register file is responsive to the one or more fields in at least one of the instructions to retrieve an operand of the at least one of the instructions from, or to store a result of the at least one of the instructions into, one of the registers of the first register set or the second register set as defined by the one or more fields of the at least one of the instructions.
摘要翻译：这里公开了一种实现多种类型寄存器集的装置及其应用。该装置包括执行单元和寄存器文件。执行单元被配置为执行包括一个或多个字段的指令。寄存器文件被配置为存储由一个或多个字段定义的操作数，并且被配置为将执行指令的结果存储在由一个或多个字段定义的目的地中。寄存器文件包括（i）具有被配置为存储单个数据类型的数据的寄存器的第一寄存器组，以及具有被配置为存储多个数据类型的数据的寄存器的第二寄存器组。寄存器文件响应于至少一个指令中的一个或多个字段，以从至少一个指令获取至少一个指令的操作数，或者将至少一个指令的结果存储到由所述至少一个指令的一个或多个字段定义的第一寄存器组或第二寄存器组的寄存器。

52. 发明授权

US07487333B2 High-performance, superscalar-based computer system with out-of-order instruction execution 失效
公开(公告)号：US07487333B2
公开(公告)日：2009-02-03
申请号：US10700485
申请日：2003-11-05
申请人： Le-Trong Nguyen , Derek J Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H Trang
发明人： Le-Trong Nguyen , Derek J Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H Trang
IPC分类号： G06F9/302 , G06F9/38 , G06F9/40
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

53. 发明授权

US07043624B2 System and method for assigning tags to control instruction processing in a superscalar processor 失效
公开(公告)号：US07043624B2
公开(公告)日：2006-05-09
申请号：US10847460
申请日：2004-05-18
申请人： Kevin R. Iadonato , Trevor A. Deosaran , Sanjiv Garg
发明人： Kevin R. Iadonato , Trevor A. Deosaran , Sanjiv Garg
IPC分类号： G06F15/00 , G06F9/30
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3885
摘要： A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each instruction. A queue having a plurality of slots containing tags which are used for tagging the instructions. The tags are arranged in the queue in an order specified by the program order of their corresponding instructions. A control unit monitors the completion of executed instructions and advances the tags in the queue upon completion of an executed instruction. The register file stores an instruction's information at a location in the register file defined by the tag assigned to that instruction. The register file also contains a plurality of read address enable ports and corresponding read output ports. Each of the slots from the queue is coupled to a corresponding one of the read address enable ports. Thus, the information for each instruction can be read out of the register file in program order.

54. 发明申请

US20050283591A1 System and method for handling load and/or store operations in a superscalar microprocessor 失效
公开(公告)号：US20050283591A1
公开(公告)日：2005-12-22
申请号：US11113135
申请日：2005-04-25
申请人： Cheryl Brashears , Johannes Wang , Le Nguyen , Derek Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Te-Li Lau , Sze-Shun Wang , Quang Trang
发明人： Cheryl Brashears , Johannes Wang , Le Nguyen , Derek Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Te-Li Lau , Sze-Shun Wang , Quang Trang
IPC分类号： G06F9/00 , G06F9/312 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3017 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.

55. 发明授权

US06965987B2 System and method for handling load and/or store operations in a superscalar microprocessor 失效
公开(公告)号：US06965987B2
公开(公告)日：2005-11-15
申请号：US10713145
申请日：2003-11-17
申请人： Cheryl Senter Brashears , Johannes Wang , Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
发明人： Cheryl Senter Brashears , Johannes Wang , Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
IPC分类号： G06F9/00 , G06F9/312 , G06F9/318 , G06F9/38 , G06F9/34 , G06F9/44 , G06F12/04
CPC分类号： G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3017 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.

56. 发明授权

US06934829B2 High-performance, superscalar-based computer system with out-of-order instruction execution 失效
公开(公告)号：US06934829B2
公开(公告)日：2005-08-23
申请号：US10697257
申请日：2003-10-31
申请人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
发明人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
IPC分类号： G06F9/32 , G06F9/30 , G06F9/34 , G06F9/38 , G06F9/42 , G06F9/40
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

57. 发明授权

US06915412B2 High-performance, superscalar-based computer system with out-of-order instruction execution 失效
公开(公告)号：US06915412B2
公开(公告)日：2005-07-05
申请号：US10283106
申请日：2002-10-30
申请人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
发明人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
IPC分类号： G06F9/32 , G06F9/30 , G06F9/34 , G06F9/38 , G06F9/42 , G06F15/76 , G06F13/36 , G06F13/40
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

58. 发明授权

US06647485B2 High-performance, superscalar-based computer system with out-of-order instruction execution 失效
公开(公告)号：US06647485B2
公开(公告)日：2003-11-11
申请号：US09852293
申请日：2001-05-10
申请人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
发明人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
IPC分类号： G06F930
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

59. 发明授权

US06360309B1 System and method for assigning tags to control instruction processing in a superscalar processor 失效
公开(公告)号：US06360309B1
公开(公告)日：2002-03-19
申请号：US09574251
申请日：2000-05-19
申请人： Kevin R. Iadonato , Trevor A. Deosaran , Sanjiv Garg
发明人： Kevin R. Iadonato , Trevor A. Deosaran , Sanjiv Garg
IPC分类号： G06F1500
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3885
摘要： A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each instruction. A queue having a plurality of slots containing tags which are used for tagging the instructions. The tags are arranged in the queue in an order specified by the program order of their corresponding instructions. A control unit monitors the completion of executed instructions and advances the tags in the queue upon completion of an executed instruction. The register file stores an instruction's information at a location in the register file defined by the tag assigned to that instruction. The register file also contains a plurality of read address enable ports and corresponding read output ports. Each of the slots from the queue is coupled to a corresponding one of the read address enable ports. Thus, the information for each instruction can be read out of the register file in program order.

60. 发明授权

US06272617B1 System and method for register renaming 失效
标题翻译：用于注册重命名的系统和方法
公开(公告)号：US06272617B1
公开(公告)日：2001-08-07
申请号：US09399000
申请日：1999-09-17
申请人： Trevor A. Deosaran , Sanjiv Garg , Kevin R. Iadonato
发明人： Trevor A. Deosaran , Sanjiv Garg , Kevin R. Iadonato
IPC分类号： G06F1500
CPC分类号： G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A tag is assigned to each instruction in the variable advance instruction window. The tag of each instruction to leave the window is assigned to the next new instruction to be added to it. The results of instructions executed by the processor are stored in a temp buffer according to their corresponding tags to avoid output and anti-dependencies. The temp buffer therefore permits the processor to execute instructions out of order and in parallel. Data dependency checks for input dependencies are performed only for each new instruction added to the variable advance instruction window and register renaming is performed to avoid input dependencies.
摘要翻译：一种用于在具有用于存储要由处理器执行的指令组的可变提前指令窗口的处理器中执行寄存器重命名源寄存器的系统和方法，其中当位置变得可用时将新指令添加到可变提前指令窗口。标签被分配给变量提前指令窗口中的每个指令。离开窗口的每个指令的标签被分配给要添加到其中的下一个新指令。由处理器执行的指令的结果根据其相应的标签存储在临时缓冲器中，以避免输出和反依赖。因此，临时缓冲器允许处理器按顺序并行执行指令。仅对添加到变量提前指令窗口的每个新指令执行输入相关性的数据依赖性检查，并执行寄存器重命名以避免输入依赖关系。

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