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51. 发明授权

US06469573B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US06469573B2
公开(公告)日：2002-10-22
申请号：US09731880
申请日：2000-12-08
申请人： Kazushige Kanda , Tamio Ikehashi , Ken Takeuchi , Kenichi Imamiya
发明人： Kazushige Kanda , Tamio Ikehashi , Ken Takeuchi , Kenichi Imamiya
IPC分类号： G05F110
CPC分类号： G11C7/062
摘要： A semiconductor integrated circuit includes a limiter circuit for outputting a voltage determining flag in order to set a boosted voltage level of a booster circuit to be a predetermined value, and a monitoring circuit for monitoring a monitoring node of the limiter circuit to output a monitoring signal for the stabilization of a boosted voltage to a first external terminal. The monitoring circuit detects a first level change of the voltage determining flag from “H” to “L” after the starting of the operation of the limiter circuit, by means of a comparator, to which an external power supply voltage and external reference voltage supplied from second and third external terminals are given, and thereafter, outputs a monitoring signal for holding a constant logical level during the operation of the limiter circuit. In order to provide a voltage trimming function, a voltage intended to be set in an external terminal may be given from the outside to deactivate a feedback system of the limiter circuit to operate a resistance value of the limiter circuit to detect and store a limiter flag. Thus, there is provided a semiconductor integrated circuit capable of simply monitoring the output voltage state of an internal power supply circuit by the external terminal and easily trimming an internal voltage.
摘要翻译：半导体集成电路包括限幅电路，用于输出电压确定标志，以便将升压电路的升压电压设定为预定值;以及监视电路，用于监视限幅器电路的监视节点以输出监视信号用于稳定第一外部端子的升压电压。监控电路通过比较器检测在限制器电路的操作开始之后电压确定标志从“H”到“L”的第一电平变化，供给外部电源电压和外部参考电压给出第二和第三外部端子，然后在限幅器电路的操作期间输出用于保持恒定逻辑电平的监视信号。为了提供电压调整功能，可以从外部给出旨在设置在外部端子中的电压以去激活限幅器电路的反馈系统，以操作限幅器电路的电阻值以检测和存储限幅器标志。因此，提供了能够简单地通过外部端子监视内部电源电路的输出电压状态并容易地修整内部电压的半导体集成电路。

52. 发明授权

US08315094B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US08315094B2
公开(公告)日：2012-11-20
申请号：US12957865
申请日：2010-12-01
申请人： Kazushige Kanda , Toshiki Hisada , Katsuaki Isobe
发明人： Kazushige Kanda , Toshiki Hisada , Katsuaki Isobe
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： Provided is a semiconductor memory device including: multiple bit lines arranged in parallel to one another; multiple sense-amplifier bit lines arranged away from end portions of the bit lines; a fourth sense-amplifier bit line formed with a wire of a first layer arranged below the bit lines; selection transistors with a pair of gate electrodes arranged in a direction normal to the first to sixth bit lines; a first wire arranged below the bit lines and the sense-amplifier bit lines, and having an end portion extending to below the third bit line and connected to the bit line; a third wire formed with a layer of the gate electrode used as a wire, the third wire including a first end portion positioned below the fourth sense-amplifier bit line and connected to the fourth sense-amplifier bit line, and a second end portion positioned below the second sense-amplifier bit line; and a fourth wire formed with a wire of the first layer and arranged between the third wire and the second sense-amplifier bit line to connect the third wire to the second sense-amplifier bit line.
摘要翻译：提供一种半导体存储器件，包括：彼此平行布置的多个位线; 多个读出放大器位线布置成远离位线的端部; 第四感测放大器位线，其布置在位线下方的第一层的导线; 选择晶体管，其具有沿与第一至第六位线垂直的方向排列的一对栅电极; 布置在位线下方的第一线和读出放大器位线，并且具有延伸到第三位线下方并连接到位线的端部; 第三线，其形成有用作线的栅极电极层，所述第三线包括位于所述第四感测放大器位线下方并连接到所述第四感测放大器位线的第一端部，以及位于低于第二感测放大器位线; 以及第四导线，其由第一层的导线形成，并且布置在第三导线和第二读出放大器位线之间，以将第三导线连接到第二感测放大器位线。

53. 发明授权

US08149638B2 Semiconductor memory device and inspecting method of the same 失效
标题翻译：半导体存储器件及其检测方法
公开(公告)号：US08149638B2
公开(公告)日：2012-04-03
申请号：US12884694
申请日：2010-09-17
申请人： Tomonori Kurosawa , Takahiko Sasaki , Kazushige Kanda
发明人： Tomonori Kurosawa , Takahiko Sasaki , Kazushige Kanda
IPC分类号： G11C7/00
CPC分类号： G11C29/02 , G11C11/16 , G11C29/025 , G11C2029/1204
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array includes memory cells, lines provided to correspond to the memory cells, a first decoder configured to select a first line as an inspection target from the lines, a second decoder configured to select a second line for generating a reference voltage from the lines, a driver configured to charge the first and second lines, a discharging circuit configured to simultaneously discharge the first and second lines, and a sense amplifier configured to compare a voltage of the first line with a voltage of the second line to detect a defect of the first line while the first line is discharged.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元阵列，其包括存储单元，提供用于对应于存储单元的线，第一解码器，被配置为从线选择第一行作为检查对象;第二解码器，被配置为选择用于从所述线路产生参考电压的第二线路，被配置为对所述第一和第二线路充电的驱动器，配置成同时对所述第一和第二线路进行放电的放电电路;以及读出放大器，被配置为将所述第一线路的电压与第一线的电压在第一线放电时检测第一线的缺陷。

54. 发明申请

US20110103135A1 NON-VOLATILE MEMORY DEVICE AND METHOD FOR WRITING DATA THERETO 有权
标题翻译：非易失性存储器件及其数据写入方法
公开(公告)号：US20110103135A1
公开(公告)日：2011-05-05
申请号：US13005582
申请日：2011-01-13
申请人： Toshiaki EDAHIRO , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
发明人： Toshiaki EDAHIRO , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/32 , G11C2213/72
摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.
摘要翻译：本发明提供一种将数据写入非易失性存储器件的方法，该非易失性存储器件具有彼此相交的第一布线和第二布线以及布置在其间的每个交叉处的存储单元，每个存储单元具有可变电阻元件和整流元件系列。根据该方法，在所选择的第一布线中升高之前，将第二布线充电至不小于整流元件阈值的一定电压。然后，将所选择的第一布线充电到写入或擦除所需的电压，之后放电所选择的第二布线。

55. 发明授权

US07646222B2 Semiconductor device for generating power on reset signal 失效
标题翻译：用于产生上电复位信号的半导体器件
公开(公告)号：US07646222B2
公开(公告)日：2010-01-12
申请号：US11376416
申请日：2006-03-16
申请人： Masaki Ichikawa , Kazushige Kanda
发明人： Masaki Ichikawa , Kazushige Kanda
IPC分类号： H03L7/00
CPC分类号： H03K17/223 , G06F1/24
摘要： A reference voltage generating circuit receives a power supply voltage and generates a reference voltage. A reference voltage level guarantee circuit generates a sense signal when the circuit senses that a value of the reference voltage has reached a predetermined value. A power supply voltage sensing circuit has a voltage comparator circuit which compares a voltage obtained by dividing a power supply voltage with the reference voltage and outputs a power ON reset signal. An operation of the voltage comparator circuit is controlled based on a sense signal. When the value of the power supply voltage increases and the value of the reference voltage reaches a predetermined value, the voltage comparator circuit operates, and a power ON reset signal is outputted in response to a result of comparison between a divisional voltage and the reference voltage.
摘要翻译：参考电压产生电路接收电源电压并产生参考电压。当电路感测到参考电压的值已经达到预定值时，参考电压电平保证电路产生感测信号。电源电压检测电路具有电压比较器电路，其将通过将电源电压分压获得的电压与参考电压进行比较，并输出电源接通复位信号。基于感测信号来控制电压比较器电路的操作。当电源电压值增加并且参考电压的值达到预定值时，电压比较器电路工作，并且响应于分压与参考电压之间的比较结果而输出电源复位信号。

56. 发明申请

US20090010039A1 NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20090010039A1
公开(公告)日：2009-01-08
申请号：US12132972
申请日：2008-06-04
申请人： Naoya Tokiwa , Kazushige Kanda , Toshiaki Edahiro , Koji Hosono , Takuya Futatsuyama , Shigeo Ohsima
发明人： Naoya Tokiwa , Kazushige Kanda , Toshiaki Edahiro , Koji Hosono , Takuya Futatsuyama , Shigeo Ohsima
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0097 , G11C2013/0092 , G11C2213/32 , G11C2213/72
摘要： According to one embodiment, a nonvolatile memory device includes: a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value; a first data latch storing write and erase data to be written on a given group of memory cells of the memory cell array for a write and erase operation; and a second data latch storing reference data for performing a compensation operation of the given group to compensate write and erase disturbance accompanied by the write or erase operation.
摘要翻译：根据一个实施例，非易失性存储器件包括：存储单元阵列，其包括各自具有用于非易失性地存储由电可重写电阻值识别的数据的可变电阻元件的存储单元; 存储要写入存储单元阵列的给定组的存储单元的用于写入和擦除操作的写入和擦除数据的第一数据锁存器; 以及第二数据锁存器，存储用于执行给定组的补偿操作以补偿伴随着写入或擦除操作的写入和擦除干扰的参考数据。

57. 发明申请

US20080291716A1 METHOD OF PROGRAMMING A NON-VOLATILE MEMORY DEVICE 有权
标题翻译：编程非易失性存储器件的方法
公开(公告)号：US20080291716A1
公开(公告)日：2008-11-27
申请号：US12123827
申请日：2008-05-20
申请人： Takuya Futatsuyama , Koji Hosono , Toshiaki Edahiro , Naoya Tokiwa , Kazushige Kanda , Shigeo Ohshima
发明人： Takuya Futatsuyama , Koji Hosono , Toshiaki Edahiro , Naoya Tokiwa , Kazushige Kanda , Shigeo Ohshima
IPC分类号： G11C11/00
CPC分类号： G11C11/36
摘要： A method of programming a non-volatile memory device with memory cells formed of variable resistance elements and disposed between word lines and bit lines, includes: previously charging a selected word line and a selected bit line together with a non-selected word line and a non-selected bit line up to a certain voltage; and further charging the selected word line and the non-selected bit line up to a program voltage higher than the certain voltage and a program-block voltage, respectively, and simultaneously discharging the selected bit line.
摘要翻译：一种使用由可变电阻元件形成并且设置在字线和位线之间的存储单元来编程非易失性存储器件的方法包括：预先对所选择的字线和所选择的位线以及未选择的字线和非选择位线达到一定电压; 并且进一步对所选字线和未选择的位线进行充电，直到分别高于特定电压和编程块电压的编程电压，并同时对所选择的位线进行放电。

58. 发明授权

US07428161B2 Semiconductor memory device with MOS transistors each having floating gate and control gate 失效
标题翻译：具有MOS晶体管的半导体存储器件分别具有浮动栅极和控制栅极
公开(公告)号：US07428161B2
公开(公告)日：2008-09-23
申请号：US11537880
申请日：2006-10-02
申请人： Kazushige Kanda
发明人： Kazushige Kanda
IPC分类号： G11C5/06 , G11C11/34 , G11C16/04 , G11C8/00
CPC分类号： G11C5/063 , G06F11/1068 , G11C16/24 , H01L27/115 , H01L27/11521
摘要： A semiconductor memory device includes memory cell arrays, word lines, bit lines, column gates, sense amplifiers, and an error correcting circuit. The memory cell array includes first regions and a second region. The first region includes first element isolating regions which have stripe shapes along the bit lines. The memory cell is formed on an element region between the adjacent element isolating regions. The first regions are arranged in plurality along the word line direction. The second region is provided adjacent to the first region in a direction along the word lines. The second region includes a second element isolating region whose width along the word line direction is greater than that of the first element isolating region. Addresses of the bit line adjacent to the second region are different from one another among the memory cell arrays.
摘要翻译：半导体存储器件包括存储单元阵列，字线，位线，列门，读出放大器和纠错电路。存储单元阵列包括第一区域和第二区域。第一区域包括沿着位线具有条纹形状的第一元件隔离区域。存储单元形成在相邻元件隔离区域之间的元件区域上。第一区域沿字线方向排列成多个。第二区域沿着字线的方向设置在第一区域附近。第二区域包括其沿着字线方向的宽度大于第一元件隔离区域的宽度的第二元件隔离区域。与第二区域相邻的位线的地址在存储单元阵列中彼此不同。

59. 发明申请

US20070206399A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20070206399A1
公开(公告)日：2007-09-06
申请号：US11682478
申请日：2007-03-06
申请人： Eiichi Makino , Koji Hosono , Kazushige Kanda , Shigeo Ohshima
发明人： Eiichi Makino , Koji Hosono , Kazushige Kanda , Shigeo Ohshima
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： G11C5/025 , G11C5/063 , G11C16/0483 , H01L2224/06155 , H01L2224/06156 , H01L2224/48227 , H01L2924/15311
摘要： A nonvolatile semiconductor memory device having a first memory cell array including a plurality of electrical reprogramming and erasable nonvolatile semiconductor memory cells formed in a first area of a semiconductor substrate, a second memory cell array including a plurality of electrical reprogramming and erasable nonvolatile semiconductor memory cells formed in a second area different from said first area of said semiconductor substrate, said first and second memory cell arrays being arranged in a first direction, and a first pad section for inputting data to and outputting data from said first memory cell array and said second memory cell array, said first pad section having a plurality of pads arranged between said first memory cell array and said second memory cell array along a second direction perpendicular to said first direction.
摘要翻译：一种具有第一存储单元阵列的非易失性半导体存储器件，包括形成在半导体衬底的第一区域中的多个电重新编程和可擦除非易失性半导体存储单元，第二存储单元阵列包括多个电重编程和可擦除非易失性半导体存储单元形成在与所述半导体衬底的所述第一区域不同的第二区域中，所述第一和第二存储单元阵列沿第一方向布置;以及第一焊盘区段，用于向所述第一存储单元阵列和所述第二存储单元阵列输入数据并输出数据所述第一焊盘部分具有沿垂直于所述第一方向的第二方向布置在所述第一存储单元阵列和所述第二存储单元阵列之间的多个焊盘。

60. 发明申请

US20060208777A1 Semiconductor device for generating power on reset signal 失效
标题翻译：用于产生上电复位信号的半导体器件
公开(公告)号：US20060208777A1
公开(公告)日：2006-09-21
申请号：US11376416
申请日：2006-03-16
申请人： Masaki Ichikawa , Kazushige Kanda
发明人： Masaki Ichikawa , Kazushige Kanda
IPC分类号： H03L7/00
CPC分类号： H03K17/223 , G06F1/24
摘要： A reference voltage generating circuit receives a power supply voltage and generates a reference voltage. A reference voltage level guarantee circuit generates a sense signal when the circuit senses that a value of the reference voltage has reached a predetermined value. A power supply voltage sensing circuit has a voltage comparator circuit which compares a voltage obtained by dividing a power supply voltage with the reference voltage and outputs a power ON reset signal. An operation of the voltage comparator circuit is controlled based on a sense signal. When the value of the power supply voltage increases and the value of the reference voltage reaches a predetermined value, the voltage comparator circuit operates, and a power ON reset signal is outputted in response to a result of comparison between a divisional voltage and the reference voltage.
摘要翻译：参考电压产生电路接收电源电压并产生参考电压。当电路感测到参考电压的值已经达到预定值时，参考电压电平保证电路产生感测信号。电源电压检测电路具有电压比较器电路，其将通过将电源电压分压获得的电压与参考电压进行比较，并输出电源接通复位信号。基于感测信号来控制电压比较器电路的操作。当电源电压值增加并且参考电压的值达到预定值时，电压比较器电路工作，并且响应于分压与参考电压之间的比较结果而输出电源复位信号。

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