专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US5742538A Long instruction word controlling plural independent processor operations 失效
公开(公告)号：US5742538A
公开(公告)日：1998-04-21
申请号：US632785
申请日：1996-04-15
申请人： Karl M. Guttag , Christopher J. Read , Keith Balmer
发明人： Karl M. Guttag , Christopher J. Read , Keith Balmer
IPC分类号： G06F7/52 , G06F7/57 , G06F9/30 , G06F9/302 , G06F9/315 , G06F9/38
CPC分类号： G06F7/53 , G06F7/57 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/3851 , G06F9/3853 , G06F9/3867 , G06F9/3885 , G06F2207/382
摘要： A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data. A single instruction controlling both the multiplier unit and the arithmetic logic unit permits addition of dual products. The dual products are temporarily stored in a data register permitting the multiply and add operations to be pipelined. The dual products are formed in one data word and added by a rotate/mask and add operation in a three input arithmetic unit.

52. 发明授权

US5727225A Method, apparatus and system forming the sum of data in plural equal sections of a single data word 失效
标题翻译：形成单个数据字的多个相等部分中的数据之和的方法，装置和系统
公开(公告)号：US5727225A
公开(公告)日：1998-03-10
申请号：US473380
申请日：1995-06-07
申请人： Karl M. Guttag , Christopher J. Read
发明人： Karl M. Guttag , Christopher J. Read
IPC分类号： G06F17/15 , G06F15/00
CPC分类号： G06F17/153
摘要： This invention is a technique for summing plural sections of a single data word. The technique uses a repeated process forming larger and larger partial sums. Initially the single data word is rotated one section. The original single data word and the rotated single data word are masked with a mask having "1's" and "0's" in alternate sections. The mask blocks alternate sections so that adjacent sections of the original data word may be summed on a whole data word basis without any overflow disrupting the partial products. The two masked data words are then summed. This sum results in half as many partial sums as before. Each of these larger partial sums now occupies two original sections of the data word. The process can be repeated for these large partial sums. In the preferred embodiment this technique is used with an arithmetic logic unit (230) capable of forming mixed arithmetic and Boolean combinations of three inputs having a barrel rotator (235) driving one input. The arithmetic logic unit (230) receives the single data word at a first input (241) and the rotated single data word at a second input (241). The mask supplies the third input (243). The arithmetic logic unit (230) then forms the combination (A&C)+(B&C), which is field addition of A and B as masked by C. With proper selection of the mask and the rotate amount, the three input arithmetic logic unit (230) forms the shift, mask and addition in a single cycle.
摘要翻译：本发明是用于求和单个数据字的多个部分的技术。该技术使用形成更大和更大部分和的重复过程。最初单个数据字被旋转一个部分。原始单个数据字和旋转的单个数据字在替代部分中具有“1”和“0”的掩码。掩模块替代部分，使得原始数据字的相邻部分可以在整个数据字的基础上求和，而不会使部分产物中断。然后将两个屏蔽的数据字相加。这个总和导致了与以前一样多的部分和。这些较大的部分和中的每一个现在占据数据字的两个原始部分。对于这些大的部分和可以重复该过程。在优选实施例中，该技术与能够形成具有驱动一个输入的桶旋转器（235）的三个输入的混合运算和布尔组合的算术逻辑单元（230）一起使用。算术逻辑单元（230）在第一输入（241）处接收单个数据字，并在第二输入（241）处接收旋转的单个数据字。掩模提供第三个输入（243）。算术逻辑单元（230）然后形成组合（A＆C）+（B＆C），其是由C屏蔽的A和B的场相加。通过适当地选择掩模和旋转量，三输入算术逻辑单元 230）在单个周期中形成移位，掩码和加法。

53. 发明授权

US5724599A Message passing and blast interrupt from processor 失效
标题翻译：来自处理器的消息传递和爆炸中断
公开(公告)号：US5724599A
公开(公告)日：1998-03-03
申请号：US208171
申请日：1994-03-08
申请人： Keith Balmer , Karl M. Guttag , Robert J. Gove , Nicholas Ing-Simmons , Iain Robertson
发明人： Keith Balmer , Karl M. Guttag , Robert J. Gove , Nicholas Ing-Simmons , Iain Robertson
IPC分类号： G06F15/00 , G06F15/16
CPC分类号： G06F15/16
摘要： The invention involves communication within a multiprocessor system. The multiprocessor system includes a command word bus and a plurality of data processors. Each data processor is connected to the command word bus and includes a command circuit, a decoder and a reset control circuit. The command circuit may generate a command word on the command word bus including at least one reset command word for resetting a data processor. The decoder decodes command words received via the command word bus and includes at least a reset command decoder for decoding a reset command word. The reset control circuit resets the data processor into a state corresponding to initial application of electrical power upon receiving a reset command word. Each command word circuit generates command words indicating a particular data processor to which it is directed. Only a predetermined subset of the data processors may send the reset command word directed to other data processors. Additional actions such as interrupts, halt and cache memory flush may be controlled via the command word. In the preferred embodiment, a single command word may be directed to plural data processors. In the preferred embodiment, the command word bus and each of the data processors are disposed on a single semiconductor chip.
摘要翻译：本发明涉及多处理器系统内的通信。多处理器系统包括命令字总线和多个数据处理器。每个数据处理器连接到命令字总线，并包括命令电路，解码器和复位控制电路。命令电路可以在命令字总线上生成包括用于复位数据处理器的至少一个复位命令字的命令字。解码器解码通过命令字总线接收的命令字，并且至少包括用于对复位命令字进行解码的复位命令解码器。复位控制电路在接收到复位命令字时将数据处理器复位为与初始施加电力相对应的状态。每个命令字电路产生指示其所针对的特定数据处理器的命令字。只有数据处理器的预定子集可以发送定向到其他数据处理器的复位命令字。可以通过命令字来控制诸如中断，停止和高速缓冲存储器刷新等附加动作。在优选实施例中，单个命令字可以被引导到多个数据处理器。在优选实施例中，命令字总线和每个数据处理器设置在单个半导体芯片上。

54. 发明授权

US5696959A Memory store from a selected one of a register pair conditional upon the state of a selected status bit 失效
标题翻译：存储器根据所选状态位的状态从寄存器对中选定的一个存储器存储
公开(公告)号：US5696959A
公开(公告)日：1997-12-09
申请号：US478129
申请日：1995-06-07
申请人： Karl M. Guttag , Sydney W. Poland , Keith Balmer
发明人： Karl M. Guttag , Sydney W. Poland , Keith Balmer
IPC分类号： G06T1/60 , G06F9/302 , G06F9/312 , G06F9/318 , G06F9/32 , G06F9/34 , G06F9/38 , G06F12/08
CPC分类号： G06F9/30101 , G06F9/30014 , G06F9/30036 , G06F9/30043 , G06F9/30094 , G06F9/30167 , G06F9/30189 , G06F9/30192 , G06F9/34 , G06F9/3842
摘要： A memory store operation comes from one of a pair of registers selected by an arithmetic logic unit condition. An instruction logic circuit (250, 660) controls an addressing circuit (120) to store data in a first register into memory if a selected status bit has a first state and to store data in a second register associated with the first register into memory if the selected status bit has a second state in response to a register pair conditional store instruction. The bits may indicate a negative output of the arithmetic logic unit (230), a carry out signal, an overflow, or a zero output. The register pair conditional store instruction designates a particular one of the status bits to control the conditional store. The instruction logic circuit (250, 660) substitutes the selected status bit for a least significant bit of the register number. Thus memory store is from the first register if the status bit is "1" and is from the second register if the status bit is "0". In a further embodiment the register pair conditional write instruction is conditional. The write operation aborts if the designated condition is true. In the preferred embodiment of this invention, the arithmetic logic unit (230), the status register (210), the data registers (200) and the instruction decode logic (250, 660) are embodied in at least one digital image/graphics processor (71) as a part of a multiprocessor formed in a single integrated circuit (100) used in image processing.
摘要翻译：存储器存储操作来自由算术逻辑单元条件选择的一对寄存器之一。如果选择的状态位具有第一状态并且将与第一寄存器相关联的第二寄存器中的数据存储到存储器中，则指令逻辑电路（250,660）控制寻址电路（120）将第一寄存器中的数据存储到存储器中，如果所选状态位响应于寄存器对条件存储指令具有第二状态。这些位可以指示算术逻辑单元（230）的负输出，进位信号，溢出或零输出。寄存器对条件存储指令指定用于控制条件存储的特定一个状态位。指令逻辑电路（250,660）将选择的状态位替换为寄存器编号的最低有效位。因此，如果状态位为“1”，则存储器来自第一寄存器，如果状态位为“0”，则来自第二寄存器。在另一实施例中，寄存器对条件写指令是有条件的。如果指定的条件为真，则写入操作中止。在本发明的优选实施例中，算术逻辑单元（230），状态寄存器（210），数据寄存器（200）和指令解码逻辑（250,660）被体现在至少一个数字图像/图形处理器（71）作为在图像处理中使用的单个集成电路（100）中形成的多处理器的一部分。

55. 发明授权

US5640578A Arithmetic logic unit having plural independent sections and register storing resultant indicator bit from every section 失效
标题翻译：具有多个独立部分的算术逻辑单元和从每个部分存储结果指示符位的寄存器
公开(公告)号：US5640578A
公开(公告)日：1997-06-17
申请号：US158742
申请日：1993-11-30
申请人： Keith Balmer , Nicholas Ing-Simmons , Karl M. Guttag , Robert J. Gove , Jeremiah E. Golston , Christopher J. Read , Sydney W. Poland
发明人： Keith Balmer , Nicholas Ing-Simmons , Karl M. Guttag , Robert J. Gove , Jeremiah E. Golston , Christopher J. Read , Sydney W. Poland
IPC分类号： G06F3/153 , G06F7/575 , G06F9/302 , G06F9/318 , G06F9/32 , G06F12/08 , G06T1/00 , G06T1/20 , G06T11/00 , G09G5/39 , H04N1/387 , G06F7/38 , G06F7/50
CPC分类号： G06F7/575 , G06F9/30014 , G06F9/30036 , G06F9/30094 , G06F9/30189 , G06F9/30192 , G06F2207/382 , G06F2207/3828 , G06F7/49905
摘要： An arithmetic logic unit (230) may be divided into a plurality of independent sections (301, 302, 303, 340). A bit zero of carry status signal corresponding to each section that is stored in a flags register (211), which preferably includes more bits than the maximum number of sections of the arithmetic logic unit (230). New status signals may overwrite the previous status signals or rotate the stored bits and store the new status signals. A status register (210) stores a size indicator that determines the a number of sections of the arithmetic logic unit (230). A status detector has a zero detector (321, 322, 323, 324) for each elementary section (301, 302, 303, 304) of the arithmetic logic unit (230). When there are fewer than the maximum number of sections, these zero signals are ANDed (331, 332, 341). A multiplexer couples the carry-out of an elementary (311, 312, 313, 314) to the carry-in of an adjacent elementary section (301, 302, 303, 304) or not depending on the selected number of sections. The status detector supplies carry outs from each elementary section (301, 302, 303, 304) not coupled to an adjacent elementary section (301, 302, 303, 304) to the flags register (211). Status signals stored in the flags register (211) influence the combination of inputs formed by the arithmetic logic unit (230) within corresponding sections. An expand circuit (238) expands selected bits of flags register (211) to form a third input to a three input arithmetic logic unit (230).
摘要翻译：算术逻辑单元（230）可以被划分为多个独立部分（301,302,303,340）。对应于存储在标志寄存器（211）中的每个部分的进位状态信号的位零，其优选地包括比算术逻辑单元（230）的最大部分数量多的位。新的状态信号可以覆盖先前的状态信号或旋转存储的比特并存储新的状态信号。状态寄存器（210）存储确定算术逻辑单元（230）的段数的大小指示符。状态检测器对于算术逻辑单元（230）的每个基本部分（301,302,303,304）具有零检测器（321,322,323,324）。当小于最大数量的部分时，这些零信号为“与”（331,332,341）。多路复用器将基本（311,312,313,314）的进位输出耦合到相邻基本部分（301,302,303,304）的进位，或者不依赖于所选择的部分数量。状态检测器从没有耦合到相邻基本部分（301,302,303,304）的每个基本部分（301,302,303,304）提供进位到标志寄存器（211）。存储在标志寄存器（211）中的状态信号影响由相应部分内的算术逻辑单元（230）形成的输入的组合。扩展电路（238）扩展标志寄存器（211）的所选位以形成三输入算术逻辑单元（230）的第三输入。

56. 发明授权

US5606520A Address generator with controllable modulo power of two addressing capability 失效
标题翻译：地址发生器具有两种寻址能力的可控模数功率
公开(公告)号：US5606520A
公开(公告)日：1997-02-25
申请号：US484540
申请日：1995-06-07
申请人： Robert J. Gove , Karl M. Guttag , Keith Balmer , Nicholas K. Ing-Simmons
发明人： Robert J. Gove , Karl M. Guttag , Keith Balmer , Nicholas K. Ing-Simmons
IPC分类号： G06F15/167 , G06F12/02 , G06F12/06 , G06F15/173 , G06F15/80 , G06F7/38 , G06F12/00
CPC分类号： G06F15/17375 , G06F12/0284
摘要： A data processing address generator includes a plurality of address registers, a plurality of index address registers, a modulo register storing a plurality of carry break indicators and an arithmetic unit. The arithmetic unit adds or subtracts a selected address register and a selected index register. The arithmetic unit generates a normal carry between a particular bit and the next more significant bit if a corresponding carry break indicator stored in said modulo register has a first digital state. The arithmetic unit breaks any carry between the particular bit and the next more significant bit if the corresponding carry break indicator has a second digital state. The carry break may be dependent upon a modulo qualifier bit being in an enabling state. The modulo qualifier bit may be stored in one of a plurality of qualifier registers corresponding to the address registers.
摘要翻译：数据处理地址生成器包括多个地址寄存器，多个索引地址寄存器，存储多个进位断点指示符的模数寄存器和运算单元。算术单元增加或减少选定的地址寄存器和选定的索引寄存器。如果存储在所述模数寄存器中的对应进位断点指示符具有第一数字状态，则运算单元在特定位和下一更高有效位之间产生正常进位。如果相应的进位断点指示符具有第二数字状态，运算单元将特定位和下一个更高有效位之间的任何进位断开。进位中断可以取决于模数限定位位于使能状态。模数限定符位可以存储在与地址寄存器对应的多个限定符寄存器之一中。

57. 发明授权

US5537563A Devices, systems and methods for accessing data using a gun preferred data organization 失效
标题翻译：使用枪优选数据组织访问数据的设备，系统和方法
公开(公告)号：US5537563A
公开(公告)日：1996-07-16
申请号：US018487
申请日：1993-02-16
申请人： Karl M. Guttag , Robert J. Gove , Richard Simpson
发明人： Karl M. Guttag , Robert J. Gove , Richard Simpson
IPC分类号： G09G5/39 , G06F13/00
CPC分类号： G09G5/39 , G09G2352/00
摘要： A processing system operates on data words each having first and second portions. A first memory stores the first portion of a first data word accessible by a first set of address bits received at first address inputs and a second set of address bits received at second address inputs, and stores the second portion of a second word accessible by the first set of address bits received at the first address inputs and a third set of address bits received at the second address inputs. A second memory stores the first portion of the second data word accessible by a first set of address bits received at first address inputs and a second set of bits received at second address input, and stores the second portion of the first word accessible by the first set of address bits received at the first address inputs and a third set of address bits received at the second address inputs. A first access mode accesses a selected one of the first and second portions of both the first and second words. A second access mode accesses both the first and second portions of a selected one of the first and second words.
摘要翻译：处理系统对每个具有第一和第二部分的数据字进行操作。第一存储器存储由在第一地址输入处接收的第一组地址位可访问的第一数据字的第一部分和在第二地址输入处接收的第二组地址位，并且存储由第二地址位可访问的第二字的第二部分在第一地址输入处接收的第一组地址位和在第二地址输入处接收的第三组地址位。第二存储器存储由在第一地址输入处接收的第一组地址位可访问的第二数据字的第一部分和在第二地址输入处接收到的第二组位，并且存储由第一地址输入可访问的第一字的第二部分在第一地址输入处接收的一组地址位和在第二地址输入处接收的第三组地址位。第一访问模式访问第一和第二单词的第一和第二部分中的所选择的一个。第二访问模式访问第一和第二单词中所选择的一个的第一和第二部分。

58. 发明授权

US5522082A Graphics display processor, a graphics display system and a method of processing graphics data with control signals connected to a central processing unit and graphics circuits 失效
标题翻译：图形显示处理器，图形显示系统以及连接到中央处理单元和图形电路的控制信号处理图形数据的方法
公开(公告)号：US5522082A
公开(公告)日：1996-05-28
申请号：US965561
申请日：1992-10-23
申请人： Karl M. Guttag , Kevin C. McDonough , Sergio Maggi
发明人： Karl M. Guttag , Kevin C. McDonough , Sergio Maggi
IPC分类号： G06F9/30 , G06T1/20 , G06F9/00
CPC分类号： G06F9/30 , G06T1/20
摘要： The present invention is a programmable data processing system and apparatus which operates as an independent microprocessor. The programmable data processing system of the present invention stores both general purpose and special purpose graphic instructions. The programmable data processing apparatus of the present invention has both types of instructions within its instruction set. This provision of a single processing apparatus for preforming both types of instructions enables a highly flexible solution to bit map graphics problems. This is because the program of the data processing apparatus may be altered to provide the most desirable graphics algorithm without loss of the general purpose calculation and program flow capability of a general purpose data processor. The data processor of the present invention may serve as a parallel processor for a host data processing system for primarily control of bit mapped graphics. In addition this same type data processing apparatus may serve as an independent microprocessor within a single user computer or graphics terminal.
摘要翻译：本发明是作为独立微处理器工作的可编程数据处理系统和装置。本发明的可编程数据处理系统存储通用和专用图形指令。本发明的可编程数据处理装置在其指令集内具有两种类型的指令。提供用于预处理两种类型的指令的单个处理装置使得能够高度灵活地解决图形问题的位图。这是因为可以改变数据处理装置的程序以提供最理想的图形算法，而不会损失通用数据处理器的通用计算和程序流能力。本发明的数据处理器可以用作用于主要控制位映射图形的主机数据处理系统的并行处理器。此外，该相同类型的数据处理装置可以在单个用户计算机或图形终端内用作独立的微处理器。

59. 发明授权

US5471592A Multi-processor with crossbar link of processors and memories and method of operation 失效
标题翻译：具有处理器和存储器的交叉连接的多处理器和操作方法
公开(公告)号：US5471592A
公开(公告)日：1995-11-28
申请号：US263504
申请日：1994-06-21
申请人： Robert J. Gove , Karl M. Guttag , Keith Balmer , Nicholas K. Ing-Simmons
发明人： Robert J. Gove , Karl M. Guttag , Keith Balmer , Nicholas K. Ing-Simmons
IPC分类号： G06F15/167 , G06F12/02 , G06F12/06 , G06F15/173 , G06F15/80 , G06F13/00
CPC分类号： G06F15/17375 , G06F12/0284
摘要： There is disclosed a multiprocessor system and method arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories, are contained on a single silicon chip.
摘要翻译：公开了一种在一个实施例中将图像和图形处理器设置为多处理器系统和方法。该处理器由多个单独的处理器构成，所有处理器都具有到几个存储器的通信链路，而不受限制。交叉开关用于建立处理器存储器链路，并且整个图像处理器（包括各个处理器，交叉开关和存储器）都包含在单个硅芯片上。

60. 发明授权

US5398316A Devices, systems and methods for accessing data using a pixel preferred data organization 失效
标题翻译：使用像素优先数据组织访问数据的设备，系统和方法
公开(公告)号：US5398316A
公开(公告)日：1995-03-14
申请号：US17566
申请日：1993-02-16
申请人： Karl M. Guttag , Richard D. Simpson , Robert J. Gove
发明人： Karl M. Guttag , Richard D. Simpson , Robert J. Gove
IPC分类号： G06T1/60 , G06F15/62
CPC分类号： G06T1/60
摘要： A processing system operating on data words having first and second portions includes a memory bank comprising first and second memories each with associated first and second set of address inputs. First memory includes a first storage location storing the first portion of a first word accessible by a set of address bits received at the first inputs and a second set of address bits received at the second inputs. The first memory further includes a second storage location storing the second portion of a second word accessible by the first set of bits received at the first inputs and a third set of bits received at the second inputs. Second memory includes a first storage location storing the second portion of the second word accessible by the first set of bits received at the first inputs and the second set of bits received at the second inputs. Second memory has a second storage location storing the first portion of the second word accessible by the first inputs and the third set of bits received at the second inputs. Processing system includes a processor operating in a first mode to access a selected one of the first and second words and in a second mode to access a selected one of the first and second portions of both the first and second words.
摘要翻译：对具有第一和第二部分的数据字操作的处理系统包括存储器组，其包括第一和第二存储器，每个存储器具有相关联的第一和第二组地址输入。第一存储器包括存储第一字的第一部分的第一存储位置，该第一字可由在第一输入处接收的一组地址位可访问，以及在第二输入处接收的第二组地址位。第一存储器还包括第二存储位置，存储由在第一输入处接收的第一组位可访问的第二字的第二部分和在第二输入处接收的第三组位。第二存储器包括存储第二字的第二部分的第一存储位置，该第二字可由在第一输入处接收的第一组位和第二输入端接收的第二组位可访问。第二存储器具有存储由第一输入可访问的第二字的第一部分和在第二输入处接收的第三组位的第二存储位置。处理系统包括以第一模式操作的处理器，以访问第一和第二字中的所选择的一个，并且以第二模式访问第一和第二字的第一和第二部分中的所选择的一个。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式