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51. 发明授权

US08492280B1 Method for simultaneously forming features of different depths in a semiconductor substrate 失效
标题翻译：同时形成半导体衬底中不同深度的特征的方法
公开(公告)号：US08492280B1
公开(公告)日：2013-07-23
申请号：US13465050
申请日：2012-05-07
申请人： Habib Hichri , Xi Li , Richard S. Wise
发明人： Habib Hichri , Xi Li , Richard S. Wise
IPC分类号： H01L21/311
CPC分类号： H01L21/3065 , H01L21/76229 , H01L21/84 , H01L27/1087 , H01L29/66181
摘要： Embodiments of the invention may include first providing a stack of layers including a semiconductor substrate, a buried oxide layer on the semiconductor substrate, a semiconductor-on-insulator layer on the buried-oxide layer, a nitride layer on the semiconductor-on-insulator layer, and a silicon oxide layer on the nitride layer. A first opening and second opening with a smaller cross-sectional area than the first opening are then formed in the silicon oxide layer, the nitride layer, the semiconductor-on-insulator layer, and the buried-oxide layer. The first opening and the second opening are then etched with a first etching gas. The first opening and the second opening are then etched with a second etching gas, which includes the first etching gas and a halogenated silicon compound, for example, silicon tetrafluoride or silicon tetrachloride. In one embodiment, the first etching gas includes hydrogen bromide, nitrogen trifluoride, and oxygen.
摘要翻译：本发明的实施例可以包括首先提供包括半导体衬底，半导体衬底上的掩埋氧化物层，掩埋氧化物层上的绝缘体上半导体层，绝缘体上半导体上的氮化物层层和氮化物层上的氧化硅层。然后在氧化硅层，氮化物层，绝缘体上半导体层和掩埋氧化物层上形成具有比第一开口更小的横截面面积的第一开口和第二开口。然后用第一蚀刻气体蚀刻第一开口和第二开口。然后用第二蚀刻气体蚀刻第一开口和第二开口，第二蚀刻气体包括第一蚀刻气体和卤化硅化合物，例如四氟化硅或四氯化硅。在一个实施方案中，第一蚀刻气体包括溴化氢，三氟化氮和氧。

52. 发明授权

US08165928B2 Managing events within supply chain networks 有权
标题翻译：管理供应链网络中的事件
公开(公告)号：US08165928B2
公开(公告)日：2012-04-24
申请号：US09919567
申请日：2001-07-30
申请人： John J. Dooley , Xi Li
发明人： John J. Dooley , Xi Li
IPC分类号： G06Q10/00
CPC分类号： G06Q10/08 , G06K2017/0045 , G06Q10/06 , G06Q10/0637 , G06Q10/087 , G06Q20/203 , G06Q20/208
摘要： A supply chain network system comprises a site data appliance (SDA) and a Universal Data Appliance Protocol (UDAP) adapter coupled with one or more data source equipments (DSE). The SDA collects specification information comprising event information from the one or more DSE. A server is coupled with the SDA in the supply chain network. In response to the server requesting the specification information, the SDA sends to the server the specification information in a Description Document. A data center (DC) is coupled with the server in the supply chain network. The DC receives the Description Document and maps the event information in the specification information with event handlers. A mapping of the event information with the event handlers is sent from the DC to the server. When an event is generated by the one or more DSE, the map is used to select an appropriate event handler to execute.
摘要翻译：供应链网络系统包括与一个或多个数据源设备（DSE）耦合的站点数据设备（SDA）和通用数据设备协议（UDAP）适配器。 SDA从一个或多个DSE收集包括事件信息的规范信息。服务器与供应链网络中的SDA配合使用。响应于请求规范信息的服务器，SDA向服务器发送描述文档中的规范信息。数据中心（DC）与供应链网络中的服务器相连。 DC接收描述文档，并使用事件处理程序将规范信息中的事件信息映射。将事件信息与事件处理程序的映射从DC发送到服务器。当一个或多个DSE生成事件时，该映射用于选择要执行的适当的事件处理程序。

53. 发明授权

US07683416B2 Post STI trench capacitor 失效
标题翻译：后STI沟槽电容器
公开(公告)号：US07683416B2
公开(公告)日：2010-03-23
申请号：US11935698
申请日：2007-11-06
申请人： Anil K. Chinthakindi , Deok-kee Kim , Xi Li
发明人： Anil K. Chinthakindi , Deok-kee Kim , Xi Li
IPC分类号： H01L27/108
CPC分类号： H01L29/94 , H01L28/91 , H01L29/66181
摘要： A design structure for capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.
摘要翻译：在由诸如凹陷隔离或浅沟槽隔离的隔离结构限定的沟槽中形成用于去耦应用的适当大值的电容器的设计结构。电容器提供与有源区域共同延伸的接触区域，并且可以单独或少量可靠地形成。板触点优选通过延伸到形成电容器板的掺杂剂扩散区域之间或之间的注入区域制成。可以通过形成隔离结构之后的过程形成电容器，使得可以使用优选的软掩模工艺来形成隔离结构和工艺共同性，并避免兼容性约束，同时电容器形成过程可以与其他处理共同执行结构。

54. 发明授权

US07682922B2 Post STI trench capacitor 失效
标题翻译：后STI沟槽电容器
公开(公告)号：US07682922B2
公开(公告)日：2010-03-23
申请号：US11624385
申请日：2007-01-18
申请人： Anil K. Chinthakindi , Deok-Kee Kim , Xi Li
发明人： Anil K. Chinthakindi , Deok-Kee Kim , Xi Li
IPC分类号： H01L21/20
CPC分类号： H01L29/94 , H01L27/0805 , H01L28/91 , H01L29/66181
摘要： A capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.
摘要翻译：在由诸如凹陷隔离或浅沟槽隔离的隔离结构限定的沟槽中形成具有用于去耦应用的适当大值的电容器。电容器提供与有源区域共同延伸的接触区域，并且可以单独或少量可靠地形成。板触点优选通过延伸到形成电容器板的掺杂剂扩散区域之间或之间的注入区域制成。可以通过形成隔离结构之后的过程形成电容器，使得可以使用优选的软掩模工艺来形成隔离结构和工艺共同性，并避免兼容性约束，同时电容器形成过程可以与其他处理共同执行结构。

55. 发明申请

US20080173918A1 Post STI Trench Capacitor 失效
标题翻译：后STI沟槽电容器
公开(公告)号：US20080173918A1
公开(公告)日：2008-07-24
申请号：US11935698
申请日：2007-11-06
申请人： Anil K. Chinthakindi , Deok-kee Kim , Xi Li
发明人： Anil K. Chinthakindi , Deok-kee Kim , Xi Li
IPC分类号： H01L29/94
CPC分类号： H01L29/94 , H01L28/91 , H01L29/66181
摘要： A design structure for capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.
摘要翻译：在由诸如凹陷隔离或浅沟槽隔离的隔离结构限定的沟槽中形成用于去耦应用的适当大值的电容器的设计结构。电容器提供与有源区域共同延伸的接触区域，并且可以单独或少量可靠地形成。板触点优选通过延伸到形成电容器板的掺杂剂扩散区域之间或之间的注入区域制成。可以通过形成隔离结构之后的过程形成电容器，使得可以使用优选的软掩模工艺来形成隔离结构和工艺共同性，并避免兼容性约束，同时电容器形成过程可以与其他处理共同执行结构。

56. 外观设计

USD1043848S1 Toy 有权
公开(公告)号：USD1043848S1
公开(公告)日：2024-09-24
申请号：US29845064
申请日：2022-07-05
申请人： Xi Li
设计人： Xi Li
摘要： FIG. 1 is a first perspective view of a toy showing my new design;
FIG. 2 is a second perspective view thereof;
FIG. 3 is a front view thereof;
FIG. 4 is a back view thereof;
FIG. 5 is a left side view thereof;
FIG. 6 is a right side view thereof;
FIG. 7 is a top view thereof;
FIG. 8 is a bottom view thereof;
FIG. 9 is another perspective view thereof, but shown in a usage state in an environmental view;
FIG. 10 is an enlarged view of the selected portion 10 in FIG. 1;
FIG. 11 is an enlarged view of the selected portion 11 in FIG. 1;
FIG. 12 is an enlarged view of the selected portion 12 in FIG. 1;
FIG. 13 is an enlarged view of the selected portion 13 in FIG. 1; and,
FIG. 14 is an enlarged view of the selected portion 14 in FIG. 1.
The broken lines illustrate portions of the toy that form no part of the claimed design. In FIG. 9 the additional broken lines illustrate environmental structure that form no part of the claim.

57. 发明申请

US20170352019A1 METHOD AND SYSTEM FOR EFFICIENT SHARED TRANSACTION PROCESSING 审中-公开
公开(公告)号：US20170352019A1
公开(公告)日：2017-12-07
申请号：US15170669
申请日：2016-06-01
申请人： Xi Li , Weilong Liu , Mo Yang , Yun Luo , Santosh Lachhman Achhra , Anandan Ethirkottai Sundararajan , Haochuan Zhang
发明人： Xi Li , Weilong Liu , Mo Yang , Yun Luo , Santosh Lachhman Achhra , Anandan Ethirkottai Sundararajan , Haochuan Zhang
IPC分类号： G06Q20/22 , G06Q50/00 , H04L12/58 , H04L29/08
CPC分类号： G06Q20/29 , G06Q20/14 , G06Q20/32 , G06Q20/3276 , G06Q50/01 , H04L12/185 , H04L51/04 , H04L67/1044 , H04W4/08 , H04W4/50
摘要： One embodiment of the invention is directed to a method comprising, receiving, by a server computer, a request to establish a group identifier for a group. A group identifier is generated for the group. Group invitations to join the group are transmitted and group invitation responses are received. The method further comprises receiving, by the server computer, confirmations to share a group transaction. A plurality of messages are initiated, the plurality of messages corresponding to the plurality of confirmations, where the plurality of messages result in an initiation of a single message to a third-party, the third-party computer being configured to conduct the group transaction according the single message.

58. 发明申请

US20130295773A1 Method for Simultaneously Forming Features of Different Depths in a Semiconductor Substrate 有权
标题翻译：同时形成半导体基板中不同深度特征的方法
公开(公告)号：US20130295773A1
公开(公告)日：2013-11-07
申请号：US13865223
申请日：2013-04-18
申请人： Habib Hichri , Xi Li , Richard Wise
发明人： Habib Hichri , Xi Li , Richard Wise
IPC分类号： H01L21/3065
CPC分类号： H01L21/3065 , H01L21/76229 , H01L21/84 , H01L27/1087 , H01L29/66181
摘要： Embodiments of the invention may include first providing a stack of layers including a semiconductor substrate, a buried oxide layer on the semiconductor substrate, a semiconductor-on-insulator layer on the buried-oxide layer, a nitride layer on the semiconductor-on-insulator layer, and a silicon oxide layer on the nitride layer. A first opening and second opening with a smaller cross-sectional area than the first opening are then formed in the silicon oxide layer, the nitride layer, the semiconductor-on-insulator layer, and the buried-oxide layer. The first opening and the second opening are then etched with a first etching gas. The first opening and the second opening are then etched with a second etching gas, which includes the first etching gas and a halogenated silicon compound, for example, silicon tetrafluoride or silicon tetrachloride. In one embodiment, the first etching gas includes hydrogen bromide, nitrogen trifluoride, and oxygen.
摘要翻译：本发明的实施例可以包括首先提供包括半导体衬底，半导体衬底上的掩埋氧化物层，掩埋氧化物层上的绝缘体上半导体层，绝缘体上半导体上的氮化物层层和氮化物层上的氧化硅层。然后在氧化硅层，氮化物层，绝缘体上半导体层和掩埋氧化物层上形成具有比第一开口更小的横截面面积的第一开口和第二开口。然后用第一蚀刻气体蚀刻第一开口和第二开口。然后用第二蚀刻气体蚀刻第一开口和第二开口，第二蚀刻气体包括第一蚀刻气体和卤化硅化合物，例如四氟化硅或四氯化硅。在一个实施方案中，第一蚀刻气体包括溴化氢，三氟化氮和氧。

59. 发明授权

US08299573B2 Trench capacitor 失效
标题翻译：沟槽电容器
公开(公告)号：US08299573B2
公开(公告)日：2012-10-30
申请号：US12818448
申请日：2010-06-18
申请人： Chengwen Pei , Xi Li , Geng Wang
发明人： Chengwen Pei , Xi Li , Geng Wang
IPC分类号： H01L21/02
CPC分类号： H01L29/945 , H01L21/3065 , H01L27/1087 , H01L29/36 , H01L29/66181
摘要： A trench and method of fabrication is disclosed. The trench shape is cylindrosymmetric, and is created by forming a dopant profile that is monotonically increasing in dopant concentration level as a function of depth into the substrate. A dopant sensitive etch is then performed, resulting in a trench shape providing increased surface area, yet having relatively smooth trench walls.
摘要翻译：公开了一种沟槽和制造方法。沟槽形状是圆柱对称的，并且通过形成掺杂剂分布而形成，掺杂剂分布随掺杂剂浓度水平而单调增加，作为进入衬底的深度的函数。然后进行掺杂剂敏感蚀刻，导致沟槽形状提供增加的表面积，但具有相对平滑的沟槽壁。

60. 发明授权

US08278164B2 Semiconductor structures and methods of manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08278164B2
公开(公告)日：2012-10-02
申请号：US12700059
申请日：2010-02-04
申请人： Xi Li , Viorel C. Ontalus
发明人： Xi Li , Viorel C. Ontalus
IPC分类号： H01L21/336
CPC分类号： H01L29/165 , H01L21/302 , H01L29/1608 , H01L29/161 , H01L29/78 , H01L29/7827
摘要： A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures.
摘要翻译：半导体结构具有用于增强晶体管性能的嵌入式应力源材料。形成半导体结构的方法包括在一个或多个栅极结构下蚀刻衬底材料中的底切，同时用衬垫材料保护植入物。该方法还包括移除在植入物侧面上的衬垫材料并且在一个或多个栅极结构下的底切中沉积应力源材料。

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