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51. 发明申请

US20130134498A1 MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20130134498A1
公开(公告)日：2013-05-30
申请号：US13304380
申请日：2011-11-24
申请人： Shih-Guei Yan , Wen-Jer Tsai , Cheng-Hsien Cheng
发明人： Shih-Guei Yan , Wen-Jer Tsai , Cheng-Hsien Cheng
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/66833 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/7881 , H01L29/792
摘要： A memory device is described, including a tunnel dielectric layer over a substrate, a gate over the tunnel dielectric layer, at least one charge storage layer between the gate and the tunnel dielectric layer, two doped regions in the substrate beside the gate, and a word line that is disposed on and electrically connected to the gate and has a thickness greater than that of the gate.
摘要翻译：描述了存储器件，包括衬底上的隧道介电层，隧道介电层上的栅极，栅极和隧道介电层之间的至少一个电荷存储层，栅极旁边的衬底中的两个掺杂区域，以及字线，其设置在栅极上并电连接到栅极并且具有大于栅极的厚度的厚度。

52. 发明授权

US08399326B2 Method of manufacturing memory devices 有权
标题翻译：制造存储器件的方法
公开(公告)号：US08399326B2
公开(公告)日：2013-03-19
申请号：US12785500
申请日：2010-05-24
申请人： Ta-Wei Lin , Wen-Jer Tsai
发明人： Ta-Wei Lin , Wen-Jer Tsai
IPC分类号： H01L21/336 , H01L21/311
CPC分类号： H01L29/7841 , H01L27/108 , H01L27/10802
摘要： Disclosed is a memory device and method of operation thereof. The memory device may include a source region and a drain region of a first dopant type, the source and drain regions contain a first semiconductor material; a body region of a second dopant type, the body region being sandwiched between the source and drain regions, the body comprising a second semiconductor material; a gate dielectric layer over at least the body region; and a gate comprising a conductive material over the gate dielectric layer. Specifically, one of the first semiconductor material and the second semiconductor material is lattice matched with the other of the first semiconductor material and the second semiconductor material and has an energy gap smaller than the energy gap of the other of the first semiconductor material and the second semiconductor material.
摘要翻译：公开了一种存储装置及其操作方法。存储器件可以包括第一掺杂剂类型的源极区域和漏极区域，源极区域和漏极区域包含第一半导体材料; 所述主体区域被夹在所述源极和漏极区域之间，所述主体包括第二半导体材料; 至少在所述身体区域上的栅介电层; 以及包括在所述栅极介电层上的导电材料的栅极。具体地，第一半导体材料和第二半导体材料之一与第一半导体材料和第二半导体材料中的另一个晶格匹配，并且具有小于第一半导体材料和第二半导体材料中的另一个的能隙的能隙半导体材料。

53. 发明授权

US07750368B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US07750368B2
公开(公告)日：2010-07-06
申请号：US12139418
申请日：2008-06-13
申请人： Ta-Wei Lin , Wen-Jer Tsai
发明人： Ta-Wei Lin , Wen-Jer Tsai
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7841 , H01L27/108 , H01L27/10802
摘要： Disclosed is a memory device and method of operation thereof. The memory device may include a source region and a drain region of a first dopant type, the source and drain regions contain a first semiconductor material; a body region of a second dopant type, the body region being sandwiched between the source and drain regions, the body comprising a second semiconductor material; a gate dielectric layer over at least the body region; and a gate comprising a conductive material over the gate dielectric layer. Specifically, one of the first semiconductor material and the second semiconductor material is lattice matched with the other of the first semiconductor material and the second semiconductor material and has an energy gap smaller than the energy gap of the other of the first semiconductor material and the second semiconductor material.
摘要翻译：公开了一种存储装置及其操作方法。存储器件可以包括第一掺杂剂类型的源极区域和漏极区域，源极区域和漏极区域包含第一半导体材料; 所述主体区域被夹在所述源极和漏极区域之间，所述主体包括第二半导体材料; 至少在所述身体区域上的栅介电层; 以及包括在所述栅极介电层上的导电材料的栅极。具体地，第一半导体材料和第二半导体材料之一与第一半导体材料和第二半导体材料中的另一个晶格匹配，并且具有小于第一半导体材料和第二半导体材料中的另一个的能隙的能隙半导体材料。

54. 发明申请

US20100035389A1 Dynamic Random Access Memory Cell and Manufacturing Method Thereof 有权
标题翻译：动态随机存取存储器单元及其制造方法
公开(公告)号：US20100035389A1
公开(公告)日：2010-02-11
申请号：US12570147
申请日：2009-09-30
申请人： Ta-Wei Lin , Wen-Jer Tsai
发明人： Ta-Wei Lin , Wen-Jer Tsai
IPC分类号： H01L21/8242
CPC分类号： H01L27/10802 , H01L21/84 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： A dynamic random access memory cell and a manufacturing method thereof are provided. First, a substrate on which a bottom oxide layer and a semiconductor layer are formed is provided. The semiconductor layer is formed on the bottom oxide layer. Next, a gate is formed on the semiconductor layer. Then, the semiconductor layer is patterned to expose a portion of the bottom oxide layer. Afterwards, an insulation layer is formed at the side walls of the semiconductor layer, wherein the height of the insulation layer is shorter than that of the semiconductor layer, so that a gap is formed between the tops of the insulation layer and the semiconductor layer. Further, a doping layer covering the insulation layer and having the same height with the semiconductor layer is formed on the bottom oxide layer. The doping layer contacts the side walls of the semiconductor layer via the gap.
摘要翻译：提供了一种动态随机存取存储单元及其制造方法。首先，提供形成有底部氧化物层和半导体层的基板。半导体层形成在底部氧化物层上。接下来，在半导体层上形成栅极。然后，对半导体层进行图案化以暴露底部氧化物层的一部分。之后，在半导体层的侧壁形成绝缘层，其中绝缘层的高度比半导体层的高度短，从而在绝缘层的顶部和半导体层之间形成间隙。此外，在底部氧化物层上形成覆盖绝缘层并且与半导体层具有相同高度的掺杂层。掺杂层经由间隙与半导体层的侧壁接触。

55. 发明申请

US20080144371A1 SYSTEMS AND METHODS FOR PROGRAMMING A MEMORY DEVICE 有权
标题翻译：用于编程存储器件的系统和方法
公开(公告)号：US20080144371A1
公开(公告)日：2008-06-19
申请号：US12018709
申请日：2008-01-23
申请人： Chih-Chieh Yeh , Wen-Jer Tsai , Yi-Ying Liao
发明人： Chih-Chieh Yeh , Wen-Jer Tsai , Yi-Ying Liao
IPC分类号： G11C16/10 , G11C16/06
CPC分类号： G11C16/0475 , G11C11/5671 , G11C16/0483 , G11C2211/5621
摘要： A multi-Level Cell (MLC) can be used to store, for example, 4 bits per cell by storing two bits on each of two sides. Each side can store, e.g., four different current level states that can be determined by the number of holes injected into, e.g., nitride layer, during programming. As more holes are injected the current decreases for a given voltage. The current can be low, therefore, it can be advantageous in one embodiment to use a current amplifier. The current amplifier can be a BJT, MOS or other type of device.
摘要翻译：多级单元（MLC）可用于通过在两侧存储两位来存储例如每单元4位。每一侧都可以存储例如四个不同的电流状态，这些状态可以通过在编程期间注入到例如氮化物层中的空穴的数量来确定。随着更多的孔被注入，给定电压的电流减小。电流可能很低，因此，在一个实施例中使用电流放大器可能是有利的。电流放大器可以是BJT，MOS或其他类型的器件。

56. 发明授权

US06822910B2 Non-volatile memory and operating method thereof 有权
标题翻译：非易失性存储器及其操作方法
公开(公告)号：US06822910B2
公开(公告)日：2004-11-23
申请号：US10248220
申请日：2002-12-29
申请人： Wen-Jer Tsai , Chih-Chieh Yeh , Tao-Cheng Lu
发明人： Wen-Jer Tsai , Chih-Chieh Yeh , Tao-Cheng Lu
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0466
摘要： A non-volatile memory device is described, comprising a plurality of memory cells, a plurality of word lines, a plurality of drain lines, and a plurality of source lines, wherein two adjacent memory cells in a column constitute a cell pair, and all cell pairs are arranged in rows and columns. The two memory cells in each cell pair share a source region, and two adjacent cell pairs in a column share a drain region. The source regions and the gates of the memory cells in the same row are coupled to a source line and a word line, respectively, and the drain regions of the memory cells in the same column are coupled to a drain line.
摘要翻译：描述了一种非易失性存储器件，其包括多个存储器单元，多个字线，多个漏极线和多个源极线，其中列中的两个相邻的存储器单元构成一个单元对，并且全部单元对以行和列排列。每个单元对中的两个存储单元共享源区，并且列中的两个相邻单元对共享漏区。相同行中的存储单元的源极区域和栅极分别耦合到源极线和字线，并且同一列中的存储器单元的漏极区域耦合到漏极线。

57. 发明授权

US06649971B1 Nitride read-only memory cell for improving second-bit effect and method for making thereof 有权
标题翻译：用于改善第二位效应的氮化物只读存储单元及其制造方法
公开(公告)号：US06649971B1
公开(公告)日：2003-11-18
申请号：US10064905
申请日：2002-08-28
申请人： Yen-Hung Yeh , Wen-Jer Tsai , Mu-Yi Liu , Kwang-Yang Chan , Tso-Hung Fan , Tao-Cheng Lu
发明人： Yen-Hung Yeh , Wen-Jer Tsai , Mu-Yi Liu , Kwang-Yang Chan , Tso-Hung Fan , Tao-Cheng Lu
IPC分类号： H01L29788
CPC分类号： H01L29/7923
摘要： A NROM cell for reducing for reducing the second-bit effect is described. The NORM cell of the present invention is formed with a substrate, a silicon oxide/silicon nitride/silicon oxide (ONO) layer disposed on the substrate, a gate disposed on the silicon oxide/silicon nitride/silicon oxide layer, source/drain regions configured in the substrate beside the gate, and a shallow pocket doped region configured between the source/drain regions and the ONO layer beside the gate. The depth of the shallow pocket doped region is sufficiently small to prevent interference to the current flow that travels to the source/drain regions.
摘要翻译：描述了用于降低第二位效应的NROM单元。本发明的NORM单元由衬底，设置在衬底上的氧化硅/氮化硅/氧化硅（ONO）层，设置在氧化硅/氮化硅/氧化硅层上的栅极，源/漏区配置在栅极旁边的衬底中，以及配置在源极/漏极区域和栅极旁边的ONO层之间的浅阱掺杂区域。浅阱掺杂区域的深度足够小，以防止对流向源极/漏极区域的电流的干扰。

58. 发明授权

US06646924B1 Non-volatile memory and operating method thereof 有权
标题翻译：非易失性存储器及其操作方法
公开(公告)号：US06646924B1
公开(公告)日：2003-11-11
申请号：US10064642
申请日：2002-08-02
申请人： Wen-Jer Tsai , Chih-Chieh Yeh , Tao-Cheng Lu
发明人： Wen-Jer Tsai , Chih-Chieh Yeh , Tao-Cheng Lu
IPC分类号： G11C1604
CPC分类号： H01L29/7885 , G11C16/0475 , H01L27/115
摘要： A non-volatile memory is described, which comprises a plurality of memory cells, a plurality of word lines, a plurality of drain lines and a plurality of source lines. Two adjacent memory cells in the same row share a source and are grouped into a cell pair, and all of the cell pairs are arranged in rows and columns, wherein two cell pairs in the same row share a drain. The sources of the memory cells in the same row are connected to a source line, and the drains of the memory cells in the same row are connected to a drain line. The gates of the memory cells in the same column are coupled to a word line.
摘要翻译：描述了一种非易失性存储器，其包括多个存储器单元，多个字线，多个漏极线和多个源极线。同一行中的两个相邻的存储单元共享一个源并将其分组成一个单元对，并且所有的单元对排列成行和列，其中同一行中的两个单元对共享一个漏极。同一行中的存储单元的源极连接到源极线，并且同一行中的存储器单元的漏极连接到漏极线。同一列中的存储单元的栅极耦合到字线。

59. 发明授权

US06614694B1 Erase scheme for non-volatile memory 有权
标题翻译：非易失性存储器的擦除方案
公开(公告)号：US06614694B1
公开(公告)日：2003-09-02
申请号：US10112707
申请日：2002-04-02
申请人： Chih-Chieh Yeh , Wen-Jer Tsai , Tao-Cheng Lu
发明人： Chih-Chieh Yeh , Wen-Jer Tsai , Tao-Cheng Lu
IPC分类号： G11C1604
CPC分类号： G11C16/3404 , A61K31/365 , G11C16/0475 , G11C16/3418
摘要： A method of an erase scheme for a non-volatile memory cell. The non-volatile memory cell includes a substrate, source, drain with a channel region and a gate above the channel region separated by nonconducting charge-trapping material sandwiched between first and second insulating layers. The method includes the following steps. First, hot hole erase is performed to inject hot holes into the nonconducting charge-trapping material to eliminate first electrons trapped in the nonconducting charge-trapping material and causing some holes to remain in the second insulating layer. Finally, soft anneal is performed to inject second electrons to the second insulating layer to eliminate the holes left in the second insulating layer.
摘要翻译：一种用于非易失性存储单元的擦除方案的方法。非易失性存储单元包括具有沟道区的衬底，源极，漏极以及夹在第一和第二绝缘层之间的由不导电的电荷俘获材料隔开的沟道区上方的栅极。该方法包括以下步骤。首先，进行热孔擦除以将热空穴注入到不导电的电荷捕获材料中，以消除捕获在不导电的电荷捕获材料中的第一电子，并使一些孔留在第二绝缘层中。最后，进行软退火以将第二电子注入第二绝缘层以消除留在第二绝缘层中的孔。

60. 发明授权

US06445614B1 Accelerated testing method and circuit for non-volatile memory 有权
标题翻译：非易失性存储器的加速测试方法和电路
公开(公告)号：US06445614B1
公开(公告)日：2002-09-03
申请号：US09930745
申请日：2001-08-14
申请人： Wen-Jer Tsai , Nian-Kai Zous , Ta-Hui Wang
发明人： Wen-Jer Tsai , Nian-Kai Zous , Ta-Hui Wang
IPC分类号： G11C1606
CPC分类号： G11C29/50004 , G11C16/04 , G11C29/50 , G11C2029/1202
摘要： An accelerated test for a non-volatile memory. A threshold voltage variation standard for assessment is selected. A set of negative gate bias voltages is applied to the gate terminals of the non-volatile memory to conduct the accelerated testing and obtain a test result. A curve relating lifetime and negative gate bias voltage is derived from the test result. According to the threshold voltage variation standard, the lifetime of the non-volatile memory is found. A word line negative gate bias voltage generator is coupled to a word line driver to apply a set of negative gate bias voltages to the gate terminals of programmed memory cells and conduct an accelerated testing.
摘要翻译：非易失性存储器的加速测试。选择用于评估的阈值电压变化标准。一组负栅极偏置电压施加到非易失性存储器的栅极端子，以进行加速测试并获得测试结果。从测试结果得出相关寿命和负栅极偏置电压的曲线。根据阈值电压变化标准，找到非易失性存储器的寿命。字线负栅极偏置电压发生器耦合到字线驱动器以将一组负栅极偏置电压施加到编程的存储器单元的栅极端子并进行加速测试。

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