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    • 53. 发明授权
    • Integrated injection logic with both grid and internal double-diffused
injectors
    • 集成注入逻辑与电网和内部双扩散注射器
    • US4119998A
    • 1978-10-10
    • US815768
    • 1977-07-14
    • Yukuya TokumaruMasanori NakaiSatoshi ShinozakiJunichi NakamuraShintaro ItoYoshio Nishi
    • Yukuya TokumaruMasanori NakaiSatoshi ShinozakiJunichi NakamuraShintaro ItoYoshio Nishi
    • H01L27/02H01L27/04
    • H01L27/0233
    • An integrated injection logic semiconductor device is composed of an N type semiconductor substrate, a P type layer, a first N type region so formed as to penetrate through the P type semiconductor layer and contact the N type semiconductor substrate, a second N type region formed in the P type semiconductor layer, and a P type region formed in the first N type region. A third N type region is provided surrounding said first and second N type regions and penetrating through the P type semiconductor layer. I.sup.2 L circuit is composed of a lateral PNP transistor whose emitter, base and collector are constituted by said P type region, said first N type region and said P type semiconductor layer, respectively, and a vertical NPN transistor whose emitter, base and collector are constituted by said N type semiconductor substrate, said P type semiconductor layer and said second N type region, respectively.
    • 集成注入逻辑半导体器件由N型半导体衬底,P型层,形成为穿透P型半导体层并接触N型半导体衬底的第一N型区域构成,形成第二N型区域 在P型半导体层中形成的P型区域和形成在第一N型区域中的P型区域。 围绕所述第一和第二N型区域并穿过P型半导体层设置第三N型区域。 I2L电路由发射极,基极和集电极分别由所述P型区域,所述第一N型区域和所述P型半导体层分别构成的横向PNP晶体管和其发射极,基极和集电极构成的垂直NPN晶体管构成 分别由所述N型半导体衬底,所述P型半导体层和所述第二N型区域。
    • 54. 发明授权
    • I.I.L. with graded base inversely operated transistor
    • 一, 具有分级基极反向操作晶体管
    • US4064526A
    • 1977-12-20
    • US644048
    • 1975-12-24
    • Yukuya TokumaruMasanori NakaiSatoshi ShinozakiJunichi NakamuraShintaro ItoYoshio Nishi
    • Yukuya TokumaruMasanori NakaiSatoshi ShinozakiJunichi NakamuraShintaro ItoYoshio Nishi
    • H01L27/082H01L21/331H01L21/8226H01L27/02H01L29/73H01L27/04H01L29/36H01L29/72
    • H01L27/0237Y10S148/085Y10S148/087Y10S148/167
    • An integrated injection logic semiconductor device comprises an N type semiconductor substrate, a P type semiconductor layer laminated on said semiconductor substrate, and N type first region formed in a manner penetrating through said P type semiconductor layer to reach said N type semiconductor substrate, a first P type region formed in said first N type region, a second N type regionformed in said P type semiconductor layer, and a second P type region formed between said second N type region and said N type semiconductor substrate in a manner connected directly to said N type semiconductor substrate. An integrated injection logic circuit is comprised of a lateral NPN transistor whose emitter, base and collector are constituted by said first P type region, first N type region and P type semiconductor layer, respectively, and a vertical PNP transistor whose emitter, base and collector are constituted by said N type semiconductor substrate, P type semiconductor layer plus second P type region, and second N type region, respectively.
    • 一种集成注入逻辑半导体器件,包括N型半导体衬底,层叠在所述半导体衬底上的P型半导体层和以穿过所述P型半导体层的方式形成以到达所述N型半导体衬底的N型第一区域,第一 形成在所述第一N型区域中的P型区域,形成在所述P型半导体层中的第二N型区域和形成在所述第二N型区域和所述N型半导体衬底之间的第二P型区域, 型半导体衬底。 集成注入逻辑电路由横向NPN晶体管组成,其发射极,基极和集电极分别由所述第一P型区域,第一N型区域和P型半导体层构成,垂直PNP晶体管的发射极,基极和集电极 分别由所述N型半导体衬底,P型半导体层加上第二P型区域和第二N型区域构成。