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51. 发明申请

US20080288849A1 Apparatus for generating soft decision values and method thereof 有权
标题翻译：用于产生软判决值的装置及其方法
公开(公告)号：US20080288849A1
公开(公告)日：2008-11-20
申请号：US11978569
申请日：2007-10-30
申请人： Sung Chung Park , Jun Jin Kong , Seung Jae Lee , Seung-Hwan Song
发明人： Sung Chung Park , Jun Jin Kong , Seung Jae Lee , Seung-Hwan Song
IPC分类号： H03M13/45 , G06F11/00
CPC分类号： H04L25/067 , H04L27/06 , H04L27/22
摘要： According to an example embodiment, a method of generating a soft decision value using an Analog-to-Digital Converter (ADC) having a given resolution may include receiving metric values calculated based on levels of a transmission signal and output levels of the ADC. Metric values corresponding to a level of a received signal may be selected from among the received metric values. A first maximum metric value may be detected from among the selected metric values when a transmission bit is a first level, and a second maximum metric value may be detected from among the selected metric values when the transmission bit is a second level. The soft decision value may be generated based on a difference between the first maximum metric value and the second maximum metric value.
摘要翻译：根据示例实施例，使用具有给定分辨率的模数转换器（ADC）产生软判决值的方法可以包括基于传输信号的电平和ADC的输出电平来计算的度量值。可以从接收到的度量值中选择与接收信号的电平对应的度量值。当传输位是第一级时，可以从选择的度量值中检测第一最大度量值，并且当传输位是第二级时，可以从所选择的度量值中检测第二最大度量值。可以基于第一最大度量值和第二最大度量值之间的差异来生成软判决值。

52. 发明授权

US09280287B2 Method of compressing data and device for performing the same 有权
标题翻译：压缩数据的方法和执行该数据的装置
公开(公告)号：US09280287B2
公开(公告)日：2016-03-08
申请号：US14135628
申请日：2013-12-20
申请人： Man Keun Seo , Dae Wook Kim , Hong Rak Son , Jun Jin Kong
发明人： Man Keun Seo , Dae Wook Kim , Hong Rak Son , Jun Jin Kong
IPC分类号： G06F13/00 , G06F13/38 , G06F3/06 , H03M7/30
CPC分类号： G06F3/0608 , G06F3/0641 , G06F3/0655 , G06F3/0673 , G06F3/0679 , H03M7/3086 , H03M7/6082
摘要： A data compression method includes receiving an input data stream including a previous data block and a current data block, and executing a first comparison of a part of the previous data block with part of a previous reference data block, and a second comparison of the current data block with a current reference data block, where the first and second comparisons are executed in parallel. The method further includes selectively, based on results of the first and second comparisons, outputting the current data block or compressing an extended data block, where the extended data block includes the part of the previous data block and the current data block.
摘要翻译：数据压缩方法包括接收包括先前数据块和当前数据块的输入数据流，并且执行先前数据块的一部分与先前参考数据块的一部分的第一比较，以及当前具有当前参考数据块的数据块，其中第一和第二比较并行执行。该方法还包括基于第一和第二比较的结果选择性地输出当前数据块或压缩扩展数据块，其中扩展数据块包括先前数据块的一部分和当前数据块。

53. 发明授权

US08635509B2 Method of operating memory controller and memory system including the memory controller 失效
标题翻译：操作存储器控制器和存储器系统的方法，包括存储器控制器
公开(公告)号：US08635509B2
公开(公告)日：2014-01-21
申请号：US13612074
申请日：2012-09-12
申请人： Seong Hyeog Choi , Jun Jin Kong , Hong Rak Son
发明人： Seong Hyeog Choi , Jun Jin Kong , Hong Rak Son
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： G06F11/1072 , G06F11/108 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00
摘要： According to example embodiments, a method of controlling a memory controller includes executing an error correction code (ECC) on first page data that has been read from a non-volatile memory device using a first read voltage level, estimating a second read voltage level for reading the first page data using metadata of second page data when an uncorrectable error is detected in the first page data according to a result of executing the ECC.
摘要翻译：根据示例实施例，一种控制存储器控制器的方法包括：对使用第一读取电压电平从非易失性存储器件读取的第一页数据执行纠错码（ECC），估计第二读取电压电平根据执行ECC的结果在第一页数据中检测到不可校正的错误时，使用第二页数据的元数据读取第一页数据。

54. 发明授权

US08607118B2 Iterative decoding method and apparatus 有权
标题翻译：迭代解码方法和装置
公开(公告)号：US08607118B2
公开(公告)日：2013-12-10
申请号：US12475640
申请日：2009-06-01
申请人： Jong Seon No , Beom Kyu Shin , Seok Il Youn , Jae Dong Yang , Jun Jin Kong , Jae Hong Kim , Yong June Kim , Kyoung Lae Cho
发明人： Jong Seon No , Beom Kyu Shin , Seok Il Youn , Jae Dong Yang , Jun Jin Kong , Jae Hong Kim , Yong June Kim , Kyoung Lae Cho
IPC分类号： H03M13/00
CPC分类号： H03M13/1105 , H03M13/136 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/2906 , H03M13/3738 , H03M13/3753 , H04L1/0051 , H04L1/0057
摘要： An iterative decoding method is disclosed and includes sequentially executing a number of iterative decoding cycles in relation to a parity check equation until the parity check equation is resolved, or a maximum number N of iterative decoding cycles is reached, during execution of the number of iterative decoding cycles, storing in a data buffer minimum estimated values for a set of variable nodes corresponding to a minimum number of bit errors, and outputting the minimum estimated values stored in the data buffer as a final decoding result when the number of iterative decoding cycles reaches N.
摘要翻译：公开了一种迭代解码方法，并且包括相对于奇偶校验方程顺序执行多个迭代解码周期，直到奇偶校验方程被解析为止，或者在迭代次数的执行期间达到迭代解码周期的最大数量N 解码周期，在数据缓冲器中存储对应于最小数量的位错误的一组可变节点的最小估计值，并且当迭代解码周期数达到时，输出存储在数据缓冲器中的最小估计值作为最终解码结果 N.

55. 发明授权

US08305818B2 Memory device and method for estimating characteristics of multi-bit programming 有权
标题翻译：用于估计多位编程特性的存储器件和方法
公开(公告)号：US08305818B2
公开(公告)日：2012-11-06
申请号：US13303353
申请日：2011-11-23
申请人： Kyoung Lae Cho , Seung-Hwan Song , Yoon Dong Park , Jun Jin Kong , Jae-Hong Kim
发明人： Kyoung Lae Cho , Seung-Hwan Song , Yoon Dong Park , Jun Jin Kong , Jae-Hong Kim
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/32 , G11C16/349 , G11C29/00 , G11C2211/5634
摘要： Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states selected from a plurality of threshold voltage states corresponding to data stored in the multi-bit cell array; and an estimation unit to estimate a threshold voltage change over time values for the plurality of threshold voltage states based on the extracted threshold voltage change. Through this, it is possible to monitor a change over time of threshold voltages of a memory cell.
摘要翻译：提供了可以估计多位单元特性的存储器件和/或方法。存储器设备可以包括：多位单元阵列; 监测单元，用于提取从对应于存储在多位单元阵列中的数据的多个阈值电压状态中选择的参考阈值电压状态的时间值的阈值电压变化; 以及估计单元，用于基于所提取的阈值电压变化来估计所述多个阈值电压状态的时间值的阈值电压变化。由此，可以监视存储单元的阈值电压随时间的变化。

56. 发明授权

US08281217B2 Memory devices and encoding and/or decoding methods 有权
标题翻译：存储器件和编码和/或解码方法
公开(公告)号：US08281217B2
公开(公告)日：2012-10-02
申请号：US12379746
申请日：2009-02-27
申请人： Yong June Kim , Jae Hong Kim , Jun Jin Kong
发明人： Yong June Kim , Jae Hong Kim , Jun Jin Kong
IPC分类号： G11C29/00
CPC分类号： H03M13/2903 , G06F11/1072 , H03M13/29 , H03M13/353
摘要： Memory devices and/or encoding/decoding methods are provided. A memory device may include: a memory cell array; an internal decoder configured to apply, to a first codeword read from the memory cell array, a first decoding scheme selected based on a characteristic of a first channel in which the first codeword is read to perform error control codes (ECC) decoding of the first codeword, and apply, to a second codeword read from the memory cell array, a second decoding scheme selected based on a characteristic of a second channel in which the second codeword is read to perform the ECC decoding of the second codeword; and an external decoder configured to apply an external decoding scheme to the ECC-decoded first codeword and the ECC-decoded second codeword to perform the ECC decoding of the first codeword and the second codeword.
摘要翻译：提供存储器件和/或编码/解码方法。存储器件可以包括：存储器单元阵列; 内部解码器，被配置为向从存储器单元阵列读取的第一代码字应用基于第一通道的特性选择的第一解码方案，其中读取第一代码字以执行第一代码字的错误控制代码（ECC）解码代码字，并且应用于从存储单元阵列读取的第二码字，基于第二通道的特性选择的第二解码方案，其中读取第二码字以执行第二码字的ECC解码; 以及外部解码器，被配置为将外部解码方案应用于ECC解码的第一码字和ECC解码的第二码字，以执行第一码字和第二码字的ECC解码。

57. 发明申请

US20120069654A1 MEMORY DEVICE AND METHOD FOR ESTIMATING CHARACTERISTICS OF MULTI-BIT PROGRAMMING 有权
标题翻译：用于估计多位编程特性的存储器件和方法
公开(公告)号：US20120069654A1
公开(公告)日：2012-03-22
申请号：US13303353
申请日：2011-11-23
申请人： Kyoung Lae CHO , Seung-Hwan Song , Yoong Dong Park , Jun Jin Kong , Jae Hong Kim
发明人： Kyoung Lae CHO , Seung-Hwan Song , Yoong Dong Park , Jun Jin Kong , Jae Hong Kim
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/32 , G11C16/349 , G11C29/00 , G11C2211/5634
摘要： Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states selected from a plurality of threshold voltage states corresponding to data stored in the multi-bit cell array; and an estimation unit to estimate a threshold voltage change over time values for the plurality of threshold voltage states based on the extracted threshold voltage change. Through this, it is possible to monitor a change over time of threshold voltages of a memory cell.
摘要翻译：提供了可以估计多位单元特性的存储器件和/或方法。存储器设备可以包括：多位单元阵列; 监测单元，用于提取从对应于存储在多位单元阵列中的数据的多个阈值电压状态中选择的参考阈值电压状态的时间值的阈值电压变化; 以及估计单元，用于基于所提取的阈值电压变化来估计所述多个阈值电压状态的时间值的阈值电压变化。由此，可以监视存储单元的阈值电压随时间的变化。

58. 发明申请

US20120020156A1 METHOD FOR PROGRAMMING NON-VOLATILE MEMORY DEVICE AND APPARATUSES PERFORMING THE METHOD 有权
标题翻译：编程非易失性存储器件的方法及其方法
公开(公告)号：US20120020156A1
公开(公告)日：2012-01-26
申请号：US13190913
申请日：2011-07-26
申请人： Seong Hyeog Choi , Hong Rak Son , Jun Jin Kong , Yong June Kim
发明人： Seong Hyeog Choi , Hong Rak Son , Jun Jin Kong , Yong June Kim
IPC分类号： G11C16/10
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10
摘要： A method of programming multi-level cells included in a spare region, the method including programming first page data and at least one first dummy data in a first multi-level cell; and programming second page data and at least one second dummy data in a second multi-level cell.
摘要翻译：一种对包含在备用区域中的多级单元进行编程的方法，所述方法包括在第一多级单元中编程第一页数据和至少一个第一虚拟数据; 以及在第二多级单元中编程第二页数据和至少一个第二伪数据。

59. 发明申请

US20110249495A1 NON-VOLATILE MEMORY DEVICE, OPERATION METHOD THEREOF, AND DEVICES HAVING THE NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件，其操作方法和具有非易失性存储器件的器件
公开(公告)号：US20110249495A1
公开(公告)日：2011-10-13
申请号：US13071727
申请日：2011-03-25
申请人： Kyoung Lae Cho , Hyuck-Sun Kwon , Jun Jin Kong
发明人： Kyoung Lae Cho , Hyuck-Sun Kwon , Jun Jin Kong
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/3454
摘要： A non-volatile memory device is provided. The non-volatile memory device includes a memory cell array including a plurality of multi-level cells each storing data corresponding to one of a plurality of states of a first group of states, and a control circuit. The control circuit configured to program data corresponding to one of the plurality of states in a first multi-level cell according to a first verify voltage level of a first group of verify voltage levels, and to control the first multi-level cell to be re-programmed to one of a plurality of states of a second group of states according to a first verify voltage level of a second group of verify voltage levels. Each voltage level of the second group of verify voltage levels has a higher level than the verify voltage levels of the first group of verify voltage levels. One of the plurality of states of the second group of states includes at least one of the plurality of states of the first group of states.
摘要翻译：提供了一种非易失性存储器件。非易失性存储器件包括存储单元阵列，其包括多个多电平单元，每个多电平单元存储与第一组状态的多个状态中的一个对应的数据，以及控制电路。控制电路被配置为根据第一组验证电压电平的第一验证电压电平对第一多电平单元中的多个状态中的一个状态进行编程的数据，并且控制第一多电平单元被重新根据第二验证电压电平组的第一验证电压电平编程为第二组状态的多个状态中的一个状态。第二组验证电压电平的每个电压电平具有比第一组验证电压电平的验证电压电平更高的电平。第二组状态的多个状态之一包括第一组状态的多个状态中的至少一个状态。

60. 发明授权

US08004891B2 Memory device and method of programming thereof 有权
标题翻译：存储器件及其编程方法
公开(公告)号：US08004891B2
公开(公告)日：2011-08-23
申请号：US12453964
申请日：2009-05-28
申请人： Yong June Kim , Kyoung Lae Cho , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
发明人： Yong June Kim , Kyoung Lae Cho , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C7/1006
摘要： Example embodiments may provide a memory device and memory data programming method. The memory device according to example embodiments may encode a first data page to generate at least one first codeword and encode a second data page to generate a second codeword. The memory device may generate the first codeword with at least one of a maximum value of a number of successive ones and a second maximum value of a number of successive zeros. The memory device may program the at least one first codeword and the at least one second codeword to a plurality of multi-bit cells.
摘要翻译：示例性实施例可以提供存储器设备和存储器数据编程方法。根据示例性实施例的存储器件可编码第一数据页以产生至少一个第一码字，并对第二数据页进行编码以产生第二码字。存储器装置可以利用连续零个数的最大值和连续零数的第二最大值中的至少一个来生成第一码字。存储器件可以将至少一个第一代码字和至少一个第二代码字编程到多个多位单元。

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