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51. 发明授权

US6084264A Trench MOSFET having improved breakdown and on-resistance characteristics 有权
标题翻译：沟槽MOSFET具有改进的击穿和导通电阻特性
公开(公告)号：US6084264A
公开(公告)日：2000-07-04
申请号：US200197
申请日：1998-11-25
申请人： Mohamed N. Darwish
发明人： Mohamed N. Darwish
IPC分类号： H01L21/336 , H01L29/06 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/113 , H01L31/119 , H01L31/062
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/1095 , H01L29/7813 , H01L29/0615 , H01L29/0878 , H01L29/0886
摘要： A trench MOSFET is formed in a structure which includes a P-type epitaxial layer overlying an N+ substrate. An N drain region is implanted through the bottom of the trench into the P-epitaxial layer, and after a diffusion step extends between the N+ substrate and the bottom of the trench. The junction between the N drain region and the P-epitaxial layer extends between the N+ substrate and a sidewall of the trench. In some embodiments the epitaxial layer can have a stepped doping concentration or a threshold voltage adjust implant can be added. Alternatively, the drain region can be omitted, and the trench can extend all the way through the P-epitaxial layer into the N+ substrate. A MOSFET constructed in accordance with this invention can have a reduced threshold voltage and on-resistance and an increased punchthrough breakdown voltage.
摘要翻译：在包括覆盖在N +衬底上的P型外延层的结构中形成沟槽MOSFET。通过沟槽的底部将N沟道区域注入到P外延层中，并且在扩散步骤在N +衬底和沟槽的底部之间延伸。 N漏极区和P-外延层之间的结在N +衬底和沟槽的侧壁之间延伸。在一些实施例中，外延层可以具有阶梯式掺杂浓度，或者可以添加阈值电压调整植入物。或者，可以省略漏极区，并且沟槽可以一直延伸穿过P外延层进入N +衬底。根据本发明构造的MOSFET可以具有降低的阈值电压和导通电阻以及增加的穿通击穿电压。

52. 发明授权

US5016076A Lateral MOS controlled thyristor 失效
标题翻译：横向MOS控制晶闸管
公开(公告)号：US5016076A
公开(公告)日：1991-05-14
申请号：US486459
申请日：1990-02-28
申请人： Mohamed N. Darwish
发明人： Mohamed N. Darwish
IPC分类号： H01L29/74 , H01L29/745 , H01L29/749
CPC分类号： H01L29/749 , H01L29/7455
摘要： A lateral MOS-controlled thyristor (MCT) structure using a single MOS gate for both turn-on and turn off. By eliminating a parasitic lateral PNP transistor through the addition of a high resistivity region surrounding one output terminal, and adding a DMOS transistor to a conventional thyristor structure, the maximum turn-off current limit is increased with lower forward voltage drop than that available in prior art lateral MCTs.

53. 发明授权

US08330214B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08330214B2
公开(公告)日：2012-12-11
申请号：US12790734
申请日：2010-05-28
申请人： Amit Paul , Mohamed N. Darwish
发明人： Amit Paul , Mohamed N. Darwish
IPC分类号： H01L29/66
CPC分类号： H01L21/265 , H01L21/26586 , H01L29/0634 , H01L29/0873 , H01L29/0882 , H01L29/0886 , H01L29/1045 , H01L29/1095 , H01L29/408 , H01L29/66666 , H01L29/7802 , H01L29/7827 , H01L29/7835
摘要： The present inventors have realized that manufacturability plays into optimization of power semiconductor devices in some surprising new ways. If the process window is too narrow, the maximum breakdown voltage will not be achieved due to doping variations and the like normally seen in device fabrication. Thus, among other teachings, the present application describes some ways to improve the process margin, for a given breakdown voltage specification, by actually reducing the maximum breakdown voltage. In one class of embodiments, this is done by introducing a vertical gradation in the density of fixed electrostatic charge, or in the background doping of the drift region, or both. Several techniques are disclosed for achieving this.
摘要翻译：本发明人已经认识到，可制造性以令人惊讶的新方式发挥功率半导体器件的优化。如果工艺窗口太窄，则由于在器件制造中通常看到的掺杂变化等，将不能实现最大的击穿电压。因此，除其他教导之外，本申请描述了通过实际降低最大击穿电压来改善给定击穿电压规格的工艺裕度的一些方法。在一类实施例中，这是通过引入固定静电电荷的密度或漂移区的背景掺杂或两者的垂直渐变来完成的。为了实现这一点，公开了几种技术。

54. 发明申请

US20120161226A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20120161226A1
公开(公告)日：2012-06-28
申请号：US13156848
申请日：2011-06-09
申请人： Mohamed N. Darwish
发明人： Mohamed N. Darwish
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L21/02164 , H01L21/0217 , H01L21/02321 , H01L21/2003 , H01L21/265 , H01L21/2658 , H01L21/26586 , H01L21/28008 , H01L21/30604 , H01L21/324 , H01L21/76224 , H01L21/823885 , H01L29/0619 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0661 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/408 , H01L29/4236 , H01L29/42368 , H01L29/66537 , H01L29/66666 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L29/7813 , H01L29/7827 , H01L29/7835
摘要： A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type.
摘要翻译：半导体器件包括形成在其上的第一导电类型的半导体层和第二导电类型的半导体层。第二导电类型的半导体层的特征在于第一厚度。半导体器件包括具有预定深度并延伸到第二导电类型的半导体层的一组沟槽，从而限定设置在第二导电类型的半导体层与每个沟槽之间的界面区域。沟槽包括基本上由布置在其中的介电材料组成的远端部分和包括电介质材料的近端部分和设置在沟槽的近端部分中的电介质材料内部的栅极材料。半导体器件还包括耦合到第二导电类型的半导体层的源极区域。

55. 发明授权

US08080848B2 High voltage semiconductor device with lateral series capacitive structure 有权
标题翻译：具有横向串联电容结构的高压半导体器件
公开(公告)号：US08080848B2
公开(公告)日：2011-12-20
申请号：US11801819
申请日：2007-05-10
申请人： Mohamed N. Darwish , Robert Kuo-Chang Yang
发明人： Mohamed N. Darwish , Robert Kuo-Chang Yang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/0634 , H01L29/0692 , H01L29/407 , H01L29/66659
摘要： According to the present invention, semiconductor device breakdown voltage can be increased by embedding field shaping regions within a drift region of the semiconductor device. A controllable current path extends between two device terminals on the top surface of a planar substrate, and the controllable current path includes the drift region. Each field shaping region includes two or more electrically conductive regions that are electrically insulated from each other, and which are capacitively coupled to each other to form a voltage divider dividing a potential between the first and second terminals. One or more of the electrically conductive regions are isolated from any external electrical contact. Such field shaping regions can provide enhanced electric field uniformity in current-carrying parts of the drift region, thereby increasing device breakdown voltage.
摘要翻译：根据本发明，可以通过在半导体器件的漂移区域内嵌入场成形区域来增加半导体器件击穿电压。可控电流路径在平面基板的顶表面上的两个器件端子之间延伸，并且可控电流路径包括漂移区域。每个场整形区域包括彼此电绝缘并且彼此电容耦合以形成分压第一和第二端子之间的电势的分压器的两个或更多个导电区域。一个或多个导电区域与任何外部电触点隔离。这种场成形区域可以在漂移区域的载流部分中提供增强的电场均匀性，从而增加器件击穿电压。

56. 发明申请

US20110039384A1 Power MOSFET With Recessed Field Plate 审中-公开
标题翻译：功率MOSFET与嵌入式现场板
公开(公告)号：US20110039384A1
公开(公告)日：2011-02-17
申请号：US12912811
申请日：2010-10-27
申请人： Mohamed N. Darwish
发明人： Mohamed N. Darwish
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/66734 , H01L29/7808 , H01L29/7809
摘要： A trench MOSFET contains a recessed field plate (RFP) trench adjacent the gate trench. The RFP trench contains an RFP electrode insulated from the die by a dielectric layer along the walls of the RFP trench. The gate trench has a thick bottom oxide layer, and the gate and RFP trenches are preferably formed in the same processing step and are of substantially the same depth. When the MOSFET operates in the third quadrant (with the source/body-to-drain junction forward-biased), the combined effect of the RFP and gate electrodes significantly reduces in the minority carrier diffusion current and reverse-recovery charge. The RFP electrode also functions as a recessed field plates to reduce the electric field in the channel regions when the MOSFET source/body to-drain junction reverse-biased.
摘要翻译：沟槽MOSFET包含与栅极沟槽相邻的凹陷场板（RFP）沟槽。 RFP沟槽包含沿着RFP沟槽的壁通过电介质层与裸片绝缘的RFP电极。栅极沟槽具有厚的底部氧化物层，并且栅极和RFP沟槽优选地在相同的处理步骤中形成并且具有基本上相同的深度。当MOSFET在第三象限（源极/体对漏极结正向偏置）中工作时，RFP和栅电极的组合效应在少数载流子扩散电流和反向恢复电荷中显着降低。当MOSFET源极/体对漏极结反向偏置时，RFP电极还用作凹陷场板，以减小沟道区域中的电场。

57. 发明申请

US20080191307A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080191307A1
公开(公告)日：2008-08-14
申请号：US11971096
申请日：2008-01-08
申请人： Mohamed N. Darwish
发明人： Mohamed N. Darwish
IPC分类号： H01L29/861
CPC分类号： H01L29/7802 , H01L21/02164 , H01L21/0217 , H01L21/02321 , H01L21/2003 , H01L21/265 , H01L21/2658 , H01L21/26586 , H01L21/28008 , H01L21/30604 , H01L21/324 , H01L21/76224 , H01L21/823885 , H01L29/0619 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0661 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/408 , H01L29/4236 , H01L29/42368 , H01L29/66537 , H01L29/66666 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L29/7813 , H01L29/7827 , H01L29/7835
摘要： A semiconductor structure includes a number of semiconductor regions, a pair of dielectric regions and a pair of terminals. The first and second regions of the structure are respectively coupled to the first and second terminals. The third region of the structure is disposed between the first and second regions. The dielectric regions extend into the third region. A concentration of doping impurities present in the third region and a distance between the dielectric regions define an electrical characteristic of the structure. The electrical characteristic of the structure is independent of the width of the dielectric regions width. The first and second regions are of opposite conductivity types. The structure optionally includes a fourth region that extends into the third region, and surrounds a portion of the pair of dielectric regions. The interface region between the dielectric regions and the fourth region includes intentionally introduced charges.
摘要翻译：半导体结构包括多个半导体区域，一对电介质区域和一对端子。该结构的第一和第二区域分别耦合到第一和第二端子。结构的第三区域设置在第一和第二区域之间。电介质区域延伸到第三区域。存在于第三区域中的掺杂杂质的浓度和电介质区域之间的距离限定了该结构的电特性。该结构的电气特性与电介质区域的宽度无关。第一和第二区域具有相反的导电类型。该结构可选地包括延伸到第三区域中并围绕该对电介质区域的一部分的第四区域。电介质区域和第四区域之间的界面区域包括有意引入的电荷。

58. 发明申请

US20080164516A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080164516A1
公开(公告)日：2008-07-10
申请号：US11971123
申请日：2008-01-08
申请人： Mohamed N. Darwish
发明人： Mohamed N. Darwish
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L21/02164 , H01L21/0217 , H01L21/02321 , H01L21/2003 , H01L21/265 , H01L21/2658 , H01L21/26586 , H01L21/28008 , H01L21/30604 , H01L21/324 , H01L21/76224 , H01L21/823885 , H01L29/0619 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0661 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/408 , H01L29/4236 , H01L29/42368 , H01L29/66537 , H01L29/66666 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L29/7813 , H01L29/7827 , H01L29/7835
摘要： A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor device also includes a body layer extending a first predetermined distance into the semiconductor layer of the second conductivity type and a pair of trenches extending a second predetermined distance into the semiconductor layer of the second conductivity type. Each of the pair of trenches consists essentially of a dielectric material disposed therein and a concentration of doping impurities present in the semiconductor layer of the second conductivity type and a distance between the pair of trenches define an electrical characteristic of the semiconductor device. The semiconductor device further includes a control gate coupled to the semiconductor layer of the second conductivity type and a source region coupled to the semiconductor layer of the second conductivity type.
摘要翻译：半导体器件包括形成在其上的第一导电类型的半导体层和第二导电类型的半导体层。半导体器件还包括延伸第二预定距离的第二预定距离的第二预定距离的第二导电类型的半导体层的主体层和延伸到第二导电类型的半导体层的一对沟槽。一对沟槽中的每一个基本上由设置在其中的介电材料组成，并且存在于第二导电类型的半导体层中的掺杂杂质的浓度和该对沟槽之间的距离限定了半导体器件的电特性。半导体器件还包括耦合到第二导电类型的半导体层的控制栅极和耦合到第二导电类型的半导体层的源极区域。

59. 发明授权

US07326995B2 Trench MIS device having implanted drain-drift region and thick bottom oxide 有权
标题翻译：沟槽MIS器件具有植入漏极漂移区域和厚底部氧化物
公开(公告)号：US07326995B2
公开(公告)日：2008-02-05
申请号：US11158382
申请日：2005-06-22
申请人： Mohamed N. Darwish , King Owyang
发明人： Mohamed N. Darwish , King Owyang
IPC分类号： H01L29/72
CPC分类号： H01L29/7813 , H01L21/2253 , H01L21/28185 , H01L21/28194 , H01L21/28211 , H01L21/823487 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/42368
摘要： A trench MIS device is formed in a P-epitaxial layer that overlies an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the substrate. The thick insulating layer reduces the capacitance between the gate and the drain and therefore improves the ability of the device to operate at high frequencies. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The thick bottom oxide layer is formed on the bottom of the trench while the sidewall spacers are still in place. Therefore, in embodiments where the thermal budget of the process is limited following the implant of the drain-drift region, the PN junctions between the drain-drift region and the epitaxial layer are self-aligned with the edges of the thick bottom oxide. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The relatively flat dopant profile in the channel region provides an increased punchthrough voltage and low threshold voltage.
摘要翻译：沟槽MIS器件形成在覆盖在N +衬底上的P外延层中。在一个实施例中，器件包括在沟槽底部的厚氧化物层和从沟槽的底部延伸到衬底的N型漏 - 漂移区。厚的绝缘层减小了栅极和漏极之间的电容，从而提高了器件在高频下工作的能力。优选地，漏极漂移区域至少部分地通过在沟槽的侧壁上制造间隔物并且在侧壁间隔物之间并通过沟槽的底部注入N型掺杂剂而形成。厚的底部氧化物层形成在沟槽的底部，同时侧壁间隔物仍然在位。因此，在漏极 - 漂移区的注入之后，工艺的热预算受到限制的实施例中，漏 - 漂移区和外延层之间的PN结与厚的底部氧化物的边缘自对准。漏极漂移区可以比在N外延层中形成的常规“漂移区”更重的掺杂。因此，器件具有低导通电阻。通道区域中相对平坦的掺杂物分布提供了增加的穿通电压和低阈值电压。

60. 发明授权

US07009247B2 Trench MIS device with thick oxide layer in bottom of gate contact trench 有权
公开(公告)号：US07009247B2
公开(公告)日：2006-03-07
申请号：US10722984
申请日：2003-11-25
申请人： Mohamed N. Darwish
发明人： Mohamed N. Darwish
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L21/2253 , H01L21/28185 , H01L21/28194 , H01L21/28211 , H01L21/28238 , H01L21/823487 , H01L29/0634 , H01L29/0847 , H01L29/1095 , H01L29/42368 , H01L29/4983 , H01L29/512 , H01L29/518 , H01L29/66621 , H01L29/7834
摘要： A trench MIS device includes a thick dielectric layer at the bottom of the trench. The thick dielectric layer can be formed by the deposition or thermal growth of a dielectric material, such as silicon dioxide, on the bottom portion of the trench. The thick dielectric layer, which reduces the capacitance between the drain and gate of the device, can be formed in both the active areas of the device, where the switching function is performed, and in the inactive areas where, among other things, contacts are made to the gate electrode.

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