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51. 发明申请

US20070133295A1 Reducing read disturb for non-volatile storage 有权
标题翻译：减少非易失性存储的读取干扰
公开(公告)号：US20070133295A1
公开(公告)日：2007-06-14
申请号：US11295776
申请日：2005-12-06
申请人： Yupin Fong , Jun Wan , Jeffrey Lutze
发明人： Yupin Fong , Jun Wan , Jeffrey Lutze
IPC分类号： G11C16/06
CPC分类号： G11C16/3418 , G11C16/3427
摘要： A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.
摘要翻译：公开了一种用于减少或去除非易失性存储设备中的读取干扰形式的系统。一个实施例旨在通过消除或最小化存储器元件的通道的升高来防止读取干扰。例如，一个实施方式在读取过程期间防止或减少NAND串通道的源极侧的升压。因为NAND串通道的源极侧不被提升，所以读取干扰的至少一种形式被最小化或不发生。

52. 发明授权

US07218552B1 Last-first mode and method for programming of non-volatile memory with reduced program disturb 有权
标题翻译：用于编程非易失性存储器的最后模式和方法，减少了程序干扰
公开(公告)号：US07218552B1
公开(公告)日：2007-05-15
申请号：US11223623
申请日：2005-09-09
申请人： Jun Wan , Jeffrey W. Lutze
发明人： Jun Wan , Jeffrey W. Lutze
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/349 , G11C2211/5648
摘要： A non-volatile memory is programmed in a manner which reduces the incidence of program disturb for inhibited memory elements which undergo boosting to reduce program disturb, but which experience reduced boosting benefits due to their word line location. To achieve this result, a word line sequence in which the memory elements are programmed is adjusted so that higher word lines are programmed first, out of sequence relative to the remaining word lines. Additionally, self-boosting can be used for the higher word lines, while erased area self-boosting or a variant can be used for the remaining word lines. Furthermore, pre-charging of the channel of the inhibited memory elements may be employed prior to the self boosting, for the non-volatile storage elements which are programmed after those associated with the first word line.
摘要翻译：非易失性存储器被编程为减少对经过增强的抑制存储器元件的编程干扰的发生率以减少编程干扰的方式，但是哪些经验减少了由于其字线位置而引起的益处。为了实现该结果，调整存储器元件被编程的字线序列，使得较高的字线首先被编程，而不是相对于剩余字线的顺序。另外，自增强可以用于较高的字线，而擦除区域自增强或变体可用于剩余的字线。此外，对于在与第一字线相关联的那些之后编程的非易失性存储元件，可以在自增强之前采用禁止的存储器元件的通道的预充电。

53. 发明申请

US20070025156A1 System for programming non-volatile memory with self-adjusting maximum program loop 有权
标题翻译：用于自适应最大程序循环编程非易失性存储器的系统
公开(公告)号：US20070025156A1
公开(公告)日：2007-02-01
申请号：US11394441
申请日：2006-03-31
申请人： Jun Wan , Jeffrey Lutze
发明人： Jun Wan , Jeffrey Lutze
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10
摘要： The maximum allowable number of voltage programming pulses to program memory elements of a non-volatile memory device is adjusted to account for changes in the memory elements which occur over time. Programming pulses are applied until the threshold voltage of one or more memory elements reaches a certain verify level, after which a defined maximum number of additional pulses may be applied to other memory elements to allow them to also Teach associated target threshold voltage levels. The technique enforces a maximum allowable number of programming pulses that can change over time as the memory is cycled.
摘要翻译：调整非易失性存储器件对程序存储器元件的电压编程脉冲的最大允许数量，以便考虑随时间发生的存储元件的变化。施加编程脉冲，直到一个或多个存储器元件的阈值电压达到某个验证电平，在此之后，定义的最大数量的附加脉冲可以被施加到其它存储器元件，以允许它们也教导相关联的目标阈值电压电平。该技术实现了随着存储器循环而随时间变化的最大允许编程脉冲数。

54. 发明授权

US07161836B1 Method for programming non-volatile memory with self-adjusting maximum program loop 有权
标题翻译：用自调节最大程序循环编程非易失性存储器的方法
公开(公告)号：US07161836B1
公开(公告)日：2007-01-09
申请号：US11194439
申请日：2005-08-01
申请人： Jun Wan , Jeffrey W. Lutze
发明人： Jun Wan , Jeffrey W. Lutze
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： The maximum allowable number of voltage programming pulses to program memory elements of a non-volatile memory device is adjusted to account for changes in the memory elements which occur over time. Programming pulses are applied until the threshold voltage of one or more memory elements reaches a certain verify level, after which a defined maximum number of additional pulses may be applied to other memory elements to allow them to also reach associated target threshold voltage levels. The technique enforces a maximum allowable number of programming pulses that can change over time as the memory is cycled.
摘要翻译：调整非易失性存储器件对程序存储器元件的电压编程脉冲的最大允许数量，以便考虑随时间发生的存储元件的变化。施加编程脉冲，直到一个或多个存储器元件的阈值电压达到某个验证电平，之后可以将限定的最大数量的附加脉冲施加到其它存储器元件以允许它们也达到相关联的目标阈值电压电平。该技术实现了随着存储器循环而随时间变化的最大允许编程脉冲数。

55. 发明申请

US20050107994A1 System, method, and computer program product for determining wall thickness in graphic model 失效
标题翻译：用于确定图形模型中壁厚的系统，方法和计算机程序产品
公开(公告)号：US20050107994A1
公开(公告)日：2005-05-19
申请号：US10717273
申请日：2003-11-19
申请人： Jun Wan , Chee-Keong Chong , Zhi Li
发明人： Jun Wan , Chee-Keong Chong , Zhi Li
IPC分类号： G06F17/50 , G06T17/20 , G06F17/10
CPC分类号： G06T17/20 , G06F17/5018
摘要： A system, method, and computer program product for measuring wall thickness. After an internal body topology of the model is generated, the topology is traversed between wall elements to determine wall thickness.
摘要翻译：一种用于测量壁厚的系统，方法和计算机程序产品。在生成模型的内部结构拓扑之后，在壁元素之间遍历拓扑以确定壁厚。

56. 发明授权

US08843693B2 Non-volatile memory and method with improved data scrambling 有权
标题翻译：非易失性存储器和具有改进的数据加扰的方法
公开(公告)号：US08843693B2
公开(公告)日：2014-09-23
申请号：US13109972
申请日：2011-05-17
申请人： Jonathan Hsu , Chris Nga Yee Avila , Alexander Kwok-Tung Mak , Sergey Anatolievich Gorobets , Tien-chien Kuo , Yee Lih Koh , Jun Wan
发明人： Jonathan Hsu , Chris Nga Yee Avila , Alexander Kwok-Tung Mak , Sergey Anatolievich Gorobets , Tien-chien Kuo , Yee Lih Koh , Jun Wan
IPC分类号： G06F12/00 , G11C7/10 , G11C16/34 , G06F12/14
CPC分类号： G11C16/3427 , G06F12/1408 , G11C7/1006 , G11C7/1012
摘要： A memory device cooperating with a memory controller scrambles each unit of data using a selected scrambling key before storing it in an array of nonvolatile memory cells. This helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. For a given page of data having a logical address and for storing at a physical address, the key is selected from a finite sequence thereof as a function of both the logical address and the physical address. In a block management scheme the memory array is organized into erase blocks, the physical address is the relative page number in each block. When logical address are grouped into logical groups and manipulated as a group and each group is storable into a sub-block, the physical address is the relative page number in the sub-block.
摘要翻译：与存储器控制器协作的存储器件在将其存储在非易失性存储器单元阵列之前，使用所选择的加密密钥对每个数据单元进行加扰。这有助于减少由特定数据模式的重复和长期存储引起的编程干扰，用户读取干扰和浮动栅极到浮动栅极耦合。对于具有逻辑地址并用于存储在物理地址的给定页面的数据，从作为逻辑地址和物理地址的函数的有限序列中选择密钥。在块管理方案中，存储器阵列被组织成擦除块，物理地址是每个块中的相对页号。当逻辑地址分组为逻辑组并作为组操作并且每个组可存储到子块中时，物理地址是子块中的相对页号。

57. 发明授权

US08752751B2 Lead frame support plate and window clamp for wire bonding machines 有权
标题翻译：引线框架支撑板和夹具用于引线接合机
公开(公告)号：US08752751B2
公开(公告)日：2014-06-17
申请号：US13548323
申请日：2012-07-13
申请人： Phui Phoong Chuang , Hasrul Bin Hasim , Wan Azmi , Siti Nurulhaida Bt. Ramlan , Ka Shing Kwan , Ting Yu He , Jun Wan
发明人： Phui Phoong Chuang , Hasrul Bin Hasim , Wan Azmi , Siti Nurulhaida Bt. Ramlan , Ka Shing Kwan , Ting Yu He , Jun Wan
IPC分类号： B23K37/04
CPC分类号： H01L24/78 , B23K20/004 , B23K37/04 , H01L24/85 , H01L2224/78701 , H01L2224/78704 , H01L2224/78981 , H01L2224/85 , H01L2924/00014 , Y10T29/49826 , H01L2224/45099
摘要： A lead frame support plate 200 and a window clamp 400 for wire bonding machines are disclosed herein. In a described embodiment, the lead frame support plate 200 includes a network of suction grooves 218 provided on a support surface 212, each suction groove 218 being arranged to be in fluid communication with at least a vacuum hole 216 to enable a suction force to be created, in response to a vacuum force, along the network of suction grooves for holding a lead frame against the support surface. A window clamp 400 having slots for compensating deformation of the window clamp and a method of fabricating the lead frame support plate are also disclosed.
摘要翻译：本文公开了引线框支撑板200和用于引线接合机的窗夹400。在所描述的实施例中，引线框架支撑板200包括设置在支撑表面212上的抽吸槽218的网络，每个抽吸槽218布置成与至少一个真空孔216流体连通，以使抽吸力成为产生响应于真空力的沿着用于将引线框架保持抵靠支撑表面的抽吸槽的网络。还公开了一种具有用于补偿窗夹的变形的狭槽的窗夹具400和制造引线框架支撑板的方法。

58. 发明申请

US20120297111A1 Non-Volatile Memory And Method With Improved Data Scrambling 有权
标题翻译：非易失性存储器和改进的数据加扰方法
公开(公告)号：US20120297111A1
公开(公告)日：2012-11-22
申请号：US13109972
申请日：2011-05-17
申请人： Jonathan Hsu , Chris Nga Yee Avila , Alexander Kwok-Tung Mak , Sergey Anatolievich Gorobets , Tien-Chien Kuo , Yee Lih Koh , Jun Wan
发明人： Jonathan Hsu , Chris Nga Yee Avila , Alexander Kwok-Tung Mak , Sergey Anatolievich Gorobets , Tien-Chien Kuo , Yee Lih Koh , Jun Wan
IPC分类号： G06F12/02
CPC分类号： G11C16/3427 , G06F12/1408 , G11C7/1006 , G11C7/1012
摘要： A memory device cooperating with a memory controller scrambles each unit of data using a selected scrambling key before storing it in an array of nonvolatile memory cells. This helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. For a given page of data having a logical address and for storing at a physical address, the key is selected from a finite sequence thereof as a function of both the logical address and the physical address. In a block management scheme the memory array is organized into erase blocks, the physical address is the relative page number in each block. When logical address are grouped into logical groups and manipulated as a group and each group is storable into a sub-block, the physical address is the relative page number in the sub-block.
摘要翻译：与存储器控制器协作的存储器件在将其存储在非易失性存储器单元阵列之前，使用所选择的加密密钥对每个数据单元进行加扰。这有助于减少由特定数据模式的重复和长期存储引起的程序干扰，用户读取干扰和浮动栅极到浮动栅极耦合。对于具有逻辑地址并用于存储在物理地址的给定页面的数据，从作为逻辑地址和物理地址的函数的有限序列中选择密钥。在块管理方案中，存储器阵列被组织成擦除块，物理地址是每个块中的相对页号。当逻辑地址分组为逻辑组并作为组操作并且每个组可存储到子块中时，物理地址是子块中的相对页号。

59. 发明申请

US20110189681A1 STAT3 AND TYK2 AS DRUG TARGETS FOR NEURODEGENERATIVE DISEASES 有权
标题翻译： STAT3和TYK2作为治疗神经病变的药物目标
公开(公告)号：US20110189681A1
公开(公告)日：2011-08-04
申请号：US13000303
申请日：2008-06-30
申请人： Nancy Yuk-Yu Ip , Zhenguo Wu , Jerry Hsueh-Ching Wang , Kit Yu Fu , Jun Wan
发明人： Nancy Yuk-Yu Ip , Zhenguo Wu , Jerry Hsueh-Ching Wang , Kit Yu Fu , Jun Wan
IPC分类号： C12Q1/68 , C12Q1/02 , C12Q1/48 , G01N33/50
CPC分类号： G01N33/6896 , G01N33/6872 , G01N2333/9121 , G01N2500/04 , G01N2500/10 , G01N2500/20 , Y10T436/143333
摘要： The invention provides Stat3 and Tyk2 targets that have importance for diagnosis of neurode-generative diseases such as Alzheimer's disease. Stat3 and Tyk2 are also important as targets for drug development for neurodegenerative diseases.
摘要翻译：本发明提供了对诊断神经发生疾病如阿尔茨海默病具有重要意义的Stat3和Tyk2靶标。 Stat3和Tyk2也作为神经退行性疾病药物开发的目标是重要的。

60. 发明授权

US07630249B2 Intelligent control of program pulse duration 有权
标题翻译：智能控制程序脉冲持续时间
公开(公告)号：US07630249B2
公开(公告)日：2009-12-08
申请号：US11766583
申请日：2007-06-21
申请人： Yupin Fong , Jun Wan
发明人： Yupin Fong , Jun Wan
IPC分类号： G11C11/03
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have a constant pulse width and increasing magnitudes until a maximum voltage is reached. At that point, the magnitude of the programming pulses stops increasing and the programming pulses are applied in a manner to provide varying time duration of the programming signal between verification operations. For example, after the pulses reach the maximum magnitude the pulse widths are increased. Alternatively, after the pulses reach the maximum magnitude multiple program pulses are applied between verification operations.
摘要翻译：为了对一组非易失性存储元件进行编程，将一组编程脉冲施加到非易失性存储元件的控制门（或其它终端）。编程脉冲具有恒定的脉冲宽度和增加的幅度，直到达到最大电压。在这一点上，编程脉冲的幅度停止增加，编程脉冲以一种方式施加，以便在验证操作之间提供编程信号的变化的持续时间。例如，在脉冲达到最大幅度之后，脉冲宽度增加。或者，在脉冲达到最大幅度之后，在验证操作之间施加多个编程脉冲。

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