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51. 发明授权

US07037856B1 Method of fabricating a low-defect strained epitaxial germanium film on silicon 有权
标题翻译：在硅上制造低缺陷应变外延锗膜的方法
公开(公告)号：US07037856B1
公开(公告)日：2006-05-02
申请号：US11149883
申请日：2005-06-10
申请人： Jer-Shen Maa , Douglas J. Tweet , Jong-Jan Lee , Sheng Teng Hsu
发明人： Jer-Shen Maa , Douglas J. Tweet , Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： H01L21/31
CPC分类号： H01L21/0262 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/02532 , H01L21/02664 , H01L21/823807
摘要： A method of fabricating a germanium film on a silicon substrate includes preparing a silicon substrate; depositing a first germanium film to form a continuous germanium film on the silicon substrate; annealing the silicon substrate and the germanium film thereon in a first annealing process to relax the germanium film; depositing a second germanium film on the first germanium film to form a germanium layer; patterning and etching the germanium layer; depositing a layer of dielectric material on the germanium layer; cyclic annealing the silicon substrate having the germanium layer and dielectric material thereon; and completing a device containing the silicon substrate and germanium layer.
摘要翻译：在硅衬底上制造锗膜的方法包括制备硅衬底; 沉积第一锗膜以在硅衬底上形成连续的锗膜; 在第一退火工艺中将硅衬底和锗膜退火以使锗膜松弛; 在第一锗膜上沉积第二锗膜以形成锗层; 图案化和蚀刻锗层; 在锗层上沉积介电材料层; 对其上具有锗层和介电材料的硅衬底进行循环退火; 并完成包含硅衬底和锗层的器件。

52. 发明授权

US07015147B2 Fabrication of silicon-on-nothing (SON) MOSFET fabrication using selective etching of Si1-xGex layer 失效
标题翻译：使用Si1-xGex层的选择性蚀刻制造无硅（SON）MOSFET制造
公开(公告)号：US07015147B2
公开(公告)日：2006-03-21
申请号：US10625065
申请日：2003-07-22
申请人： Jong-Jan Lee , Sheng Teng Hsu
发明人： Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： H01L21/302
CPC分类号： H01L29/66772 , H01L21/7624 , H01L21/84 , H01L27/1203 , H01L29/78639 , H01L29/78654
摘要： A method for fabrication of silicon-on-nothing (SON) MOSFET using selective etching of Si1−xGex layer, includes preparing a silicon substrate; growing an epitaxial Si1−xGex layer on the silicon substrate; growing an epitaxial thin top silicon layer on the epitaxial Si1−xGex layer; trench etching of the top silicon and Si1−xGex, into the silicon substrate to form a first trench; selectively etching the Si1−xGex layer to remove substantially all of the Si1−xGex to form an air gap; depositing a layer of SiO2 by CVD to fill the first trench; trench etching to from a second trench; selectively etching the remaining Si1−xGex layer; depositing a second layer of SiO2 by CVD to fill the second trench, thereby decoupling a source, a drain and a channel from the substrate; and completing the structure by state-of-the-art CMOS fabrication techniques.
摘要翻译：使用Si 1-x Ge层的选择性蚀刻制造无硅无硅（SON）MOSFET的方法包括制备硅衬底; 在硅衬底上生长外延Si 1-x Ge层x层; 在外延Si 1-x Ge层上生长外延薄顶硅层; 将硅和Si 1-x N x X x x沟槽蚀刻到硅衬底中以形成第一沟槽; 选择性地蚀刻Si 1-x Ge Ge层，以便基本上除去所有的Si 1-x N x Ge x Si 形成气隙; 通过CVD沉积SiO 2层以填充第一沟槽; 从第二沟槽进行沟槽蚀刻; 选择性地蚀刻剩余的Si 1-x N Ge x层; 通过CVD沉积SiO 2的第二层以填充第二沟槽，从而使源极，漏极和沟道与衬底去耦合; 并通过最先进的CMOS制造技术完成结构。

53. 发明授权

US06897074B1 Method for making single-phase c-axis doped PGO ferroelectric thin films 失效
标题翻译：制备单相c轴掺杂PGO铁电薄膜的方法
公开(公告)号：US06897074B1
公开(公告)日：2005-05-24
申请号：US10794736
申请日：2004-03-03
申请人： Fengyan Zhang , Wei-Wei Zhuang , Jong-Jan Lee , Sheng Teng Hsu
发明人： Fengyan Zhang , Wei-Wei Zhuang , Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： H01L21/00 , H01L21/02 , H01L21/316 , H01L41/22
CPC分类号： H01L21/31691 , H01L28/55 , H01L41/317
摘要： A method for forming a doped PGO ferroelectric thin film, and related doped PGO thin film structures are described. The method comprising: forming either an electrically conductive or electrically insulating substrate; forming a doped PGO film overlying the substrate; annealing; crystallizing; and, forming a single-phase c-axis doped PGO thin film overlying the substrate, having a Curie temperature of greater than 200 degrees C. Forming a doped PGO film overlying the substrate includes depositing a doped precursor in the range between 0.1N and 0.5N, with a molecular formula of Pby-xMxGe3O11, where: M is a doping element; y=4.5 to 6; and, x=0.1 to 1. The element M can be Sn, Ba, Sr, Cd, Ca, Pr, Ho, La, Sb, Zr, or Sm.
摘要翻译：描述了用于形成掺杂的PGO铁电薄膜的方法以及相关的掺杂PGO薄膜结构。该方法包括：形成导电或电绝缘的衬底; 在衬底上形成掺杂的PGO膜; 退火; 结晶并且形成覆盖在衬底上的单相c轴掺杂的PGO薄膜，其居里温度大于200℃。形成覆盖在衬底上的掺杂PGO膜包括沉积在0.1N和0.5之间的掺杂前体 N，具有分子式为Pb x Si x N x N x O 11，其中：M是掺杂物元件; y = 4.5〜6; x = 0.1〜1。元素M可以是Sn，Ba，Sr，Cd，Ca，Pr，Ho，La，Sb，Zr或Sm。

54. 发明申请

US20050101077A1 Sacrificial shallow trench isolation oxide liner for strained-silicon channel CMOS devices 有权
标题翻译：用于应变硅沟道CMOS器件的牺牲浅沟槽隔离氧化层
公开(公告)号：US20050101077A1
公开(公告)日：2005-05-12
申请号：US10985462
申请日：2004-11-09
申请人： Jong-Jan Lee , Sheng Hsu
发明人： Jong-Jan Lee , Sheng Hsu
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8238 , H01L27/08 , H01L27/092 , H01L29/78 , H01L29/786 , H01L21/336
CPC分类号： H01L21/823878 , H01L21/76224 , H01L21/823807
摘要： A strained-silicon (Si) channel CMOS device shallow trench isolation (STI) oxide region, and method for forming same have been provided. The method comprises: forming a Si substrate; forming a relaxed-SiGe layer overlying the Si substrate, or a SiGe on insulator (SGOI) substrate with a buried oxide (BOX) layer; forming a strained-Si layer overlying the relaxed-SiGe layer; forming a silicon oxide layer overlying the strained-Si layer; forming a silicon nitride layer overlying the silicon oxide layer; etching the silicon nitride layer, the silicon oxide layer, the strained-Si layer, and the relaxed-SiGe layer, forming a STI trench with trench corners and a trench surface; forming a sacrificial oxide liner on the STI trench surface; in response to forming the sacrificial oxide liner, rounding and reducing stress at the STI trench corners; removing the sacrificial oxide liner; and, filling the STI trench with silicon oxide.
摘要翻译：已经提供了应变硅（Si）沟道CMOS器件浅沟槽隔离（STI）氧化物区域及其形成方法。该方法包括：形成Si衬底; 形成覆盖在Si衬底上的弛豫SiGe层或者具有掩埋氧化物（BOX）层的绝缘体上硅锗（SGOI）衬底; 形成覆盖弛豫SiGe层的应变Si层; 形成覆盖在应变Si层上的氧化硅层; 形成覆盖所述氧化硅层的氮化硅层; 蚀刻氮化硅层，氧化硅层，应变Si层和弛豫SiGe层，形成具有沟槽角和沟槽表面的STI沟槽; 在STI沟槽表面上形成牺牲氧化物衬垫; 响应于形成牺牲氧化物衬垫，在STI沟槽角处减少应力; 去除牺牲氧化物衬垫; 并用氧化硅填充STI沟槽。

55. 发明授权

US06852652B1 Method of making relaxed silicon-germanium on glass via layer transfer 失效
标题翻译：通过层转移在玻璃上制备松弛的硅 - 锗的方法
公开(公告)号：US06852652B1
公开(公告)日：2005-02-08
申请号：US10674369
申请日：2003-09-29
申请人： Jer-Shen Maa , Jong-Jan Lee , Douglas J. Tweet , Steve Roy Droes
发明人： Jer-Shen Maa , Jong-Jan Lee , Douglas J. Tweet , Steve Roy Droes
IPC分类号： C23C14/48 , H01L21/00 , H01L21/02 , H01L21/20 , H01L21/336 , H01L21/762 , H01L27/12 , H01L29/786
CPC分类号： H01L21/76254 , Y10S438/933
摘要： A method of forming a silicon-germanium layer on an insulator includes preparing a silicon substrate; depositing a layer of silicon-germanium on the silicon substrate to form a silicon/silicon-germanium portion; implanting hydrogen ions in the silicon-germanium layer; preparing an insulator substrate; bonding the silicon/silicon-germanium portion to the insulator substrate with the silicon-germanium layer in contact with the insulator substrate to form a bonded entity; curing the bonded entity; and thermally annealing the bonded entity to split the bonded entity into a silicon/silicon germanium portion and a silicon-germanium-on-insulator portion and to relax the silicon germanium layers.
摘要翻译：在绝缘体上形成硅 - 锗层的方法包括制备硅衬底; 在硅衬底上沉积一层硅 - 锗以形成硅/硅 - 锗部分; 在硅 - 锗层中注入氢离子; 制备绝缘体基板; 将硅/锗锗部分接合到绝缘体衬底，硅 - 锗层与绝缘体衬底接触以形成键合实体; 养护保税实体; 以及对所述结合的实体进行热退火以将所述结合的实体分裂成硅/硅锗部分和绝缘体上的硅 - 锗部分并使所述硅锗层松弛。

56. 发明授权

US06825086B2 Strained-silicon channel CMOS with sacrificial shallow trench isolation oxide liner 失效
标题翻译：应变硅沟道CMOS与牺牲浅沟槽隔离氧化物衬垫
公开(公告)号：US06825086B2
公开(公告)日：2004-11-30
申请号：US10345728
申请日：2003-01-17
申请人： Jong-Jan Lee , Sheng Teng Hsu
发明人： Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： H01L21336
CPC分类号： H01L21/823878 , H01L21/76224 , H01L21/823807
摘要： A strained-silicon (Si) channel CMOS device shallow trench isolation (STI) oxide region, and method for forming same have been provided. The method comprises: forming a Si substrate; forming a relaxed-SiGe layer overlying the Si substrate, or a SiGe on insulator (SGOI) substrate with a buried oxide (BOX) layer; forming a strained-Si layer overlying the relaxed-SiGe layer; forming a silicon oxide layer overlying the strained-Si layer; forming a silicon nitride layer overlying the silicon oxide layer; etching the silicon nitride layer, the silicon oxide layer, the strained-Si layer, and the relaxed-SiGe layer, forming a STI trench with trench corners and a trench surface; forming a sacrificial oxide liner on the STI trench surface; in response to forming the sacrificial oxide liner, rounding and reducing stress at the STI trench corners; removing the sacrificial oxide liner; and, filling the STI trench with silicon oxide.
摘要翻译：已经提供了应变硅（Si）沟道CMOS器件浅沟槽隔离（STI）氧化物区域及其形成方法。该方法包括：形成Si衬底; 形成覆盖在Si衬底上的弛豫SiGe层或者具有掩埋氧化物（BOX）层的绝缘体上硅锗（SGOI）衬底; 形成覆盖弛豫SiGe层的应变Si层; 形成覆盖在应变Si层上的氧化硅层; 形成覆盖所述氧化硅层的氮化硅层; 蚀刻氮化硅层，氧化硅层，应变Si层和弛豫SiGe层，形成具有沟槽角和沟槽表面的STI沟槽; 在STI沟槽表面上形成牺牲氧化物衬垫; 响应于形成牺牲氧化物衬垫，在STI沟槽角处减少应力; 去除牺牲氧化物衬垫; 并用氧化硅填充STI沟槽。

57. 发明授权

US06699764B1 Method for amorphization re-crystallization of Si1-xGex films on silicon substrates 失效
标题翻译：硅衬底上Si1-xGex薄膜的非晶化再结晶方法
公开(公告)号：US06699764B1
公开(公告)日：2004-03-02
申请号：US10238146
申请日：2002-09-09
申请人： Douglas J. Tweet , Jer-shen Maa , Jong-Jan Lee , Sheng Teng Hsu
发明人： Douglas J. Tweet , Jer-shen Maa , Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： H01L21336
CPC分类号： H01L21/263 , C30B1/023 , C30B1/04 , C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/0251 , H01L21/02532 , H01L21/02694 , H01L29/1054 , H01L29/165 , Y10S438/933
摘要： A method of fabricating a Si1−XGeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1−XGeX layer on the silicon substrate forming a Si1−XGeX/Si interface there between; epitaxially growing a silicon cap on the Si1−XGeX layer; implanting hydrogen ions through the Si1−XGeX layer to a depth of between about 3 nm to 100 nm below the Si1−XGeX/Si interface; amorphizing the Si1−XGeX layer to form an amorphous, graded SiGe layer; and annealing the structure at a temperature of between about 650° C. to 1100° C. for between about ten seconds and sixty minutes to recrystallize the SiGe layer.
摘要翻译：在硅衬底上制造Si1-XGeX膜的方法包括制备硅衬底; 在硅衬底上外延沉积形成Si1-XGeX / Si界面的Si1-XGeX层; 在Si1-XGeX层上外延生长硅帽; 通过Si1-XGeX层将氢离子注入Si1-XGeX / Si界面以下约3nm至100nm之间的深度; 将Si1-XGeX层非晶化以形成无定形的梯度SiGe层; 并在约650℃至1100℃的温度下对该结构退火约十秒至六十分钟以使SiGe层重结晶。

58. 发明授权

US09559358B2 Alkali and alkaline-earth ion batteries with hexacyanometallate cathode and non-metal anode 有权
标题翻译：碱金属和碱土金属离子电池与六金属金属阴极和非金属阳极
公开(公告)号：US09559358B2
公开(公告)日：2017-01-31
申请号：US13449195
申请日：2012-04-17
申请人： Yuhao Lu , Jong-Jan Lee , Motoaki Nishijima , Seizoh Kakimoto
发明人： Yuhao Lu , Jong-Jan Lee , Motoaki Nishijima , Seizoh Kakimoto
IPC分类号： H01M4/58 , H01M4/04 , H01M4/136 , H01M4/587 , H01M4/139 , H01M4/02 , H01M10/36 , H01M10/054
CPC分类号： H01M4/58 , H01M4/0404 , H01M4/0438 , H01M4/0445 , H01M4/0459 , H01M4/136 , H01M4/139 , H01M4/587 , H01M10/054 , H01M10/36 , H01M2004/028 , Y02E60/122
摘要： A battery structure is provided for making alkali ion and alkaline-earth ion batteries. The battery has a hexacyanometallate cathode, a non-metal anode, and non-aqueous electrolyte. A method is provided for forming the hexacyanometallate battery cathode and non-metal battery anode prior to the battery assembly. The cathode includes hexacyanometallate particles overlying a current collector. The hexacyanometallate particles have the chemical formula A′n′AmM1xM2y(CN)6, and have a Prussian Blue hexacyanometallate crystal structure.
摘要翻译：提供用于制造碱性离子和碱土离子电池的电池结构。电池具有六金属金属阴极，非金属阳极和非水电解质。提供了一种用于在电池组装之前形成六氰基金属盐电池阴极和非金属电池阳极的方法。阴极包括覆盖集电器的六氰基金属盐颗粒。六氰基金属盐颗粒具有化学式A'n'AmM1xM2y（CN）6，并具有普鲁士蓝六氰基金属酸盐晶体结构。

59. 发明申请

US20130260222A1 Electrode Forming Process for Metal-Ion Battery with Hexacyanometallate Electrode 有权
标题翻译：金属离子电池与六氰基金属电极的电极成型工艺
公开(公告)号：US20130260222A1
公开(公告)日：2013-10-03
申请号：US13432993
申请日：2012-03-28
申请人： Yuhao Lu , Jong-Jan Lee
发明人： Yuhao Lu , Jong-Jan Lee
IPC分类号： H01M4/38 , H01M4/02 , H01M4/40 , H01M4/58 , H01M10/02
CPC分类号： H01M4/58 , H01M4/0404 , H01M4/0438 , H01M4/0445 , H01M4/0459 , H01M4/139 , H01M4/587 , H01M10/054
摘要： A method is provided for forming a metal-ion battery electrode with large interstitial spacing. A working electrode with hexacyanometallate particles overlies a current collector. The hexacyanometallate particles have a chemical formula AmM1xM2y(CN)6·zH2O, and have a Prussian Blue hexacyanometallate crystal structure, where A is either alkali or alkaline-earth cations. M1 and M2 are metals with 2+ or 3+ valance positions. The working electrode is soaked in an organic first electrolyte including a salt including alkali or alkaline earth cations. A first electric field is created in the first electrolyte between the working electrode and a first counter electrode, causing A cations and water molecules to he simultaneously removed from interstitial spaces in the Prussian Blue hexacyanometallate crystal structure, forming hexacyanometallate particles having the chemical formula of Am′mM1xM2y(CN)6·z′H2O, where m′
摘要翻译：提供一种用于形成具有大间隙间距的金属离子电池电极的方法。具有六氰基金属酸盐颗粒的工作电极覆盖集电器。六氰基金属盐颗粒具有化学式AmM1xM2y（CN）6·zH2O，并具有普鲁士蓝六氰基金属酸盐晶体结构，其中A为碱金属或碱土金属阳离子。 M1和M2是具有2+或3+价位的金属。将工作电极浸渍在包含碱金属或碱土金属阳离子的盐的有机第一电解质中。在工作电极和第一对电极之间的第一电解质中产生第一电场，使得阳离子和水分子同时从普鲁士蓝六氰基金属酸盐晶体结构中的间隙中除去，形成化学式为Am的六氰基金属盐颗粒 'mM1xM2y（CN）6·z'H2O，其中m'

60. 发明申请

US20120211063A1 Back Contact Solar Cell with Organic Semiconductor Heterojunctions 审中-公开
标题翻译：背面接触有机半导体异质结的太阳能电池
公开(公告)号：US20120211063A1
公开(公告)日：2012-08-23
申请号：US13215279
申请日：2011-08-23
申请人： Jong-Jan Lee , Paul J. Schuele
发明人： Jong-Jan Lee , Paul J. Schuele
IPC分类号： H01L31/0352 , H01L51/46
CPC分类号： H01L31/022441 , B82Y10/00 , B82Y30/00 , H01L31/0747 , H01L31/075 , H01L31/1804 , H01L51/0036 , H01L51/0037 , H01L51/0047 , H01L51/4213 , H01L51/4293 , Y02E10/547 , Y02E10/548 , Y02E10/549 , Y02P70/521
摘要： A back contact solar cell with organic semiconductor heterojunctions is provided. The substrate is made from silicon lightly doped with a first dopant type having a first majority carrier. A second semiconductor layer is formed overlying the texturized substrate topside, made from hydrogenated amorphous silicon (a-Si:H) and doped with the first dopant. An antireflective coating is formed overlying the second semiconductor layer. A third semiconductor layer is formed overlying the first semiconductor substrate backside, made from intrinsic a-Si:H. First and second majority carrier type organic semiconductor layers are formed overlying the third semiconductor layer in patterns. A dielectric organic semiconductor layer is formed overlying the first majority carrier type organic semiconductor layer and the second majority carrier type organic semiconductor layer, filling the spaces in the pattern. A first metal grid is connected to first organic semiconductor contact regions and a second metal grid is connected to the second organic semiconductor contact regions.
摘要翻译：提供了具有有机半导体异质结的背接触太阳能电池。衬底由具有第一多数载流子的第一掺杂剂类型的轻掺杂硅制成。形成第二半导体层，覆盖由氢化非晶硅（a-Si：H）制成并掺杂有第一掺杂剂的纹理化衬底顶层。形成覆盖第二半导体层的抗反射涂层。第三半导体层形成在由固有a-Si：H制成的第一半导体衬底背面上。第一和第二多数载流子型有机半导体层以图案形成在第三半导体层上。在第一多数载流子型有机半导体层和第二多数载流子型有机半导体层上形成绝缘有机半导体层，填充图案中的空间。第一金属网格连接到第一有机半导体接触区域，第二金属栅极连接到第二有机半导体接触区域。

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