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51. 发明授权

US07738588B2 Arrangement comprising a first semiconductor chip and a second semiconductor chip connected thereto 有权
标题翻译：包括第一半导体芯片和与其连接的第二半导体芯片的布置
公开(公告)号：US07738588B2
公开(公告)日：2010-06-15
申请号：US10727108
申请日：2003-12-02
申请人： Jens Barrenscheen , Peter Rohm , Angela Rohm, legal representative , Axel Aue , Jens Graf , Herman Roozenbeek
发明人： Jens Barrenscheen , Peter Rohm , Axel Aue , Jens Graf , Herman Roozenbeek
IPC分类号： H04L27/00
CPC分类号： H04L1/24 , G05B2219/2202 , G05B2219/2214 , G05B2219/24044 , G05B2219/24065
摘要： An arrangement including a first semiconductor chip and a second semiconductor chip connected thereto, where the second semiconductor chip is additionally connected to electrical loads and drives these electrical loads on the basis of a timing which is prescribed to it by load control data, and where the first semiconductor chip transmits to the second semiconductor chip the aforementioned load control data and pilot data which control the second semiconductor chip, and where the second semiconductor chip transmits to the first semiconductor chip diagnostic data which represent states prevailing in the second semiconductor chip or events which occur. The first semiconductor chip transmits appropriate pilot data in order to prescribe to the second semiconductor chip what transmission rate is to be used by the second semiconductor chip to transmit the diagnostic data to the first semiconductor chip.
摘要翻译：一种包括连接到其上的第一半导体芯片和第二半导体芯片的布置，其中第二半导体芯片另外连接到电负载并且基于由负载控制数据规定的定时驱动这些电负载，并且其中第一半导体芯片向第二半导体芯片发送上述负载控制数据和控制第二半导体芯片的导频数据，第二半导体芯片向第一半导体芯片发送表示第二半导体芯片中的状态的诊断数据，发生。第一半导体芯片发送适当的导频数据，以便向第二半导体芯片规定第二半导体芯片将使用什么传输速率将诊断数据发送到第一半导体芯片。

52. 发明申请

US20090234980A1 System and Method for Statistics Recording of Power Devices 有权
标题翻译：功率器件统计记录系统和方法
公开(公告)号：US20090234980A1
公开(公告)日：2009-09-17
申请号：US12046372
申请日：2008-03-11
申请人： Jens Barrenscheen , Giuseppe Bernacchia , Martin Krueger , Erwin Huber
发明人： Jens Barrenscheen , Giuseppe Bernacchia , Martin Krueger , Erwin Huber
IPC分类号： G06F1/26 , G06F3/00
CPC分类号： G06F1/26
摘要： A system and method for statistics recording of power devices is disclosed. A power circuit includes a power device to provide a specified electrical power to a load and a host controller coupled to the power device. The host controller is configured to provide issue instructions to and retrieve status information from the power device. A communications and control interface (CCI) is coupled between the power device and the host controller. The CCI is configured to operate as a communications interface between the power device and the host controller and to retrieve and store status information from the power device. The CCI may be capable of performing statistical analysis on the status information to help reduce the amount of information exchanged between the host controller and the power device, thereby reducing bandwidth requirements.
摘要翻译：公开了用于功率器件的统计记录的系统和方法。电源电路包括向负载提供特定电力的功率设备和耦合到功率设备的主机控制器。主机控制器被配置为向电力设备提供发送指令并从其获取状态信息。通信和控制接口（CCI）耦合在电源设备和主机控制器之间。 CCI被配置为作为电力设备和主机控制器之间的通信接口运行，并且从电力设备检索和存储状态信息。 CCI可能能够对状态信息进行统计分析，以帮助减少主机控制器与电源设备之间交换的信息量，从而降低带宽需求。

53. 发明申请

US20090167584A1 SYSTEM HAVING A SIGNAL CONVERTER DEVICE AND METHOD OF OPERATING 有权
标题翻译：具有信号转换器装置的系统和操作方法
公开(公告)号：US20090167584A1
公开(公告)日：2009-07-02
申请号：US12349790
申请日：2009-01-07
申请人： Jens Barrenscheen , Patrick Leteinturier
发明人： Jens Barrenscheen , Patrick Leteinturier
IPC分类号： H03M1/66
CPC分类号： G06F3/05
摘要： A system having a signal converter device, and a method for operating a system having a signal converter device is disclosed. One embodiment provides loading a capacitive device to a preparation voltage in a first operating phase, and loading the capacitive device to a measuring voltage in a second operating phase after the first operating phase.
摘要翻译：公开了一种具有信号转换器装置的系统和一种用于操作具有信号转换器装置的系统的方法。一个实施例提供了在第一操作阶段将电容性装置加载到制备电压，并且在第一操作阶段之后的第二操作阶段将电容性装置加载到测量电压。

54. 发明授权

US07133953B2 Data transmission device used to forward data received at a first device for a second device to the second device 有权
标题翻译：用于将在第一设备处接收到的用于第二设备的数据转发到第二设备的数据传输设备
公开(公告)号：US07133953B2
公开(公告)日：2006-11-07
申请号：US10308396
申请日：2002-12-03
申请人： Jens Barrenscheen
发明人： Jens Barrenscheen
IPC分类号： G06F13/14 , G06F3/00 , G06F13/00 , G06F13/42 , G06F13/24
CPC分类号： G06F13/4217
摘要： A data transmission device is used to forward data that have been received from a first device, and are intended for a second device, to the second device. The data transmission device described has a whole series of characteristics that allow the data that are to be transmitted to be transmitted very easily very quickly and which confer additional functions on the data transmission device.
摘要翻译：数据传输装置用于将已经从第一装置接收到的数据转发给第二装置，并将其用于第二装置。所描述的数据传输设备具有允许发送的数据被非常容易地非常容易地传输并且在数据传输设备上赋予附加功能的全部系列特征。

55. 发明授权

US07032049B2 Apparatus for relaying received interrupt requests 有权
公开(公告)号：US07032049B2
公开(公告)日：2006-04-18
申请号：US09962696
申请日：2001-09-24
申请人： Jens Barrenscheen
发明人： Jens Barrenscheen
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： An apparatus is described which is distinguished by the fact that the apparatus does not output an interrupt request until after a plurality of interrupt requests have been received. The apparatus outputs a plurality of interrupt requests in response to an interrupt request being received, and/or the apparatus waits to output an interrupt request until it can be assumed that the operation to be initiated by a previously output interrupt request has been executed. As a result, it can be used extremely flexibly.

56. 发明授权

US06507298B1 Method for selecting, prioritizing, and A/D conversion of analog signals, and A/D converter configuration that prioritizes and selects signals 有权
标题翻译：用于选择，优先排序和模拟信号的A / D转换的方法以及优先选择信号的A / D转换器配置
公开(公告)号：US06507298B1
公开(公告)日：2003-01-14
申请号：US09708280
申请日：2000-11-08
申请人： Jens Barrenscheen , Gunther Fenzl
发明人： Jens Barrenscheen , Gunther Fenzl
IPC分类号： H03M112
CPC分类号： G06F3/05
摘要： A method for A/D conversion of analog signals using an A/D converter, and to an appropriate A/D converter circuit. In order to process converter request signals from different converter request sources requesting analog signals for conversion, the invention proposes assigning definable, selectable priorities to the different converter request sources. If there is a request for A/D conversion from a converter request source, the system establishes which of the converter request sources requesting A/D conversion has the highest priority. An analog signal from this selected converter request source is then supplied to the A/D converter.
摘要翻译：一种使用A / D转换器和适当的A / D转换器电路对模拟信号进行A / D转换的方法。为了处理来自请求模拟信号进行转换的不同转换器请求源的转换器请求信号，本发明提出向不同转换器请求源分配可定义的可选优先级。如果存在来自转换器请求源的A / D转换的请求，则系统确定请求A / D转换的转换器请求源中的哪一个具有最高优先级。然后将来自该选择的转换器请求源的模拟信号提供给A / D转换器。

57. 发明授权

US06421770B1 Buffer memory configuration having a memory between a USB and a CPU 失效
标题翻译：具有在USB和CPU之间的存储器的缓冲存储器配置
公开(公告)号：US06421770B1
公开(公告)日：2002-07-16
申请号：US09120160
申请日：1998-07-21
申请人： Martin Huch , Jens Barrenscheen , Gunther Fenzl
发明人： Martin Huch , Jens Barrenscheen , Gunther Fenzl
IPC分类号： G06F1202
CPC分类号： G06F5/16 , G06F5/10
摘要： The buffer memory configuration has a memory disposed between a USB and a central processing unit. The memory can be mapped onto an address space which is exactly half as large as the memory itself. The first half of the memory defines a first memory page and the second half of the memory defines a second memory page, and each address in the address space is assigned exactly one memory location on each of the memory pages. A memory management unit generates a first significant bit which assigns in each case the two memory locations having the same address to the address space of the first memory page and to the address space of the second memory page. The buffer memory architecture enables the memory independently to manage the data to be transferred. The two memory pages serve to decouple the central processing unit CPU and the bus. Both memory pages are virtually visible to the user but only one of the memory pages can ever be addressed for data transfer. Consequently, overlapping of the writing cycles is avoided by arranging the transmitted data and the data to be read out in separate areas of the memory.
摘要翻译：缓冲存储器配置具有设置在USB和中央处理单元之间的存储器。存储器可以被映射到正好与存储器本身一半一样大的地址空间。存储器的前半部分定义第一存储器页面，并且存储器的第二半部分定义第二存储器页面，并且每个存储器页面上分配地址空间中的每个地址恰好一个存储器位置。存储器管理单元产生第一有效位，其在每种情况下将具有相同地址的两个存储器位置分配给第一存储器页的地址空间和第二存储器页的地址空间。缓冲存储器架构使内存独立地管理要传输的数据。两个存储器页面用于去耦中央处理单元CPU和总线。两个内存页面对用户实际上是可见的，但只有一个内存页面可以被寻址用于数据传输。因此，通过将发送的数据和要在存储器的不同区域中读出的数据进行布置来避免写入周期的重叠。

58. 发明授权

US06297761B1 Measuring apparatus for digitally detecting analog measured variables 有权
标题翻译：用于数字检测模拟测量变量的测量装置
公开(公告)号：US06297761B1
公开(公告)日：2001-10-02
申请号：US09267291
申请日：1999-03-12
申请人： Jens Barrenscheen , Andreas Jansen , Hermann Kern , Heinz Amann
发明人： Jens Barrenscheen , Andreas Jansen , Hermann Kern , Heinz Amann
IPC分类号： H03M150
CPC分类号： H03M1/50
摘要： A measuring apparatus has a sensor element that produces an output signal proportional to a variable to be measured. An integrator which, beginning at a starting value, integrates the output signal from the sensor element. A comparator is connected downstream of the integrator, compares the output signal from the integrator with a threshold value, and outputs an output signal corresponding to the result of the comparison. A reset device that is likewise connected downstream of the comparator and resets the integrator to the starting value at specific times. This is a simple way of achieving integrability in autonomous modules.
摘要翻译：测量装置具有产生与待测量的变量成比例的输出信号的传感器元件。积分器从起始值开始，将来自传感器元件的输出信号进行积分。比较器连接在积分器的下游，将积分器的输出信号与阈值进行比较，并输出与比较结果对应的输出信号。复位装置同样连接在比较器的下游，并将积分器在特定时间复位到起始值。这是在自主模块中实现可集成性的一种简单方法。

59. 发明授权

US6147635A Timer for A/D converter 有权
标题翻译： A / D转换器定时器
公开(公告)号：US6147635A
公开(公告)日：2000-11-14
申请号：US307999
申请日：1999-05-10
申请人： Jens Barrenscheen , Peter Rohm , Gunther Fenzl
发明人： Jens Barrenscheen , Peter Rohm , Gunther Fenzl
IPC分类号： G06F3/05 , H03M1/12
CPC分类号： H03M1/1225
摘要： A timer for an A/D converter generates a request signal for A/D conversion by the A/D converter. In addition to the usual request signal, the timer produces a further signal which is used, before one cycle of the timer has elapsed, to block the A/D converter for low-priority requests from other requesting devices and to reserve it for the timer. In this manner, the signal to be converted from the timer can be sampled at reproducible, equidistant instants without having to wait for the end of the last conversion.
摘要翻译：用于A / D转换器的定时器通过A / D转换器产生用于A / D转换的请求信号。除了通常的请求信号之外，定时器还产生另一个信号，该信号在定时器的一个周期过去之前被使用，以阻止来自其他请求设备的低优先级请求的A / D转换器，并将其保留给定时器。以这种方式，从定时器转换的信号可以在可再现的等距时刻进行采样，而不必等待最后一次转换的结束。

60. 发明授权

US08847568B2 Sample-point adjustment in a switching converter 有权
标题翻译：开关转换器中的采样点调整
公开(公告)号：US08847568B2
公开(公告)日：2014-09-30
申请号：US12240174
申请日：2008-09-29
申请人： Jens Barrenscheen , Giuseppe Bernacchia
发明人： Jens Barrenscheen , Giuseppe Bernacchia
IPC分类号： G05F1/00 , H02M3/156
CPC分类号： H02M3/156
摘要： An apparatus and method of generating a drive signal for a switch in a switching converter having input terminals for applying an input voltage, output terminals for providing an output signal, and at least one inductive storage element coupled to the switch. The method includes sampling the output signal to provide a sampled output signal, and generating a pulsewidth modulated drive signal having a duty cycle that is dependent on the sampled output signal, wherein the output voltage is sampled at sampling times that are dependent on the duty cycle.
摘要翻译：一种用于在具有用于施加输入电压的输入端子的开关转换器中产生用于开关的驱动信号的装置和方法，用于提供输出信号的输出端子以及耦合到该开关的至少一个感应存储元件。该方法包括对输出信号进行采样以提供采样输出信号，并产生具有取决于采样输出信号的占空比的脉宽调制驱动信号，其中输出电压在取决于占空比的采样时间。

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