专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US06985431B1 Network switch and components and method of operation 有权
标题翻译：网络交换机及组件及操作方法
公开(公告)号：US06985431B1
公开(公告)日：2006-01-10
申请号：US09384692
申请日：1999-08-27
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Fabrice Jean Verplanken , Brian Alan Youngman
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Fabrice Jean Verplanken , Brian Alan Youngman
IPC分类号： H04Q11/04
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.
摘要翻译：一种网络交换装置，这种装置的组件，以及操作这样的装置的方法，其中通过控制点和形成在半导体衬底上的多个接口处理器的协作来增强数据流处理和灵活性。控制点和接口处理器一起形成一个网络处理器，能够在执行指导网络中的数据流的指令的情况下与包括可选交换结构设备在内的其他元件协作。

52. 发明授权

US06766381B1 VLSI network processor and methods 失效
标题翻译： VLSI网络处理器和方法
公开(公告)号：US06766381B1
公开(公告)日：2004-07-20
申请号：US09384689
申请日：1999-08-27
申请人： Kenneth James Barker , Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
发明人： Kenneth James Barker , Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
IPC分类号： G06F1516
CPC分类号： H04L29/06 , H04L49/1507 , H04L49/45 , H04L69/12
摘要： A network processor useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of a plurality of interface processors formed on a semiconductor substrate. The interface processors provide data paths for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate.
摘要翻译：可用于网络交换设备的网络处理器和操作这样的处理器的方法，其中通过形成在半导体衬底上的多个接口处理器的协作来增强数据流处理和灵活性。接口处理器提供用于入站和出站数据流的数据路径，并且在存储在形成在半导体衬底上的指令存储器中的指令的控制下操作。

53. 发明授权

US06675163B1 Full match (FM) search algorithm implementation for a network processor 失效
标题翻译：网络处理器的完全匹配（FM）搜索算法实现
公开(公告)号：US06675163B1
公开(公告)日：2004-01-06
申请号：US09543531
申请日：2000-04-06
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F1730
CPC分类号： H04L45/742 , H04L45/7453 , Y10S707/99933 , Y10S707/99934 , Y10S707/99935 , Y10S707/99936 , Y10S707/99937 , Y10S707/99943 , Y10S707/99945
摘要： Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBs) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n→n mapping of the bits of the key to the bits of the hash key. The data structure that is used to store the hash key and the related information in the tree is called a leaf. Each leaf corresponds to a single key that matches exactly with the input key. The leaf contains the key as well as additional information. The length of the leaf is programmable, as is the length of the key. The leaf is stored in random access memory and is implemented as a single memory entry. If the key is located in the direct table then it is called a direct leaf.
摘要翻译：用于在搜索图案和存储在搜索树的叶中的模式之间找到完全匹配的新型数据结构，方法和装置。键输入，对密钥执行哈希函数，访问直接表（DT），并通过模式搜索控制块（PSCB），树直到达到叶。搜索机制使用一组可以位于几个寄存器和常规内存中的数据结构，然后用于构建可由相对简单的硬件宏操作的Patricia树结构。检索所需的两个密钥和相应的信息都存储在Patricia树结构中。散列函数提供密钥的比特到散列密钥的比特的n> n映射。用于存储散列键和树中相关信息的数据结构称为叶。每个叶对应于与输入键完全匹配的单个键。叶包含关键以及其他信息。叶片的长度是可编程的，密钥的长度也是可编程的。叶存储在随机存取存储器中，并被实现为单个存储器条目。如果键位于直接表中，则称为直接叶。

54. 发明授权

US06657962B1 Method and system for managing congestion in a network 失效
标题翻译：管理网络拥塞的方法和系统
公开(公告)号：US06657962B1
公开(公告)日：2003-12-02
申请号：US09546651
申请日：2000-04-10
申请人： Peter Irma August Barri , Brian Mitchell Bass , Jean Louis Calvignac , Ivan Oscar Clemminck , Marco C. Heddes , Clark Debs Jeffries , Michael Steven Siegel , Fabrice Jean Verplanken , Miroslav Vrana
发明人： Peter Irma August Barri , Brian Mitchell Bass , Jean Louis Calvignac , Ivan Oscar Clemminck , Marco C. Heddes , Clark Debs Jeffries , Michael Steven Siegel , Fabrice Jean Verplanken , Miroslav Vrana
IPC分类号： H04L1256
CPC分类号： H04L47/2441 , H04L47/10 , H04L47/12 , H04L47/30 , H04L47/32 , H04L49/103 , H04L49/3018 , H04L49/50 , H04L49/90
摘要： A system for minimizing congestion in a communication system is disclosed. The system comprises at least one ingress system for providing data. The ingress system includes a first free queue and a first flow queue. The system also includes a first congestion adjustment module for receiving congestion indications from the free queue and the flow queue. The first congestion adjustment module generates end stores transmit probabilities and performs per packet flow control actions. The system further includes a switch fabric for receiving data from the ingress system and for providing a congestion indication to the ingress system. The system further includes at least one egress system for receiving the data from the switch fabric. The egress system includes a second free queue and a second flow queue. The system also includes a second congestion adjustment module for receiving congestion indications from the second free queue and the second flow queue. The second congestion adjustment module generates and stores transmit probabilities and performs per packet flow control actions. Finally, the system includes a scheduler for determining the order and timing of transmission of packets out the egress system and to another node or destination. A method and system in accordance with the present invention provides for a unified method and system for logical connection of congestion with the appropriate flow control responses. The method and system utilizes congestion indicators within the ingress system, egress system, and the switch fabric in conjunction with a coarse adjustment system and fine adjustment system within the ingress device and the egress device to intelligently manage the system.
摘要翻译：公开了一种用于最小化通信系统中的拥塞的系统。该系统包括用于提供数据的至少一个入口系统。入口系统包括第一空闲队列和第一流队列。该系统还包括用于从空闲队列和流队列接收拥塞指示的第一拥塞调整模块。第一拥塞调整模块生成终端存储发送概率并执行每个分组流控制动作。该系统还包括用于从入口系统接收数据并向入口系统提供拥塞指示的交换结构。该系统还包括用于从交换结构接收数据的至少一个出口系统。出口系统包括第二空闲队列和第二流队列。该系统还包括第二拥塞调整模块，用于从第二空闲队列和第二流队列接收拥塞指示。第二拥塞调整模块生成并存储发送概率，并执行每个分组流控制动作。最后，该系统包括一个调度器，用于确定出口系统和另一个节点或目的地的分组传输的顺序和定时。根据本发明的方法和系统提供了用于将拥塞与适当流控制响应逻辑连接的统一方法和系统。该方法和系统利用入口系统，出口系统和交换结构中的拥塞指示符与入口设备和出口设备内的粗调系统和精细调整系统结合，智能地管理系统。

55. 发明授权

US06522271B2 Method and apparatus for transmission on a 2-bit channel using 3b/4b code 失效
公开(公告)号：US06522271B2
公开(公告)日：2003-02-18
申请号：US10096161
申请日：2002-03-12
申请人： Jean Louis Calvignac , Jeffrey James Lynch , Daniel James Sucher , Fabrice Jean Verplanken
发明人： Jean Louis Calvignac , Jeffrey James Lynch , Daniel James Sucher , Fabrice Jean Verplanken
IPC分类号： H03M700
CPC分类号： H03M7/20
摘要： A 2-bit communication channel is made to transmit complex data patterns by partitioning a digital string into 3-bit binary patterns which are encoded into 4 bits binary pattern and transmitted over the 2-bit communication channel in pairs using adjacent clock cycles on the 2-bit channel. Pre-defined ones of the 4-bit encoded data structures are used for framing on the channel and cannot be used to transmit data.

56. 发明授权

US07921396B2 Data aligner in reconfigurable computing environment 失效
公开(公告)号：US07921396B2
公开(公告)日：2011-04-05
申请号：US12126951
申请日：2008-05-26
申请人： Fabrice Jean Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Louis Calvignac
发明人： Fabrice Jean Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Louis Calvignac
IPC分类号： G06F17/50
CPC分类号： H04L69/16 , H04L49/45 , H04L69/161
摘要： A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.

57. 发明授权

US07881332B2 Configurable ports for a host ethernet adapter 失效
标题翻译：主机以太网适配器的可配置端口
公开(公告)号：US07881332B2
公开(公告)日：2011-02-01
申请号：US11097652
申请日：2005-04-01
申请人： Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： H04J3/16
CPC分类号： H04L12/40032 , H04L12/413 , H04L49/90 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/18 , H04L69/323 , H04L69/324
摘要： A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.
摘要翻译：根据本发明的系统和方法允许在可以使用相同引脚容纳10G和1G源的服务器环境中使用适配器。这是通过使用可以容纳两个数据源的高速串行器/解串器（高速serdes）来实现的。高速serdes允许在NIC上使用相对较低的参考时钟速度来提供数据源的适当时钟，并且还允许设置不同的模式以适应不同的数据源。最后，该系统允许适配器为多个数据源使用相同的引脚。

58. 发明授权

US07796513B2 Packet classification using modified range labels 失效
标题翻译：数据包分类使用修改的范围标签
公开(公告)号：US07796513B2
公开(公告)日：2010-09-14
申请号：US12187188
申请日：2008-08-06
申请人： Claude Basso , Jean Louis Calvignac , Gordon Taylor Davis , Clark Debs Jeffries
发明人： Claude Basso , Jean Louis Calvignac , Gordon Taylor Davis , Clark Debs Jeffries
IPC分类号： H04L12/26
CPC分类号： H04L45/00 , H04L12/4625 , H04L45/54 , H04L45/7453 , H04L63/0263
摘要： A method and system for encoding a set of range labels for each parameter field in a packet classification key in such a way as to require preferably only a single entry per rule in a final processing stage of a packet classifier. Multiple rules are sorted accorded to their respective significance. A range, based on a parameter in the packet header, is previously determined. Multiple rules are evaluated according to an overlapping of rules according to different ranges. Upon a determination that two or more rules overlap, each overlapping rule is expanded into multiple unique segments that identify unique range intersections. Each cluster of overlapping ranges is then offset so that at least one bit in a range for the rule remains unchanged. The range segments are then converted from binary to Gray code, which results in the ability to determine a CAM entry to use for each range.
摘要翻译：一种方法和系统，用于以分组分类密钥中的每个参数字段的一组范围标签进行编码，以便在分组分类器的最后处理阶段中优选地仅需要每个规则仅一个条目。根据各自的意义对多个规则进行排序。预先确定基于分组报头中的参数的范围。根据不同范围的规则重叠来评估多个规则。在确定两个或更多个规则重叠时，每个重叠规则被扩展为识别唯一范围交点的多个唯一段。然后，每个重叠范围的簇被偏移，使得该规则的范围中的至少一个位保持不变。范围段然后从二进制转换为格雷码，这导致确定每个范围使用的CAM条目的能力。

59. 发明授权

US07623450B2 Methods and apparatus for improving security while transmitting a data packet 失效
标题翻译：用于在传输数据分组时提高安全性的方法和装置
公开(公告)号：US07623450B2
公开(公告)日：2009-11-24
申请号：US11388011
申请日：2006-03-23
申请人： Claude Basso , Jean Louis Calvignac , Ronald Edward Fuhs , Nathaniel Paul Sellin , Colin Beaton Verrilli , Scott Michael Willenborg
发明人： Claude Basso , Jean Louis Calvignac , Ronald Edward Fuhs , Nathaniel Paul Sellin , Colin Beaton Verrilli , Scott Michael Willenborg
IPC分类号： H04L1/00
CPC分类号： H04L49/9042 , H04L49/90 , H04L69/22
摘要： In a first aspect, a first method of transmitting a data packet is provided. The first method includes the steps of (1) for each connection from which a data packet may be transmitted, storing header data corresponding to the connection; (2) employing a user application to form header and payload data of a packet, wherein the user application is associated with a connection from which the packet is to be transmitted; and (3) while transmitting the packet, comparing one or more portions of the packet header data with the header data corresponding to the connection with which the user application is associated. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了发送数据分组的第一种方法。第一种方法包括以下步骤：（1）对于可以从其发送数据分组的每个连接，存储对应于该连接的头部数据; （2）使用用户应用来形成分组的报头和有效载荷数据，其中所述用户应用与要发送所述分组的连接相关联; 和（3）在发送分组时，将分组报头数据的一个或多个部分与对应于用户应用所关联的连接的报头数据进行比较。提供了许多其他方面。

60. 发明授权

US07529224B2 Scheduler, network processor, and methods for weighted best effort scheduling 失效
标题翻译：调度器，网络处理器和加权最佳努力调度的方法
公开(公告)号：US07529224B2
公开(公告)日：2009-05-05
申请号：US11108485
申请日：2005-04-18
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
IPC分类号： H04L12/28
CPC分类号： H04L47/568 , H04L45/00 , H04L45/60 , H04L47/50 , H04L47/527
摘要： Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a three-entry calendar structure provides for weighted best effort scheduling. Each of a plurality different flows has an associated schedule control block. Schedule control blocks are stored as linked lists in a last-in-first-out buffer. Each calendar entry is associated with a different linked list by storing in the calendar entry the address of the first-out schedule control block in the linked list. Each schedule control block has a counter and is assigned a weight according to the bandwidth priority of the flow to which the corresponding packet belongs. Each time a schedule control block is accessed from a last-in-first-out buffer storing the linked list, the scheduler generates a scheduling event and the counter of the schedule control block is incremented. When an incremented counter of a schedule control block equals its weight, the schedule control block is temporarily removed from further scheduling.
摘要翻译：公开了一种用于在网络处理器中调度数据分组的系统和方法。实施例提供了一种网络处理器，其包括具有用于寻址日程控制块的最小日历结构的尽力而为调度器。在一个实施例中，三入口日历结构提供加权最佳努力调度。多个不同的流中的每一个具有相关的进度控制块。计划控制块作为链表存储在先进先出缓冲区中。通过在日历条目中存储链表中的先出时间表控制块的地址来将每个日历条目与不同的链表相关联。每个调度控制块具有计数器，并根据相应分组所属的流的带宽优先级分配权重。每当从存储链表的最先进先出缓冲器访问调度控制块时，调度器生成调度事件，并且调度控制块的计数器递增。当调度控制块的递增计数器等于其权重时，调度控制块暂时从进一步调度中移除。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式