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51. 发明授权

US5446909A Binary multiplication implemented by existing hardware with minor modifications to sequentially designate bits of the operand 失效
标题翻译：由现有硬件实现的二进制乘法，稍作修改，以顺序指定操作数的位
公开(公告)号：US5446909A
公开(公告)日：1995-08-29
申请号：US989219
申请日：1992-12-11
申请人： Gideon Intrater , Ohad Falik , Aharon Ostrer , Yair Baydatch , Gadi Erlich
发明人： Gideon Intrater , Ohad Falik , Aharon Ostrer , Yair Baydatch , Gadi Erlich
IPC分类号： G06F7/53 , G06F7/52 , G06F7/523 , G06F7/72 , G06F9/302 , G06F7/50
CPC分类号： G06F7/5272 , G06F7/727 , G06F9/3001 , G06F7/49931 , G06F7/722
摘要： Binary multiplication is performed with existing data processing apparatus to which only minor modifications are required. One operand and a partial product are stored in existing latches of a CPU. The second operand is stored in a shift register which is added to the CPU. The data in the shift register is shifted from the LSB to the MSB, with a "0" being loaded into the LSB. As the bits in the first operand are designated in sequence, the value of the partial product is increased by the value in the shift register if the designated bit is a "1". After the sequencing has designated all the bits of the first operand, the partial product is taken to be the product of the multiplication.
摘要翻译：对现有的数据处理装置执行二进制乘法，仅需要稍微的修改。一个操作数和部分产品存储在CPU的现有锁存器中。第二个操作数存储在添加到CPU的移位寄存器中。移位寄存器中的数据从LSB移位到MSB，“LSB”加载。由于第一操作数中的位按顺序指定，所以如果指定位为“1”，则部分乘积的值会增加移位寄存器中的值。在排序指定了第一个操作数的所有位之后，部分乘积被认为是乘法的乘积。

52. 发明授权

US09098274B2 Methods and apparatuses to improve turbo performance for events handling 有权
标题翻译：提高事件处理的涡轮性能的方法和装置
公开(公告)号：US09098274B2
公开(公告)日：2015-08-04
申请号：US12630438
申请日：2009-12-03
申请人： Ryan D. Wells , Ohad Falik , Mary Jean Allarey
发明人： Ryan D. Wells , Ohad Falik , Jose P. Allarey
IPC分类号： G06F1/32 , G06F9/50
CPC分类号： G06F1/324 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/3234 , G06F1/3237 , G06F1/3243 , G06F1/3246 , G06F1/3287 , G06F1/329 , G06F1/3293 , G06F1/3296 , G06F9/5027 , G06F9/5094 , G06F2209/501 , Y02D10/126 , Y02D10/17 , Y02D10/171 , Y02D10/22 , Y02D10/26 , Y02D50/20
摘要： Embodiments of an apparatus for improving performance for events handling are presented. In one embodiment, the apparatus includes a number of processing elements and task routing logic. If at least one of the processing elements is in a turbo mode, the task routing logic selects a processing element for executing a task based at least on a comparison of performance losses.
摘要翻译：介绍了一种改善事件处理性能的装置的实施例。在一个实施例中，该装置包括多个处理元件和任务布线逻辑。如果至少一个处理元件处于turbo模式，则任务路由逻辑至少基于性能损失的比较来选择用于执行任务的处理元件。

53. 发明申请

US20140095911A1 Controlling Power Consumption By Power Management Link 有权
标题翻译：通过电源管理链路控制功耗
公开(公告)号：US20140095911A1
公开(公告)日：2014-04-03
申请号：US13631907
申请日：2012-09-29
申请人： Nir Rosenzweig , Efraim Rotem , Jawad Haj-Yihia , Ohad Falik
发明人： Nir Rosenzweig , Efraim Rotem , Jawad Haj-Yihia , Ohad Falik
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/3203 , G06F1/3209 , G06F1/3215 , G06F1/3287 , Y02D10/171
摘要： Methods and apparatus relating to controlling power consumption by a power management link are described. In one embodiment, the physical interface of a power management (PM) link is shut down when a processor is in a sleep state (e.g., to conserve power), while maintaining the availability of the processor for communication to a (e.g., embedded) controller over the PM link. Other embodiments are also disclosed and claimed.
摘要翻译：描述了通过电力管理链路控制电力消耗的方法和装置。在一个实施例中，当处理器处于休眠状态（例如，以节省功率）时，功率管理（PM）链路的物理接口被关闭，同时保持用于通信的处理器的可用性（例如，嵌入式）控制器通过PM链路。还公开并要求保护其他实施例。

54. 发明授权

US07788483B1 Method and apparatus of identifying and enabling of functions of a trusted platform module device 有权
标题翻译：识别和启用可信平台模块设备功能的方法和装置
公开(公告)号：US07788483B1
公开(公告)日：2010-08-31
申请号：US11124917
申请日：2005-05-09
申请人： Ohad Falik , Dan Morav
发明人： Ohad Falik , Dan Morav
IPC分类号： H04L29/06
CPC分类号： H04L63/061 , H04L9/3263 , H04L63/0823 , H04L2209/127 , H04L2209/56
摘要： A method is disclosed for a certifying authority (CA) to establish a secure status and authenticity in an integrated circuit (IC). Cryptographic logic and certification logic are incorporated in the IC by an IC manufacturer. The cryptographic logic is operable to generate a cryptographic key intended to be communicated external to the IC. The certification logic includes a certification key intended for use in establishing a secure certification arrangement. The certification key is communicated securely to the CA and a secure certification arrangement is established between the CA and the IC using the certification key. During the secure certification arrangement, the cryptographic key is accessed by the CA to certify the cryptographic key associated with the IC and in response thereto the certification key is deleted and the secured certification arrangement is terminated.
摘要翻译：公开了一种用于认证机构（CA）在集成电路（IC）中建立安全状态和真实性的方法。加密逻辑和认证逻辑由IC制造商纳入IC。加密逻辑可操作以产生旨在在IC外部通信的加密密钥。认证逻辑包括旨在用于建立安全认证安排的认证密钥。证书密钥安全地传送给CA，并且使用认证密钥在CA和IC之间建立安全的认证安排。在安全认证安排期间，加密密钥由CA访问以证明与IC相关联的加密密钥，并且响应于此，认证密钥被删除并且安全证书安排被终止。

55. 发明授权

US07606955B1 Single wire bus for connecting devices and methods of operating the same 有权
标题翻译：用于连接设备的单线总线及其操作方法
公开(公告)号：US07606955B1
公开(公告)日：2009-10-20
申请号：US10931933
申请日：2004-09-01
申请人： Ohad Falik , Victor Flachs
发明人： Ohad Falik , Victor Flachs
IPC分类号： G06F13/00 , G06F3/00 , G06F5/00 , G06F13/42 , G06F15/16
CPC分类号： G06F13/4295
摘要： A master/slave system architecture that includes a single wire bus, a master device and bus interface coupled to the bus. The system further includes plurality of slave devices having respective bus interfaces coupled to the bus. Each of the slave devices having a designated device identification. There is further provided a communication protocol implemented over the single wire bus and employed by the master and the slave devices. The protocol includes bus transactions composed each of bit signals that belong each to a bit signal type from among a plurality of bit signal types. Each bit signal type has a time interval that is discernible from respective time intervals of all other bit signal types from among the plurality of bit signal types.
摘要翻译：主/从系统架构，其包括单线总线，主设备和耦合到总线的总线接口。该系统还包括具有耦合到总线的相应总线接口的多个从设备。每个从设备具有指定的设备标识。还提供了通过单线总线实现并由主设备和从设备采用的通信协议。该协议包括由多个比特信号类型中的每一个位信号组合成位信号类型的总线事务。每个比特信号类型具有从多个比特信号类型中的所有其他比特信号类型的各个时间间隔可以看出的时间间隔。

56. 发明授权

US07562283B2 Systems and methods for error correction using binary coded hexidecimal or hamming decoding 失效
标题翻译：使用二进制编码十六进制或汉明译码进行纠错的系统和方法
公开(公告)号：US07562283B2
公开(公告)日：2009-07-14
申请号：US11325677
申请日：2006-01-05
申请人： Ohad Falik , Yuval Itkin
发明人： Ohad Falik , Yuval Itkin
IPC分类号： H03M13/00
CPC分类号： G06F11/1012 , H03M13/152 , H03M13/159 , H03M13/19 , H03M13/2906
摘要： Systems and methods for error correction of data. In one embodiment of the invention, a plurality of error correction schemes are applied when encoding data and depending on the circumstances, one or more of those schemes is selected to decode the data. In one of these embodiments, the applied error correction schemes include the BCH algorithm and the Hamming algorithm.
摘要翻译：用于数据纠错的系统和方法。在本发明的一个实施例中，在编码数据时应用多个纠错方案，并且根据情况，选择这些方案中的一个或多个来解码数据。在这些实施例中的一个中，应用的纠错方案包括BCH算法和汉明算法。

57. 发明授权

US07318173B1 Embedded controller based BIOS boot ROM select 有权
标题翻译：基于嵌入式控制器的BIOS启动ROM选择
公开(公告)号：US07318173B1
公开(公告)日：2008-01-08
申请号：US10453851
申请日：2003-06-03
申请人： Ohad Falik , Ilia Stolov
发明人： Ohad Falik , Ilia Stolov
IPC分类号： G06F11/00
CPC分类号： G06F11/1433 , G06F9/4401 , G06F9/441
摘要： A method for selecting one of a plurality of BIOS images included in a computer system includes indicating a selection of a BIOS image via a bus by an embedded controller. The method also includes powering up or resetting the system. In addition, the method includes accessing the selected BIOS image for execution.
摘要翻译：一种用于选择包括在计算机系统中的多个BIOS映像之一的方法包括：通过嵌入式控制器通过总线指示BIOS图像的选择。该方法还包括上电或复位系统。此外，该方法包括访问所选择的BIOS映像以供执行。

58. 发明授权

US06173355B2 System for sending and receiving data on a universal serial bus (USB) using a memory shared among a number of endpoints 有权
标题翻译：在通用串行总线（USB）上使用多个端点共享的存储器发送和接收数据的系统
公开(公告)号：US06173355B2
公开(公告)日：2001-01-09
申请号：US09469663
申请日：1999-12-22
申请人： Ohad Falik , David Brief
发明人： Ohad Falik , David Brief
IPC分类号： G06F1314
CPC分类号： G06F13/4295 , H04L1/1835 , H04L1/1848 , H04L49/90 , H04L49/901 , H04L2001/0094
摘要： An apparatus for an method of sending and receiving data on a Universal Serial Bus using a memory shared among a number of end points are disclosed. The memory is a double buffer which allows the next packet to be prepared while the current packet is being transmitted. The invention also supports transmission retry.
摘要翻译：公开了一种使用在多个端点之间共享的存储器在通用串行总线上发送和接收数据的方法的装置。存储器是双缓冲器，其允许在当前分组被发送时准备下一个分组。本发明还支持传输重试。

59. 发明授权

US09311145B2 Using platform idle duration information to notify platform devices of upcoming active periods 有权
标题翻译：使用平台空闲持续时间信息通知平台设备即将到来的活动期间
公开(公告)号：US09311145B2
公开(公告)日：2016-04-12
申请号：US13719898
申请日：2012-12-19
申请人： Christian Maciocco , Ohad Falik , Ren Wang , Tsung-Yuan C. Tai
发明人： Christian Maciocco , Ohad Falik , Ren Wang , Tsung-Yuan C. Tai
IPC分类号： G06F3/00 , G06F9/48 , G06F9/54 , G06F1/32
CPC分类号： G06F9/4893 , G06F1/3206 , G06F9/54 , Y02D10/24
摘要： Methods and systems may provide for determining a next active window for a platform and notifying one or more of a plurality of devices of the platform of the next active window being determined. Additionally, one or more of the plurality of devices may be notified of an onset of the next active window. In one example, a pre-warm message is issued to notify one or more of the plurality of devices of the next active window being determined.
摘要翻译：方法和系统可以提供用于确定平台的下一个活动窗口并通知所确定的下一活动窗口的平台的多个设备中的一个或多个设备。另外，可以向多个设备中的一个或多个通知下一活动窗口的开始。在一个示例中，发出预热消息以通知所确定的下一个活动窗口的多个设备中的一个或多个。

60. 发明授权

US09015510B2 Optimizing energy efficiency using device idle duration information and latency tolerance based on a pre-wake configuration of a platform associated to the device 有权
标题翻译：基于与设备相关联的平台的前唤醒配置，使用设备空闲持续时间信息和延迟容限优化能量效率
公开(公告)号：US09015510B2
公开(公告)日：2015-04-21
申请号：US13537260
申请日：2012-06-29
申请人： Christian Maciocco , Ohad Falik , Ren Wang , Nadav Shulman , Paul Diefenbaugh , Tsung-Yuan Charles Tai
发明人： Christian Maciocco , Ohad Falik , Ren Wang , Nadav Shulman , Paul Diefenbaugh , Tsung-Yuan Charles Tai
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3228
摘要： Systems and methods may provide for aggregating a first idle duration from a first device associated with a platform and a second idle duration from a second device associated with the platform. Additionally, an idle state may be selected for the platform based at least in part on the first idle duration and the second idle duration. In one example, the idle durations are classified as deterministic, estimated or statistical.
摘要翻译：系统和方法可以提供从与平台相关联的第一设备和与平台相关联的第二设备的第二空闲持续时间聚集第一空闲持续时间。另外，可以至少部分地基于第一空闲持续时间和第二空闲持续时间来为平台选择空闲状态。在一个示例中，空闲持续时间被分类为确定性，估计或统计。

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