专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US07759755B2 Anti-reflection structures for CMOS image sensors 有权
标题翻译： CMOS图像传感器的防反射结构
公开(公告)号：US07759755B2
公开(公告)日：2010-07-20
申请号：US12120413
申请日：2008-05-14
申请人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
发明人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
IPC分类号： H01L31/112 , H01L31/0216
CPC分类号： H01L31/103 , H01L24/05 , H01L24/73 , H01L27/14603 , H01L27/1462 , H01L27/14627 , H01L27/14629 , H01L27/1464 , H01L27/14643 , H01L31/02165 , H01L31/0236 , H01L2224/04042 , H01L2224/05 , H01L2224/32225 , H01L2224/48227 , H01L2224/48464 , H01L2224/4847 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01074 , H01L2924/12043 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/3025 , Y02E10/50 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.
摘要翻译：提供了具有不同折射率的两层之间的突起阵列的光学结构。突起阵列具有小于由CMOS图像传感器的光电二极管可检测的光的波长范围的垂直和侧向尺寸。突起的阵列提供了很少的反射光的高透射率。突起阵列可以设置在光电二极管上，后端行互连结构中，用于光电二极管的透镜，光电二极管的背面或芯片封装的窗口上。

52. 发明授权

US07732845B2 Pixel sensor with reduced image lag 有权
标题翻译：具有降低图像滞后的像素传感器
公开(公告)号：US07732845B2
公开(公告)日：2010-06-08
申请号：US12099339
申请日：2008-04-08
申请人： James W Adkisson , Jeffrey P. Gambino , Rajendran Krishnasamy , Solomon Mulugeta
发明人： James W Adkisson , Jeffrey P. Gambino , Rajendran Krishnasamy , Solomon Mulugeta
IPC分类号： H01L31/062
CPC分类号： H01L27/14603
摘要： A tensile-stress-generating structure is formed above a gate electrode in a CMOS image sensor to apply a normal tensile stress between a charge collection well of a photodiode, which is also a source region of a transfer transistor, and a floating drain in the direction connecting the source region and the floating drain. The tensile stress lowers the potential barrier between the source region and the body of the transfer transistor to effect a faster and more through transfer of the electrical charges in the source region to the floating drain. Image lag is thus reduced in the CMOS image sensor. Further, charge capacity of the source region is also enhanced due to the normal tensile stress applied to the source region.
摘要翻译：在CMOS图像传感器的栅电极上方形成拉伸应力产生结构，以在也是转移晶体管的源极区域的光电二极管的电荷收集阱和浮动漏极之间施加正常的拉伸应力连接源极区域和浮动漏极的方向。拉伸应力降低了源区域和转移晶体管的主体之间的势垒，以实现更快和更多地将源区域中的电荷转移到浮动漏极。因此CMOS图像传感器中的图像滞后减少。此外，由于施加到源极区域的正常拉伸应力，源极区域的充电容量也增强。

53. 发明申请

US20090283807A1 Anti-Reflection Structures For CMOS Image Sensors 有权
标题翻译： CMOS图像传感器的防反射结构
公开(公告)号：US20090283807A1
公开(公告)日：2009-11-19
申请号：US12120413
申请日：2008-05-14
申请人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
发明人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
IPC分类号： H01L31/0232
CPC分类号： H01L31/103 , H01L24/05 , H01L24/73 , H01L27/14603 , H01L27/1462 , H01L27/14627 , H01L27/14629 , H01L27/1464 , H01L27/14643 , H01L31/02165 , H01L31/0236 , H01L2224/04042 , H01L2224/05 , H01L2224/32225 , H01L2224/48227 , H01L2224/48464 , H01L2224/4847 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01074 , H01L2924/12043 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/3025 , Y02E10/50 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.
摘要翻译：提供了具有不同折射率的两层之间的突起阵列的光学结构。突起阵列具有小于由CMOS图像传感器的光电二极管可检测的光的波长范围的垂直和侧向尺寸。突起的阵列提供了很少的反射光的高透射率。突起阵列可以设置在光电二极管上，后端行互连结构中，用于光电二极管的透镜，光电二极管的背面或芯片封装的窗口上。

54. 发明授权

US06670255B2 Method of fabricating lateral diodes and bipolar transistors 有权
标题翻译：制造横向二极管和双极晶体管的方法
公开(公告)号：US06670255B2
公开(公告)日：2003-12-30
申请号：US09965289
申请日：2001-09-27
申请人： James W. Adkisson , Jeffrey P. Gambino , Peter B. Gray , Anthony K. Stamper
发明人： James W. Adkisson , Jeffrey P. Gambino , Peter B. Gray , Anthony K. Stamper
IPC分类号： H01L21331
CPC分类号： H01L27/1203 , H01L27/0664
摘要： Disclosed is a method of fabricating a lateral semiconductor device, comprising: providing a substrate, having at least an upper silicon portion forming at least one first dopant type region and at least one second dopant type region in the upper portion of the substrate, at least one of the first dopant type regions abutting at least one of the second dopant type regions and thereby forming at least one PN junction; and forming at least one protective island on a top surface of the upper silicon portion, the protective island extending the length of the PN junction and overlapping a portion of the first dopant type region and a portion of an abutting second dopant type region.
摘要翻译：公开了一种制造横向半导体器件的方法，包括：提供衬底，至少具有在衬底的上部中至少形成至少一个第一掺杂剂型区域和至少一个第二掺杂剂类型区域的上硅部分，至少第一掺杂剂类型区域中的一个与第二掺杂剂类型区域中的至少一个邻接，从而形成至少一个PN结; 以及在所述上硅部分的顶表面上形成至少一个保护岛，所述保护岛延伸所述PN结的长度并与所述第一掺杂剂型区域的一部分和邻接的第二掺杂剂型区域的一部分重叠。

55. 发明授权

US06350653B1 Embedded DRAM on silicon-on-insulator substrate 有权
标题翻译：绝缘体上硅衬底上的嵌入式DRAM
公开(公告)号：US06350653B1
公开(公告)日：2002-02-26
申请号：US09689096
申请日：2000-10-12
申请人： James W. Adkisson , Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman
发明人： James W. Adkisson , Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman
IPC分类号： H01L21336
CPC分类号： H01L27/10864 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions and logic devices are formed in silicon-on-insulator (“SOI”) regions and where buried, doped glass is used as a mask to form deep trenches for storage in the bulk region. The resulting structure is also disclosed.
摘要翻译：提出了一种半导体器件，其涉及一种形成嵌入式DRAM和逻辑器件的方法，其中DRAM器件以块状形成，单晶半导体区域和逻辑器件形成在绝缘体上硅（“SOI”）区域中，其中掩埋的掺杂玻璃用作掩模以形成用于存储在本体区域中的深沟槽。还公开了所得到的结构。

56. 发明授权

US08138534B2 Anti-reflection structures for CMOS image sensors 有权
标题翻译： CMOS图像传感器的防反射结构
公开(公告)号：US08138534B2
公开(公告)日：2012-03-20
申请号：US12770349
申请日：2010-04-29
申请人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
发明人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
IPC分类号： H01L31/10 , H01L31/112
CPC分类号： H01L31/103 , H01L24/05 , H01L24/73 , H01L27/14603 , H01L27/1462 , H01L27/14627 , H01L27/14629 , H01L27/1464 , H01L27/14643 , H01L31/02165 , H01L31/0236 , H01L2224/04042 , H01L2224/05 , H01L2224/32225 , H01L2224/48227 , H01L2224/48464 , H01L2224/4847 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01074 , H01L2924/12043 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/3025 , Y02E10/50 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.
摘要翻译：提供了具有不同折射率的两层之间的突起阵列的光学结构。突起阵列具有小于由CMOS图像传感器的光电二极管可检测的光的波长范围的垂直和侧向尺寸。突起的阵列提供了很少的反射光的高透射率。突起阵列可以设置在光电二极管上，后端行互连结构中，用于光电二极管的透镜，光电二极管的背面或芯片封装的窗口上。

57. 发明申请

US20090250733A1 PIXEL SENSOR WITH REDUCED IMAGE LAG 有权
标题翻译：像素传感器与减少图像LAG
公开(公告)号：US20090250733A1
公开(公告)日：2009-10-08
申请号：US12099339
申请日：2008-04-08
申请人： James W. Adkisson , Jeffrey P. Gambino , Rajendran Krishnasamy , Solomon Mulugeta
发明人： James W. Adkisson , Jeffrey P. Gambino , Rajendran Krishnasamy , Solomon Mulugeta
IPC分类号： H01L31/00 , H01L21/00 , G06F9/45
CPC分类号： H01L27/14603
摘要： A tensile-stress-generating structure is formed above a gate electrode in a CMOS image sensor to apply a normal tensile stress between a charge collection well of a photodiode, which is also a source region of a transfer transistor, and a floating drain in the direction connecting the source region and the floating drain. The tensile stress lowers the potential barrier between the source region and the body of the transfer transistor to effect a faster and more through transfer of the electrical charges in the source region to the floating drain. Image lag is thus reduced in the CMOS image sensor. Further, charge capacity of the source region is also enhanced due to the normal tensile stress applied to the source region.
摘要翻译：在CMOS图像传感器的栅电极上方形成拉伸应力产生结构，以在也是转移晶体管的源极区域的光电二极管的电荷收集阱和浮动漏极之间施加正常的拉伸应力连接源极区域和浮动漏极的方向。拉伸应力降低了源区域和转移晶体管的主体之间的势垒，以实现更快和更多地将源区域中的电荷转移到浮动漏极。因此CMOS图像传感器中的图像滞后减少。此外，由于施加到源极区域的正常拉伸应力，源极区域的充电容量也增强。

58. 发明申请

US20090193378A1 MODIFYING LAYOUT OF IC BASED ON FUNCTION OF INTERCONNECT AND RELATED CIRCUIT AND DESIGN STRUCTURE 有权
标题翻译：基于互连和相关电路和设计结构的功能修改IC布局
公开(公告)号：US20090193378A1
公开(公告)日：2009-07-30
申请号：US12021333
申请日：2008-01-29
申请人： James W. Adkisson , Natalie B. Feilchenfeld , Jeffrey P. Gambino , Howard S. Landis , Benjamin T. Voegeli , Steven H. Voldman , Michael J. Zierak
发明人： James W. Adkisson , Natalie B. Feilchenfeld , Jeffrey P. Gambino , Howard S. Landis , Benjamin T. Voegeli , Steven H. Voldman , Michael J. Zierak
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Modifying a layout of an integrated circuit (IC) based on a function of an interconnect therein and a related circuit and design structure are disclosed. In one embodiment, a method includes identifying a function of an interconnect in the layout from data of the layout embodied in a computer readable medium; and modifying the layout to form another layout that accommodates the function of the interconnect. A design structure embodied in a machine readable medium used in a design process, according to one embodiment, may include a circuit including a high voltage interconnect positioned in a dielectric layer, the high voltage interconnect positioned such that no fill is above or below the high voltage interconnect.
摘要翻译：公开了基于互连功能的集成电路（IC）的布局以及相关的电路和设计结构。在一个实施例中，一种方法包括根据体现在计算机可读介质中的布局的数据来识别布局中的互连的功能; 并修改布局以形成适应互连功能的另一布局。根据一个实施例，在设计过程中使用的机器可读介质中体现的设计结构可以包括电路，其包括定位在电介质层中的高电压互连，所述高电压互连定位成使得没有填充物高于或低于高电压互连。

59. 发明申请

US20090108347A1 LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH ASYMMETRIC GATE DIELECTRIC PROFILE 有权
标题翻译：具有不对称栅介质剖面的横向扩散场效应晶体管
公开(公告)号：US20090108347A1
公开(公告)日：2009-04-30
申请号：US11924650
申请日：2007-10-26
申请人： James W. Adkisson , Natalie B. Feilchenfeld , Jeffrey P. Gambino , Benjamin T. Voegeli , Michael J. Zierak
发明人： James W. Adkisson , Natalie B. Feilchenfeld , Jeffrey P. Gambino , Benjamin T. Voegeli , Michael J. Zierak
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L29/1045 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/512 , H01L29/66659
摘要： A gate stack comprising a uniform thickness gate dielectric, a gate electrode, and an oxygen-diffusion-resistant gate cap is formed on a semiconductor substrate. Thermal oxidation is performed only on the drain side of the gate electrode, while the source side is protected from thermal oxidation. A thermal oxide on the drain side sidewall of the gate electrode is integrally formed with a graded thickness silicon oxide containing gate dielectric, of which the thickness monotonically increases from the source side to the drain side. The thickness profile may be self-aligned to the drain side edge of the gate electrode, or may have a portion with a self-limiting thickness. The graded thickness profile may be advantageously used to form a lateral diffusion metal oxide semiconductor field effect transistor providing an enhanced performance.
摘要翻译：在半导体基板上形成包括均匀厚度的栅极电介质，栅电极和耐氧扩散栅极盖的栅极堆叠。仅在栅电极的漏极侧进行热氧化，同时防止源极侧受热氧化。栅电极的漏极侧壁上的热氧化物与层状厚度的含氧化硅的栅极电介质整体形成，其厚度从源极侧向漏极侧单调增加。厚度分布可以与栅电极的漏极侧边缘自对准，或者可以具有自限制厚度的部分。梯度厚度分布可以有利地用于形成提供增强性能的横向扩散金属氧化物半导体场效应晶体管。

60. 发明申请

US20090090983A1 DUAL WORK FUNCTION HIGH VOLTAGE DEVICES 审中-公开
标题翻译：双功能高压器件
公开(公告)号：US20090090983A1
公开(公告)日：2009-04-09
申请号：US11866594
申请日：2007-10-03
申请人： James W. Adkisson , Jeffrey P. Gambino , Edward J. Nowak , Steven H. Voldman , Michael J. Zierak
发明人： James W. Adkisson , Jeffrey P. Gambino , Edward J. Nowak , Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L29/78
CPC分类号： H01L29/4983 , H01L29/41725 , H01L29/41775 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/7835
摘要： A transistor has a substrate having a channel region and source and drain regions within the substrate on opposite sides of the channel region. The structure includes a gate oxide above the channel region of the substrate and a gate conductor above the gate oxide. The polysilicon gate conductor comprises a source side positioned toward the source and a drain side positioned toward the drain. The source side comprises a first concentration of conductive doping and the drain side comprises a second concentration of the conductive doping that is less than the first concentration.
摘要翻译：晶体管具有衬底，该衬底具有在沟道区域的相对侧上的衬底内的沟道区和源极和漏极区。该结构包括在衬底的沟道区上方的栅极氧化物和栅极氧化物上方的栅极导体。多晶硅栅极导体包括位于源极侧的源极侧和朝向漏极定位的漏极侧。源侧包括第一浓度的导电掺杂，而漏极侧包括小于第一浓度的导电掺杂的第二浓度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式