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51. 发明授权

US06503798B1 Low resistance strap for high density trench DRAMS 失效
标题翻译：低电阻带用于高密度沟槽DRAMS
公开(公告)号：US06503798B1
公开(公告)日：2003-01-07
申请号：US09609168
申请日：2000-06-30
申请人： Ramachandra Divakaruni , Jeffrey P. Gambino , Herbert L. Ho , Akira Sudo
发明人： Ramachandra Divakaruni , Jeffrey P. Gambino , Herbert L. Ho , Akira Sudo
IPC分类号： H01L21336
CPC分类号： H01L27/10867
摘要： A method and structure for a dynamic random access device which includes a substrate having a trench, a conductor in the trench, a transistor adjacent the trench and a conductive strap electrically connecting the conductor and the transistor, wherein the strap comprises a plurality of strap conductors and the strap has a lower resistance than the conductor. The conductor comprises a first material having a first resistance and the strap comprises a second material different than the first material having a second resistance, wherein the second resistance is lower than the first resistance. The plurality of strap conductors comprises at least two electrically connected strap conductors, and a first strap conductor is adjacent the conductor and a second strap conductor is adjacent the transistor and the first strap conductor has an improved interface with the conductor. The strap comprises a lip strap, wherein the strap forms an L-shape. At least one of the plurality of the strap conductors is contiguous with a corner of the trench, and the plurality of strap conductors comprises a first strap conductor and a second strap conductor and the conductor is contiguous with the first strap conductor and the second strap conductor such that the second strap conductor and the conductor form an L-shape.
摘要翻译：一种用于动态随机存取装置的方法和结构，其包括具有沟槽的衬底，沟槽中的导体，与沟槽相邻的晶体管和电连接导体和晶体管的导电带，其中带包括多个带状导体并且带子具有比导体更低的电阻。导体包括具有第一电阻的第一材料，并且带包括不同于具有第二电阻的第一材料的第二材料，其中第二电阻低于第一电阻。多个带状导体包括至少两个电连接的带状导体，并且第一带导体与导体相邻，并且第二带导体与晶体管相邻，并且第一带导体具有与导体的改进的界面。带子包括唇带，其中带子形成L形。所述多个带状导体中的至少一个与所述沟槽的角部邻接，并且所述多个带状导体包括第一带状导体和第二带状导体，并且所述导体与所述第一带状导体和所述第二带状导体使得第二带状导体和导体形成L形。

52. 发明授权

US06495876B1 DRAM strap: hydrogen annealing for improved strap resistance in high density trench DRAMS 失效
标题翻译： DRAM带：用于改善高密度沟槽DRAMS中的带状电阻的氢退火
公开(公告)号：US06495876B1
公开(公告)日：2002-12-17
申请号：US09609288
申请日：2000-06-30
申请人： Gary Bronner , Ramachandra Divakaruni , Yoichi Takegawa
发明人： Gary Bronner , Ramachandra Divakaruni , Yoichi Takegawa
IPC分类号： H01L27108
CPC分类号： H01L21/3003 , H01L27/10867
摘要： A method and structure for a DRAM device which includes a trench within an insulator, a conductor within the trench, a transistor adjacent a first side of the trench, and a shallow trench isolation region formed within a top portion of the conductor on a second side of the trench, opposite the first side, wherein the top portion of the conductor has a curved shape at an edge of the shallow trench isolation region. The curved shape comprises a conductive strap and electrically connects the conductor and the single crystal where the transistor is formed, further comprising a collar oxide surrounding the top portion of the conductor, the collar oxide controlling a shape and location of the curved shape. The curved shape is formed by hydrogen annealing, and may be convex, or concave. The DRAM further comprising a collar oxide extending into the shallow trench isolation region on the second side.
摘要翻译：一种用于DRAM器件的方法和结构，其包括绝缘体内的沟槽，沟槽内的导体，与沟槽的第一侧相邻的晶体管，以及形成在第二侧的导体的顶部内的浅沟槽隔离区所述沟槽的第一侧相对，其中所述导体的顶部在所述浅沟槽隔离区域的边缘处具有弯曲形状。弯曲形状包括导电带并且电连接导体和形成晶体管的单晶，还包括围绕导体顶部的环形氧化物，该环形氧化物控制弯曲形状的形状和位置。弯曲形状由氢退火形成，并且可以是凸形或凹形。 DRAM还包括延伸到第二侧上的浅沟槽隔离区域的环状氧化物。

53. 发明授权

US06448131B1 Method for increasing the capacitance of a trench capacitor 失效
标题翻译：增加沟槽电容器电容的方法
公开(公告)号：US06448131B1
公开(公告)日：2002-09-10
申请号：US09929182
申请日：2001-08-14
申请人： Cyril Cabral, Jr. , Kevin K. Chan , Guy M. Cohen , Ramachandra Divakaruni , Christian Lavoie , Fenton R. McFeely
发明人： Cyril Cabral, Jr. , Kevin K. Chan , Guy M. Cohen , Ramachandra Divakaruni , Christian Lavoie , Fenton R. McFeely
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L28/84 , H01L29/66181 , Y10S438/964
摘要： A method for increasing the trench capacitor surface area is provided. The method, which utilizes a metal silicide to roughen the trench walls, increases capacitance due to the increase in the trench surface area after the silicide has been removed. The roughening of the trench walls can be controlled by varying one or more of the following parameters: the density of the metal, the metal film thickness, the silicide phase, and the choice of the metal. Once the metal is deposited in the trench, the method is self-limited. Shrinking the trench to its original width can be obtained by subsequent silicon deposition or by diffusion of silicon from a cap layer through the silicide.
摘要翻译：提供了一种用于增加沟槽电容器表面积的方法。利用金属硅化物粗糙化沟槽壁的方法由于硅化物被去除之后的沟槽表面积的增加而增加了电容。可以通过改变一个或多个以下参数来控制沟槽壁的粗糙化：金属的密度，金属膜厚度，硅化物相以及金属的选择。一旦金属沉积在沟槽中，该方法是自限制的。通过随后的硅沉积或通过硅化物从盖层扩散硅可以获得将沟槽缩小至原始宽度。

54. 发明授权

US06441422B1 Structure and method for ultra-scalable hybrid DRAM cell with contacted P-well 失效
标题翻译：具有接触P阱的超可扩展混合DRAM单元的结构和方法
公开(公告)号：US06441422B1
公开(公告)日：2002-08-27
申请号：US09706482
申请日：2000-11-03
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Jai-hoon Sim
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Jai-hoon Sim
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10867
摘要： An ultra-scalable hybrid memory cell having a low junction leakage and a process of fabricating the same are provided. The ultra-scalable hybrid memory cell contains a conductive connection to the body region therefore avoiding isolation of the P-well due to cut-off by the buried strap outdiffusion region. The ultra-scalable hybrid memory cell avoids the above by using a shallower than normal isolation region that allows the P-well to remain connected to the body of the memory cell.
摘要翻译：提供具有低结漏电的超可扩展混合存储器单元及其制造工艺。超可扩展混合存储器单元包含与身体区域的导电连接，从而避免由于掩埋带外扩散区域而导致的P阱的隔离。超可扩展混合存储器单元通过使用允许P阱保持连接到存储器单元的主体的比普通隔离区更浅的方式来避免上述情况。

55. 发明授权

US06440793B1 Vertical MOSFET 失效
公开(公告)号：US06440793B1
公开(公告)日：2002-08-27
申请号：US09757514
申请日：2001-01-10
申请人： Ramachandra Divakaruni , Heon Lee , Jack A. Mandelman , Carl J. Radens , Jai-Hoon Sim
发明人： Ramachandra Divakaruni , Heon Lee , Jack A. Mandelman , Carl J. Radens , Jai-Hoon Sim
IPC分类号： H01L218242
CPC分类号： H01L27/10841 , H01L21/2255 , H01L21/26586 , H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.

56. 发明授权

US06429068B1 Structure and method of fabricating embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect 失效
标题翻译：用硅化硅线和多晶硅互连制造嵌入式垂直DRAM阵列的结构和方法
公开(公告)号：US06429068B1
公开(公告)日：2002-08-06
申请号：US09897868
申请日：2001-07-02
申请人： Ramachandra Divakaruni , Ulrike Gruening , Jack A. Mandelman , Larry Nesbit , Carl Radens
发明人： Ramachandra Divakaruni , Ulrike Gruening , Jack A. Mandelman , Larry Nesbit , Carl Radens
IPC分类号： H01L218242
CPC分类号： H01L27/10891 , H01L27/10864 , H01L27/10876 , H01L27/10894
摘要： A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.
摘要翻译：用于制造嵌入式垂直DRAM单元的结构和工艺包括在阵列区域中制造具有硅化多晶硅层的垂直MOSFET DRAM单元，着陆焊盘和/或互连结构，支撑源极和漏极区域和/或栅极堆叠。该工艺消除了对M0金属化层的需要。

57. 发明授权

US06426247B1 Low bitline capacitance structure and method of making same 失效
标题翻译：低位线电容结构及其制作方法
公开(公告)号：US06426247B1
公开(公告)日：2002-07-30
申请号：US09764824
申请日：2001-01-17
申请人： Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Rajesh Rengarajan
发明人： Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Rajesh Rengarajan
IPC分类号： H01L21338
CPC分类号： H01L27/10888 , H01L23/485 , H01L27/10861 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a memory device having low bitline capacitance, comprising: providing a gate conductor stack structure on a silicon substrate, said gate stack structure having a gate oxide layer, a polysilicon layer, a silicide layer, and a top dielectric nitride layer; oxidizing sidewalls of said gate oxide stack; forming sidewall spacers on the sidewalls of said gate conductor stack, said sidewall spacers comprising a thin layer of nitride having a thickness ranging from about 50 to about 250 angstroms; overlaying the gate structure with a thin nitride liner having a thickness ranging from about 25 to about 150 angstroms; depositing an insulative oxide layer over the gate structure; polishing the insulative oxide layer down to the level of the nitride liner of the gate structure; patterning and etching the insulative oxide layer to expose said nitride liner; forming second sidewall spacers over said first sidewall spacers, said second sidewall spacers comprising an oxide layer having a thickness ranging from about 100 to about 400 angstroms; and, depositing and planarizing a layer of polysilicon covering said gate structure and the sidewall spacers.
摘要翻译：一种用于形成具有低位线电容的存储器件的方法，包括：在硅衬底上提供栅极导体堆叠结构，所述栅堆叠结构具有栅极氧化层，多晶硅层，硅化物层和顶部电介质氮化物层; 氧化所述栅极氧化层的侧壁; 在所述栅极导体堆叠的侧壁上形成侧壁间隔物，所述侧壁间隔物包括厚度范围为约50至约250埃的薄氮化物层; 用具有约25至约150埃的厚度的薄氮化物衬垫覆盖栅极结构; 在栅极结构上沉积绝缘氧化物层; 将绝缘氧化物层抛光到栅极结构的氮化物衬垫的水平面; 图案化和蚀刻绝缘氧化物层以暴露所述氮化物衬垫; 在所述第一侧壁间隔物上形成第二侧壁间隔物，所述第二侧壁间隔物包括厚度范围为约100至约400埃的氧化物层; 并且沉积和平坦化覆盖所述栅极结构和侧壁间隔物的多晶硅层。

58. 发明授权

US08759172B2 Etch stop layer formation in metal gate process 失效
标题翻译：在金属栅极工艺中形成蚀刻停止层
公开(公告)号：US08759172B2
公开(公告)日：2014-06-24
申请号：US13449433
申请日：2012-04-18
申请人： Zhengwen Li , Michael P. Chudzik , Ramachandra Divakaruni , Siddarth A. Krishnan , Unoh Kwon , Richard S. Wise
发明人： Zhengwen Li , Michael P. Chudzik , Ramachandra Divakaruni , Siddarth A. Krishnan , Unoh Kwon , Richard S. Wise
IPC分类号： H01L21/336
CPC分类号： H01L29/517 , H01L21/02126 , H01L21/02164 , H01L21/02208 , H01L21/0228 , H01L21/31116 , H01L21/76834 , H01L21/76897 , H01L29/495 , H01L29/66545
摘要： A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.
摘要翻译：一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构的金属栅极导体。栅极电介质盖形成在金属栅极导体上。栅极电介质盖是由栅极导体的金属元件催化的氧化硅，使得栅极电介质盖的边缘与金属栅极导体的侧壁对准。接触件然后形成在栅极结构的相对侧上的源极区域和漏极区域中的至少一个，其中栅极电介质盖阻挡触点与金属栅极导体接触。

59. 发明申请

US20130277764A1 Etch Stop Layer Formation In Metal Gate Process 失效
标题翻译：金属浇口工艺中的蚀刻停止层形成
公开(公告)号：US20130277764A1
公开(公告)日：2013-10-24
申请号：US13449433
申请日：2012-04-18
申请人： Zhengwen Li , Michael P. Chudzik , Ramachandra Divakaruni , Siddarth A. Krishnan , Unoh Kwon , Richard S. Wise
发明人： Zhengwen Li , Michael P. Chudzik , Ramachandra Divakaruni , Siddarth A. Krishnan , Unoh Kwon , Richard S. Wise
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/517 , H01L21/02126 , H01L21/02164 , H01L21/02208 , H01L21/0228 , H01L21/31116 , H01L21/76834 , H01L21/76897 , H01L29/495 , H01L29/66545
摘要： A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.
摘要翻译：一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构的金属栅极导体。栅极电介质盖形成在金属栅极导体上。栅极电介质盖是由栅极导体的金属元件催化的氧化硅，使得栅极电介质盖的边缘与金属栅极导体的侧壁对准。接触件然后形成在栅极结构的相对侧上的源极区域和漏极区域中的至少一个，其中栅极电介质盖阻挡触点与金属栅极导体接触。

60. 发明申请

US20130256802A1 Replacement Gate With Reduced Gate Leakage Current 审中-公开
标题翻译：降低闸门泄漏电流的更换门
公开(公告)号：US20130256802A1
公开(公告)日：2013-10-03
申请号：US13430755
申请日：2012-03-27
申请人： Hemanth Jagannathan , Ramachandra Divakaruni , Unoh Kwon , Vijay Narayanan , Ravikumar Ramachandran
发明人： Hemanth Jagannathan , Ramachandra Divakaruni , Unoh Kwon , Vijay Narayanan , Ravikumar Ramachandran
IPC分类号： H01L27/088 , H01L21/283
CPC分类号： H01L21/28518 , H01L21/26506 , H01L21/28088 , H01L21/28176 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L29/105 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659 , H01L29/7833 , H01L29/7848
摘要： Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material, which provides, in combination with other layer, a work function about 4.4 eV or less, and can include a material selected from tantalum carbide, metallic nitrides, and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel. Optionally, carbon doping can be introduced in the channel.
摘要翻译：提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。金属化合物层包括与其它层组合提供约4.4eV或更低的功函数的材料，并且可以包括选自碳化钽，金属氮化物和铪硅合金的材料。因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。任选地，可以在通道中引入碳掺杂。

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