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51. 发明申请

US20060035474A1 Increasing retention time for memory devices 审中-公开
标题翻译：增加存储设备的保留时间
公开(公告)号：US20060035474A1
公开(公告)日：2006-02-16
申请号：US10914827
申请日：2004-08-10
申请人： Pavel Komilovich , James Stasiak
发明人： Pavel Komilovich , James Stasiak
IPC分类号： H01L21/31 , H01L51/40 , H01L21/82 , H01L21/00
CPC分类号： G11C13/00 , G11C13/0014 , G11C13/0016 , H01L27/285
摘要： This disclosure relates to a doped polymer memory device. In one aspect the doped polymer memory device includes a molecularly doped polymer layer that includes a binder and a dopant. The combination of the binder and the dopant modifies polarizability of the molecularly doped polymer layer in a manner that enhances the retention time of the doped polymer memory device. In another aspect, the doped polymer memory device includes a molecularly doped polymer layer that includes a binder and a dopant. An additional dopant is added to the molecularly doped polymer layer. The additional dopant is selected to modify polarizability of the molecularly doped polymer layer in a manner that enhances the retention time of the doped polymer memory device.
摘要翻译：本公开涉及掺杂聚合物存储器件。在一个方面，掺杂聚合物存储器件包括分子掺杂的聚合物层，其包括粘合剂和掺杂剂。粘合剂和掺杂剂的组合以增加掺杂聚合物存储器件的保留时间的方式改变分子掺杂聚合物层的极化率。在另一方面，掺杂聚合物记忆装置包括分子掺杂的聚合物层，其包括粘合剂和掺杂剂。向分子掺杂的聚合物层中加入另外的掺杂剂。选择附加的掺杂剂以改善掺杂聚合物存储器件的保留时间的方式来改变分子掺杂聚合物层的极化率。

52. 发明授权

US06967350B2 Memory structures 有权
标题翻译：内存结构
公开(公告)号：US06967350B2
公开(公告)日：2005-11-22
申请号：US10116497
申请日：2002-04-02
申请人： Peter J. Frick , Andrew Koll , James Stasiak , Andrew L. Van Brocklin , Lung T. Tran
发明人： Peter J. Frick , Andrew Koll , James Stasiak , Andrew L. Van Brocklin , Lung T. Tran
IPC分类号： H01L27/10 , G11C17/18 , H01L21/8246 , H01L27/105 , H01L29/00
CPC分类号： H01L27/224 , G11C17/18 , H01L27/2418 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/1226
摘要： A memory structure that includes a first electrode, a second electrode, a third electrode, a control element of a predetermined device type disposed between the first electrode and the second electrode, and a memory storage element of the predetermined device type disposed between the second electrode and the third electrode. The memory storage element has a cross-sectional area that is less than a cross-sectional area of the control element.
摘要翻译：一种存储器结构，包括第一电极，第二电极，第三电极，设置在第一电极和第二电极之间的预定器件类型的控制元件，以及设置在第二电极之间的预定器件类型的存储器元件和第三电极。存储器存储元件具有小于控制元件的横截面面积的横截面积。

53. 发明授权

US06762094B2 Nanometer-scale semiconductor devices and method of making 有权
标题翻译：纳米级半导体器件及其制造方法
公开(公告)号：US06762094B2
公开(公告)日：2004-07-13
申请号：US10256984
申请日：2002-09-27
申请人： James Stasiak , Jennifer Wu , David E Hackleman
发明人： James Stasiak , Jennifer Wu , David E Hackleman
IPC分类号： H05K336
CPC分类号： H01L29/861 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/3086 , H01L21/32139 , H01L21/8222 , H01L27/0766 , H01L27/082 , H01L27/1021 , H01L29/04 , H01L29/0657 , H01L29/0665 , H01L29/0673 , H01L29/0684 , H01L29/66272 , H01L29/732 , Y10S438/961 , Y10S438/962 , Y10S977/887 , Y10T29/49126 , Y10T29/49128
摘要： A semiconductor device including a substrate having a dopant of a first polarity, a first semiconducting structure including a dopant of a second polarity disposed over the substrate, and having substantially planar top and side surfaces. The semiconductor device includes a first junction, formed between the first semiconducting structure and the substrate, having an area wherein at least one lateral dimension is less than about 75 nanometers.
摘要翻译：一种半导体器件，包括具有第一极性的掺杂剂的衬底，第一半导体结构，其包括设置在衬底上的第二极性的掺杂剂，并且具有基本平坦的顶表面和侧表面。半导体器件包括形成在第一半导体结构和衬底之间的第一结，其具有至少一个横向尺寸小于约75纳米的区域。

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