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51. 发明授权

US06946349B1 Method for integrating a SONOS gate oxide transistor into a logic/analog integrated circuit having several gate oxide thicknesses 有权
标题翻译：将SONOS栅极氧化物晶体管集成到具有多个栅极氧化物厚度的逻辑/模拟集成电路中的方法
公开(公告)号：US06946349B1
公开(公告)日：2005-09-20
申请号：US10914563
申请日：2004-08-09
申请人： Jae Gon Lee , Hwa Weng Koh , Elgin Quek , Dong Kyun Sohn
发明人： Jae Gon Lee , Hwa Weng Koh , Elgin Quek , Dong Kyun Sohn
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/8246 , H01L27/105
CPC分类号： H01L27/105 , H01L21/823462 , H01L21/823857 , H01L27/11568 , H01L27/11573 , Y10S438/954 , Y10S438/981
摘要： A method for integrating a SONOS device with an improved top oxide with SiO2 gate oxides of different thickness is described. In a first embodiment during ISSG oxidation to form the SiO2 gate oxides, a thin sacrificial silicon nitride layer is used over the top oxide of the ONO to minimize loss and to control the top oxide thickness. In a second embodiment the top oxide layer for the SONOS device is formed by depositing an NO stack. During ISSG oxidation to form the SiO2 gate oxides a portion of the Si3N4 in the NO stack is converted to SiO2 to form the top oxide with improved thickness control.
摘要翻译：描述了一种用于将SONOS器件与具有不同厚度的SiO 2栅极氧化物的改进的顶部氧化物集成的方法。在第一实施方案中，在ISSG氧化以形成SiO 2栅极氧化物的情况下，在ONO的顶部氧化物上使用薄的牺牲氮化硅层以使损耗最小化并控制顶部氧化物厚度。在第二实施例中，用于SONOS器件的顶部氧化物层通过沉积NO堆叠形成。在ISSG氧化形成SiO 2栅极氧化物的过程中，将NO堆叠中的一部分Si 3 N 4 N 4转化为SiO < 2以形成具有改进的厚度控制的顶部氧化物。

52. 发明授权

US09268395B2 Hierarchical power management circuit, power management method using the same, and system on chip including the hierarchical power management circuit 有权
标题翻译：分层电源管理电路，使用其电源管理方法，以及片上系统包括分层电源管理电路
公开(公告)号：US09268395B2
公开(公告)日：2016-02-23
申请号：US13233841
申请日：2011-09-15
申请人： Jae Gon Lee , Bong Il Park , Moo Kyung Kang
发明人： Jae Gon Lee , Bong Il Park , Moo Kyung Kang
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , Y02D10/171
摘要： A hierarchical power management circuit includes N power management circuits respectively included in N power domains each including at least one intellectual property (IP), wherein N is a natural number greater than one. The i-th (1
摘要翻译：分级电源管理电路包括分别包括在N个电源域中的N个电源管理电路，每个电源域包括至少一个知识产权（IP），其中N是大于1的自然数。来自N个电力管理电路的第i（1

53. 发明授权

US09166567B2 Data-retained power-gating circuit and devices including the same 有权
标题翻译：数据保持功率门控电路和包括其的器件
公开(公告)号：US09166567B2
公开(公告)日：2015-10-20
申请号：US14210892
申请日：2014-03-14
申请人： Bong Il Park , Andrew B. Kahng , Seok Hyeong Kang , Jae Gon Lee
发明人： Bong Il Park , Andrew B. Kahng , Seok Hyeong Kang , Jae Gon Lee
IPC分类号： G05F1/10 , G05F3/02 , H03K3/012 , H03K3/356
CPC分类号： H03K3/012 , H03K3/356008
摘要： A power-gating circuit and devices including the same are provided. The power-gating circuit includes a flip-flop configured to receive a first power supply voltage and a gated clock signal to operate and a switch circuit connected between a first power supply voltage source configured to supply the first power supply voltage and a second power supply voltage source configured to supply a second power supply voltage. The switch circuit includes a first switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to a clock enable signal and a second switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to the first power supply voltage.
摘要翻译：提供电源门控电路及包括其的装置。电源门控电路包括触发器，其被配置为接收第一电源电压和门控时钟信号以进行操作;以及开关电路，其连接在被配置为提供第一电源电压的第一电源电压源和第二电源电压电压源被配置为提供第二电源电压。开关电路包括第一开关，其被配置为连接在第一电源电压源和第二电源电压源之间并且响应于时钟使能信号而工作;第二开关被配置为连接在第一电源电压源和第二电源电压源，并响应于第一电源电压而工作。

54. 发明授权

US08999863B2 Stress liner for stress engineering 有权
标题翻译：应力工程应力衬
公开(公告)号：US08999863B2
公开(公告)日：2015-04-07
申请号：US12133375
申请日：2008-06-05
申请人： Jae Gon Lee , Jingze Tian , Shyue Seng Tan , Luona Goh , Wei Lu , Elgin Quek
发明人： Jae Gon Lee , Jingze Tian , Shyue Seng Tan , Luona Goh , Wei Lu , Elgin Quek
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/78 , H01L29/66
CPC分类号： H01L21/823807 , H01L29/665 , H01L29/7843
摘要： A stress liner having first and second stress type is provided over a first type and a second type transistor to improve reliability and performance without incurring area penalties or layout deficiencies.
摘要翻译：具有第一和第二应力类型的应力衬垫设置在第一类型和第二类型晶体管上，以提高可靠性和性能，而不会引起区域损失或布局缺陷。

55. 发明授权

US08750037B2 Non-volatile memory utilizing impact ionization and tunnelling and method of manufacturing thereof 有权
标题翻译：利用冲击电离和隧穿的非易失性存储器及其制造方法
公开(公告)号：US08750037B2
公开(公告)日：2014-06-10
申请号：US12456440
申请日：2009-06-16
申请人： Eng Huat Toh , Chung Foong Tan , Shyue Seng Tan , Jae Gon Lee , Elgin Quek
发明人： Eng Huat Toh , Chung Foong Tan , Shyue Seng Tan , Jae Gon Lee , Elgin Quek
IPC分类号： G11C16/04
CPC分类号： H01L29/7885 , G11C16/0408 , H01L29/42336 , H01L29/66825
摘要： A non-volatile memory device (and method of manufacture) is disclosed and structured to enable a write operation using an ionization impact process in a first portion of the device and a read operation using a tunneling process in a second portion of the device. The non-volatile memory device (1) increases hot carrier injection efficiency, (2) decreases power consumption, and (3) enables voltage and device scaling in the non-volatile memory devices.
摘要翻译：公开并构造了非易失性存储器件（和制造方法），以使得能够在器件的第一部分中使用电离冲击处理的写入操作以及在器件的第二部分中使用隧道工艺的读取操作。非易失性存储器件（1）增加了热载流子注入效率，（2）降低功耗，（3）使非易失性存储器件中的电压和器件缩放。

56. 发明授权

US08633081B2 Modifying growth rate of a device layer 有权
标题翻译：修改设备层的增长速度
公开(公告)号：US08633081B2
公开(公告)日：2014-01-21
申请号：US12980376
申请日：2010-12-29
申请人： Chunshan Yin , Palanivel Balasubramaniam , Jae Gon Lee , Elgin Quek
发明人： Chunshan Yin , Palanivel Balasubramaniam , Jae Gon Lee , Elgin Quek
IPC分类号： H01L21/336
CPC分类号： H01L21/02238 , H01L21/02299 , H01L21/2822 , H01L21/76232
摘要： A device includes a substrate with a device region on which a transistor is formed. The device region includes active edge regions and an active center region which have different oxidation growth rates. A growth rate modifier (GRM) comprising dopants which modifies oxidation growth rate is employed to produce a gate oxide layer which has a uniform thickness. The GRM may enhance or retard the oxidation growth, depending on the type of dopants used. Fluorine dopants enhance oxidation growth rate while nitrogen dopants retard oxidation growth rate.
摘要翻译：一种器件包括具有其上形成有晶体管的器件区域的衬底。器件区域包括有效边缘区域和具有不同氧化生长速率的活性中心区域。使用包含修饰氧化生长速率的掺杂剂的生长速率调节剂（GRM）来制造具有均匀厚度的栅极氧化物层。取决于所使用的掺杂剂的类型，GRM可以增强或延缓氧化生长。氟掺杂剂增强氧化生长速率，而氮掺杂剂延缓氧化生长速率。

57. 发明授权

US08470700B2 Semiconductor device with reduced contact resistance and method of manufacturing thereof 有权
公开(公告)号：US08470700B2
公开(公告)日：2013-06-25
申请号：US12804487
申请日：2010-07-22
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Shiang Yang Ong , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Shiang Yang Ong , Elgin Quek
IPC分类号： H01L21/26
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/28556 , H01L21/324 , H01L29/0847 , H01L29/41725 , H01L29/66575
摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.

58. 发明申请

US20120228705A1 LDMOS WITH IMPROVED BREAKDOWN VOLTAGE 有权
标题翻译： LDMOS具有改进的断电电压
公开(公告)号：US20120228705A1
公开(公告)日：2012-09-13
申请号：US13046332
申请日：2011-03-11
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/42364 , H01L29/42368 , H01L29/42372 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66681
摘要： An LDMOS is formed with a second gate stack over the n− drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, the first and second gate stacks sharing a common gate electrode, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack with a first high-k dielectric and the second gate stack with a second high-k dielectric, and forming the first and second gate stacks with asymmetric dielectrics.
摘要翻译： LDMOS在n漂移区上形成有第二栅极堆叠，其具有与栅极堆叠相同的公共栅电极，并且具有比栅极堆叠更高的功函数。实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二栅极叠层，第二阱，第一和第二栅极堆叠共享公共栅极电极，并且调谐第一和第二栅极堆叠的功函数以获得用于第二栅极堆叠的较高功函数。其他实施例包括用第一高k电介质形成第一栅极堆叠，以及用第二高k电介质形成第二栅极堆叠，以及用不对称电介质形成第一和第二栅极堆叠。

59. 发明申请

US20120228695A1 LDMOS WITH IMPROVED BREAKDOWN VOLTAGE 有权
标题翻译： LDMOS具有改进的断电电压
公开(公告)号：US20120228695A1
公开(公告)日：2012-09-13
申请号：US13046313
申请日：2011-03-11
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/402 , H01L29/42368 , H01L29/495 , H01L29/4983 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66681
摘要： An LDMOS is formed with a field plate over the n− drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.
摘要翻译： LDMOS在n-漂移区上形成有与栅叠层共面的场板，并且具有比栅叠层更高的功函数。实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二共面栅叠层，分别调整第一和第二栅极堆叠的功函数，以获得第二栅极堆叠的较高功函数。其他实施例包括在栅极氧化物层上形成高k金属栅极的第一栅极堆叠和场板的第二栅极堆叠，在公共栅极氧化物上形成具有不同栅电极材料的第一和第二栅极堆叠，以及形成栅极堆叠彼此分离并具有不同的栅极电介质材料。

60. 发明申请

US20120119281A1 INTEGRATED CIRCUIT SYSTEM WITH BANDGAP MATERIAL AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：具有带状材料的集成电路系统及其制造方法
公开(公告)号：US20120119281A1
公开(公告)日：2012-05-17
申请号：US12947530
申请日：2010-11-16
申请人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Chunshan Yin , Lakshmi Bera
发明人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Chunshan Yin , Lakshmi Bera
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/42324 , H01L29/42328 , H01L29/66825
摘要： A method of manufacturing an integrated circuit system includes: providing a substrate having a channel region; forming a gate stack over a portion of the channel region with the gate stack having a floating gate for storing an electrical charge; forming a source recess in the substrate adjacent to the gate stack; and forming a source by layering a first bandgap material in the source recess.
摘要翻译：一种制造集成电路系统的方法包括：提供具有沟道区的衬底; 在所述沟道区的一部分上形成栅极堆叠，所述栅极堆叠具有用于存储电荷的浮动栅极; 在所述衬底中邻近所述栅极堆叠形成源极凹槽; 以及通过在源凹槽中层叠第一带隙材料来形成源。

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