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    • 52. 发明授权
    • Transmission system via communications protected by an error management
code
    • 通过通过受错误管理代码保护的通信的传输系统
    • US5745509A
    • 1998-04-28
    • US559963
    • 1995-11-17
    • Philippe Marchand
    • Philippe Marchand
    • G11B20/18H03M13/13H04L1/00H03M13/12
    • H04L1/0057G11B20/1809H03M13/13H04L1/0045
    • A data transmission system wherein data to be transmitted is supplied to an encoding device (5) which comprises a data analysis circuit (35) for producing a parity code and an output circuit (32) for assigning the parity code to the input data so as to convert it into protected data for transmission. The data analysis circuit includes: (i) a serial-to-parallel converter (30) for converting the input data into "n" parallel data streams, the bits in each stream being at instants which are multiples of n.times.T, where T is the bit period of the input data; (ii) "n" cascade combinations of delay elements, each cascade delaying one of the "n" parallel-converted data streams by time periods which are multiples of n.times.T, each cascade having tapping points following certain ones of the delay elements therein; and (iii) combining circuits (GR1, GR2, OE) having inputs connected to tapping points of each of the cascade combinations and which derive the parity code.
    • 一种数据传输系统,其中要发送的数据被提供给包括用于产生奇偶码的数据分析电路(35)和用于将奇偶校验码分配给输入数据的输出电路(32)的编码装置(5),以便 将其转换为受保护的数据进行传输。 数据分析电路包括:(i)用于将输入数据转换为“n”个并行数据流的串行到并行转换器(30),每个流中的比特在时刻是nxT的倍数,其中T是 输入数据的位周期; (ii)延迟元件的“n”个级联组合,每个级联延迟“n”个并行转换的数据流中的一个通过n×T倍数的时间间隔,每个级联具有跟随其中某些延迟元件的分接点; 和(iii)具有连接到每个级联组合的分接点的输入并导出奇偶校验码的电路(GR1,GR2,OE)。