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51. 发明申请

US20150177811A1 POWER MANAGEMENT FOR IN-MEMORY COMPUTER SYSTEMS 有权
标题翻译：内存计算机系统的电源管理
公开(公告)号：US20150177811A1
公开(公告)日：2015-06-25
申请号：US14133861
申请日：2013-12-19
申请人： International Business Machines Corporation
发明人： Pradip Bose , Alper Buyuktosunoglu , Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair , Augusto J. Vega
IPC分类号： G06F1/32
CPC分类号： G06F1/329 , G06F1/3243 , G06F1/3275 , G06F1/3287 , Y02D10/14 , Y02D10/152 , Y02D10/171 , Y02D10/24
摘要： According to one embodiment, a method for power management of a compute node including at least two power-consuming components is provided. A power capping control system compares power consumption level of the compute node to a power cap. Based on determining that the power consumption level is greater than the power cap, actions are performed including: reducing power provided to a first power-consuming component based on determining that it has an activity level below a first threshold and that power can be reduced to the first power-consuming component. Power provided to a second power-consuming component is reduced based on determining that it has an activity level below a second threshold and that power can be reduced to the second power-consuming component. Power reduction is forced in the compute node based on determining that power cannot be reduced in either of the first or second power-consuming component.
摘要翻译：根据一个实施例，提供了一种用于包括至少两个功耗组件的计算节点的功率管理的方法。功率上限控制系统将计算节点的功耗级别与功率上限进行比较。基于确定功耗水平大于功率上限，执行动作，包括：基于确定其具有低于第一阈值的活动水平并且该功率可以减小到第一功耗组件来提供的功率第一个耗电量的组件。基于确定其具有低于第二阈值的活动水平并且该功率可以减小到第二功耗组件，提供给第二功耗组件的功率被减小。基于确定在第一或第二功耗组件中的任何一个中不能降低功率，在计算节点中强制降低功率。

52. 发明授权

US08990620B2 Exposed-pipeline processing element with rollback 有权
标题翻译：具有回滚的暴露流水线处理元素
公开(公告)号：US08990620B2
公开(公告)日：2015-03-24
申请号：US13677746
申请日：2012-11-15
申请人： International Business Machines Corporation
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
IPC分类号： G06F11/14
CPC分类号： G06F11/14 , G06F9/30036 , G06F9/30065 , G06F9/30116 , G06F9/3013 , G06F9/3863 , G06F9/3877 , G06F9/3887 , G06F11/1405 , G06F12/10 , Y02D10/13
摘要： An aspect includes providing rollback support in an exposed-pipeline processing element. A system includes the exposed-pipeline processing element with rollback support logic. The rollback support logic is configured to detect an error associated with execution of an instruction in the exposed-pipeline processing element. The rollback support logic determines whether the exposed-pipeline processing element supports replay of the instruction for a predetermined number of cycles. Based on determining that the exposed-pipeline processing element supports replay of the instruction, a rollback action is performed in the exposed-pipeline processing element to attempt recovery from the error.
摘要翻译：一个方面包括在暴露流水线处理元件中提供回滚支持。系统包括具有回滚支持逻辑的暴露流水线处理元件。回滚支持逻辑被配置为检测与暴露流水线处理元件中的指令的执行相关联的错误。回滚支持逻辑确定暴露流水线处理元件是否支持指令预定次数循环的重放。基于确定暴露流水线处理元件支持指令的重放，在暴露流水线处理元件中执行回滚动作以尝试从错误中恢复。

53. 发明申请

US20140136858A1 POWER-CONSTRAINED COMPILER CODE GENERATION AND SCHEDULING OF WORK IN A HETEROGENEOUS PROCESSING SYSTEM 有权
标题翻译：功率约束编译器代码生成和调度在异构处理系统中的工作
公开(公告)号：US20140136858A1
公开(公告)日：2014-05-15
申请号：US13680295
申请日：2012-11-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Hans M. Jacobson , Ravi Nair , John K.P. O'Brien , Zehra N. Sura
IPC分类号： G06F9/50 , G06F9/46 , G06F1/26
CPC分类号： G06F9/5094 , G06F1/329 , G06F8/41 , G06F9/46 , G06F9/4893 , Y02D10/24
摘要： An active memory system includes a computer and an active memory device including layers of memory forming a three-dimensional memory device and individual columns of chips forming vaults in communication with a processing element and logic. The processing element is configured to communicate to the chips and other processing elements. The active memory system also includes a compiler configured to implement a method. The method includes dividing a power budget for the active memory device into a discrete number of power tokens, each of the power tokens having an equal value of units of power. The method also includes determining a power requirement for executing a code segment on the processing element of the active memory device based on characteristics of the processing element and the code segment. The method further includes allocating, to the processing element at runtime, one or more power tokens to satisfy the power requirement.
摘要翻译：有源存储器系统包括计算机和主动存储器件，其包括形成三维存储器件的存储器层和形成与处理元件和逻辑通信的保险库的各个芯片列。处理元件被配置为与芯片和其它处理元件通信。活动存储器系统还包括被配置为实现方法的编译器。该方法包括将有源存储器件的功率预算分成离散数量的功率标记，每个功率令牌具有相等的功率单位值。该方法还包括基于处理元件和代码段的特性来确定在有源存储器件的处理元件上执行代码段的功率需求。该方法还包括在运行时向处理元件分配一个或多个功率令牌以满足功率需求。

54. 发明申请

US20140130051A1 MAIN PROCESSOR SUPPORT OF TASKS PERFORMED IN MEMORY 有权
标题翻译：主要处理器支持在记忆体中执行的任务
公开(公告)号：US20140130051A1
公开(公告)日：2014-05-08
申请号：US13684657
申请日：2012-11-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
IPC分类号： G06F9/46
CPC分类号： G06F9/46 , G06F9/3877 , G06F9/5044 , G06F2209/509 , Y02D10/22
摘要： According to one embodiment of the present invention, a computer system for executing a task includes a main processor, a processing element and memory. The computer system is configured to perform a method including receiving, at the processing element, the task from the main processor, performing, by the processing element, an instruction specified by the task, determining, by the processing element, that a function is to be executed on the main processor, the function being part of the task, sending, by the processing element, a request to the main processor for execution, the request including execution of the function and receiving, at the processing element, an indication that the main processor has completed execution of the function specified by the request.
摘要翻译：根据本发明的一个实施例，用于执行任务的计算机系统包括主处理器，处理元件和存储器。计算机系统被配置为执行一种方法，包括在处理元件处接收来自主处理器的任务，由处理元件执行由该任务指定的指令，由处理元件确定功能是在所述主处理器上执行所述功能是所述任务的一部分，由所述处理元件向所述主处理器发送请求以执行所述请求，所述请求包括所述功能的执行，并且在所述处理元件处接收所述处理元件的指示，主处理器已完成执行请求指定的功能。

55. 发明申请

US20210336128A1 MRAM STRUCTURE WITH TERNARY WEIGHT STORAGE 有权
公开(公告)号：US20210336128A1
公开(公告)日：2021-10-28
申请号：US16857928
申请日：2020-04-24
申请人： International Business Machines Corporation
发明人： Alexander Reznicek , Bahman Hekmatshoartabari , Michael Rizzolo , Ravi Nair
IPC分类号： H01L43/08 , H01L43/02 , H01L43/12 , H01L27/22 , G11C11/16
摘要： A memory device is provided that includes at least one MTJ pillar which can have a ternary program state as compared to a binary program state in a conventional device. The MTJ pillar contains a lower MTJ structure that includes at least a first magnetic reference material, a first tunnel barrier and a first magnetic free layer material, and an upper MTJ structure that includes at least a second magnetic reference material, a second tunnel barrier and a second magnetic free layer material; the upper MTJ structure is stacked atop the lower MTJ structure. The first and second magnetic free layer materials have different designs and/or compositions resulting in different switching voltages.

56. 发明申请

US20210166116A1 INITIALIZATION OF MEMORY NETWORKS 有权
公开(公告)号：US20210166116A1
公开(公告)日：2021-06-03
申请号：US16699814
申请日：2019-12-02
申请人： International Business Machines Corporation
发明人： Bahman Hekmatshoartabari , Ravi Nair
IPC分类号： G06N3/08 , G06N3/04
摘要： A memory network can be constructed with at least memory write weightings, memory read weightings and at least one read vector, the memory write weightings parameterizing memory write operations of a neural network to the memory matrix, the memory read weightings parameterizing memory read operations of the neural network from the memory matrix. At least one of the write weightings, the read weightings, or elements of the at least one read vector, can be initialized to have sparsity and/or low discrepancy sampling pattern. The memory network can be trained to perform a task.

57. 发明授权

US11016908B2 Distributed directory of named data elements in coordination namespace 有权
公开(公告)号：US11016908B2
公开(公告)日：2021-05-25
申请号：US16216863
申请日：2018-12-11
申请人： International Business Machines Corporation
发明人： Charles R. Johns , James A. Kahle , James C. Sexton , Ravi Nair
IPC分类号： G06F12/10 , G06F12/1072 , G06F12/1009 , G06F12/109 , G06F12/06
摘要： An approach is described that provides a distributed directory structure within a storage of an information handling system (a local node). A request is received with the request corresponding to a shared virtual address. The shared virtual address that is shared amongst a number of nodes that includes the local node and some remote nodes. A Global Address Space Directory (GASD) is retrieved that corresponds to a global virtual address space. The GASD is stored in a Coordination Namespace that is stored in a memory that is distributed amongst the nodes. A mapping that is included in the GASD is used to determine the node where the shared virtual address currently resides. The shared virtual address is then accessed from the node where it currently resides.

58. 发明授权

US10831537B2 Dynamic update of the number of architected registers assigned to software threads using spill counts 有权
公开(公告)号：US10831537B2
公开(公告)日：2020-11-10
申请号：US15435803
申请日：2017-02-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Harold W. Cain, III , Hubertus Franke , Charles R. Johns , Hung Q. Le , Ravi Nair
IPC分类号： G06F9/50 , G06F9/30 , G06F9/38 , G06F9/455
摘要： A computer system includes a processor, main memory, and controller. The processor includes a plurality of hardware threads configured to execute a plurality of software threads. The main memory includes a first register table configured to contain a current set of architected registers for the currently running software threads. The controller is configured to change a first number of the architected registers assigned to a given one of the software threads to a second number of architected registers when a result of monitoring current usage of the registers by the software threads indicates that the change will improve performance of the computer system. The processor includes a second register table configured to contain a subset of the architected registers and a mapping table for each software thread indicating whether the architected registers referenced by the corresponding software thread are located in the first register table or the second register table.

59. 发明授权

US10049061B2 Active memory device gather, scatter, and filter 有权
公开(公告)号：US10049061B2
公开(公告)日：2018-08-14
申请号：US13674520
申请日：2012-11-12
申请人： International Business Machines Corporation
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , James A. Kahle , Jaime H. Moreno , Ravi Nair
IPC分类号： G06F12/10 , G06F13/28
摘要： Embodiments relate to loading and storing of data. An aspect includes a method for transferring data in an active memory device that includes memory and a processing element. An instruction is fetched and decoded for execution by the processing element. Based on determining that the instruction is a gather instruction, the processing element determines a plurality of source addresses in the memory from which to gather data elements and a destination address in the memory. One or more gathered data elements are transferred from the source addresses to contiguous locations in the memory starting at the destination address. Based on determining that the instruction is a scatter instruction, a source address in the memory from which to read data elements at contiguous locations and one or more destination addresses in the memory to store the data elements at non-contiguous locations are determined, and the data elements are transferred.

60. 发明授权

US09870340B2 Multithreading in vector processors 有权
公开(公告)号：US09870340B2
公开(公告)日：2018-01-16
申请号：US14672568
申请日：2015-03-30
申请人： International Business Machines Corporation
发明人： Constantinos Evangelinos , Changhoan Kim , Ravi Nair
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F15/80 , G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F15/8076 , G06F9/30036 , G06F9/30189 , G06F9/321 , G06F9/3851 , G06F15/8053 , G06F15/8084
摘要： In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.

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