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51. 发明申请

US20160358820A1 VIA FORMATION USING SIDEWALL IMAGE TRANFER PROCESS TO DEFINE LATERAL DIMENSION 审中-公开
标题翻译：通过使用边框图像平移过程确定横向尺寸的形式
公开(公告)号：US20160358820A1
公开(公告)日：2016-12-08
申请号：US15239178
申请日：2016-08-17
申请人： International Business Machines Corporation , GLOBALFOUNDRIES, INC. , STMicroelectronics, Inc.
发明人： Shyng-Tsong Chen , Cheng Chi , Chi-Chun Liu , Sylvie M. Mignot , Yann A. Mignot , Hosadurga K. Shobha , Terry A. Spooner , Wenhui Wang , Yongan Xu
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532
CPC分类号： H01L21/76897 , H01L21/76802 , H01L21/76811 , H01L21/76816 , H01L21/76829 , H01L21/76834 , H01L21/76885 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L23/53238 , H01L23/53266 , H01L23/5329
摘要： A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.
摘要翻译：提供了形成通孔到半导体器件的下层的方法。该方法可以包括使用侧壁图像转移过程在下层上形成柱。介电层形成在柱和下层之上; 以及图案化在所述电介质层上的通孔掩模，所述通孔掩模具有至少部分地与所述支柱重叠的掩模开口。使用通孔掩模在电介质层中蚀刻通孔开口，掩模开口在第一方向上限定通孔开口的第一横向尺寸，并且柱沿不同于第一方向的第二方向限定通孔开口的第二横向尺寸方向。通孔开口填充有导体以形成通孔。还提供了半导体器件和通孔结构。

52. 发明申请

US20160320701A1 METHOD TO HARDEN PHOTORESIST FOR DIRECTED SELF-ASSEMBLY PROCESSES 有权
标题翻译：用于指导自组装过程的硬质合金的方法
公开(公告)号：US20160320701A1
公开(公告)日：2016-11-03
申请号：US14697669
申请日：2015-04-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Joy Cheng , Matthew E. Colburn , Chi-Chun Liu
IPC分类号： G03F7/039 , H01L21/308 , G03F7/40
CPC分类号： G03F7/039 , G03F7/0002 , G03F7/40 , G03F7/405 , H01L21/0273 , H01L21/0337 , H01L21/3086
摘要： A patterned photoresist is provided atop a substrate. A hardening agent is applied to the patterned photoresist to provide a polymeric coated patterned photoresist. The polymeric coated patterned photoresist is baked to provide a hardened photoresist, and subsequent the baking step, the polymeric coating is removed from the hardened photoresist by rinsing. The hardened photoresist can be removed anytime during the patterning of the substrate by an aqueous resist developer.
摘要翻译：图案化的光致抗蚀剂被提供在衬底顶部。将硬化剂施加到图案化的光致抗蚀剂以提供聚合物涂覆的图案化的光致抗蚀剂。将聚合物涂覆的图案化光刻胶烘烤以提供硬化的光致抗蚀剂，随后在烘烤步骤中，通过冲洗将聚合物涂层从硬化的光致抗蚀剂中除去。在通过含水抗蚀剂显影剂对基材图案化期间，可以随时去除硬化的光致抗蚀剂。

53. 发明授权

US09123658B2 Grapho-epitaxy DSA process with dimension control of template pattern 有权
标题翻译： Grapho外延DSA过程与模板图案的尺寸控制
公开(公告)号：US09123658B2
公开(公告)日：2015-09-01
申请号：US14327968
申请日：2014-07-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jassem A. Abdallah , Matthew E. Colburn , Steven J. Holmes , Chi-Chun Liu
IPC分类号： H01L21/311 , H01L21/308 , H01L21/3065
CPC分类号： H01L21/3086 , G03F7/0002 , H01L21/0337 , H01L21/3065 , H01L21/3081
摘要： A method for defining a template for directed self-assembly (DSA) materials includes patterning a resist on a stack including an ARC and a mask formed over a hydrophilic layer. A pattern is formed by etching the ARC and the mask to form template lines which are trimmed to less than a minimum feature size (L). Hydrophobic spacers are formed on the template lines and include a fractional width of L. A neutral brush layer is grafted to the hydrophilic layer. A DSA material is deposited between the spacers and annealed to form material domains in a form of alternating lines of a first and a second material wherein the first material in contact with the spacers includes a width less than a width of the lines. A metal is added to the domains forming an etch resistant second material. The first material and the spacers are removed to form a DSA template pattern.
摘要翻译：用于定义用于定向自组装（DSA）材料的模板的方法包括在包括ARC和在亲水层上形成的掩模的堆叠上构图抗蚀剂。通过蚀刻ARC和掩模形成图案，以形成修剪成小于最小特征尺寸（L）的模板线。在模板线上形成疏水间隔物，并包括L的分数宽度。将中性刷层接枝到亲水层。 DSA材料沉积在间隔物之间并退火以形成第一和第二材料的交替线形式的材料区域，其中与间隔物接触的第一材料包括小于线宽度的宽度。向形成耐蚀刻第二材料的区域中加入金属。去除第一材料和间隔物以形成DSA模板图案。

54. 发明授权

US11329001B2 Embedded chip identification formed by directed self-assembly 有权
公开(公告)号：US11329001B2
公开(公告)日：2022-05-10
申请号：US16413208
申请日：2019-05-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kangguo Cheng , Chi-Chun Liu
IPC分类号： H01L23/544 , H01L21/02 , H01L21/3205 , H01L21/311
摘要： A security region is provided. The security region includes a plurality of parallel conductive lines on a substrate, wherein each of the parallel conductive lines has a width and includes a bend, and wherein at least a portion of the plurality of parallel conductive lines is discontinuous, and an electrically insulating material between each adjacent pair of parallel conductive lines.

55. 发明授权

US11195995B2 Back-end-of-line compatible processing for forming an array of pillars 有权
公开(公告)号：US11195995B2
公开(公告)日：2021-12-07
申请号：US16735020
申请日：2020-01-06
申请人： International Business Machines Corporation
发明人： Chi-Chun Liu , Yann Mignot , Ekmini Anuja De Silva , Nelson Felix , John Christopher Arnold
IPC分类号： H01L43/12 , H01L43/02 , H01L27/22
摘要： A method of forming a semiconductor structure includes forming a memorization layer over a substrate, forming a first self-aligned double patterning (SADP) stack including a first organic planarization layer (OPL), masking layer, set of mandrels, and set of spacers, and forming a patterned memorization layer by transferring a first pattern of the first set of spacers to the memorization layer. The method also includes forming a second SADP stack comprising a second OPL, masking layer, set of mandrels, and set of spacers, and forming an array of pillars by transferring a second pattern of the second set of spacers to the patterned memorization layer. The first and second OPL and the first and second sets of mandrels are a spin-on coated OPL material, and the memorization layer and first and second masking layers are a material configured for removal selective to the spin-on coated OPL material.

56. 发明授权

US11139242B2 Via-to-metal tip connections in multi-layer chips 有权
公开(公告)号：US11139242B2
公开(公告)日：2021-10-05
申请号：US16397250
申请日：2019-04-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Ruilong Xie , Chih-Chao Yang , Chi-Chun Liu , Kangguo Cheng
IPC分类号： H01L23/528 , H01L23/522 , H01L21/02 , H01L21/3105 , H01L21/768 , H01L21/311
摘要： Integrated chips and methods for forming vias in the same include forming a multi-layer isolation structure on an underlying layer. The multi-layer isolation structure includes a first isolation layer around a second isolation layer. Conductive material is formed around the multi-layer isolation structure. The first isolation layer is etched back to expose at least a portion of a sidewall of the conductive material. A conductive via is formed to contact a top surface and the exposed portion of the sidewall of the conductive material.

57. 发明申请

US20210151377A1 SELF-ALIGNED TOP VIA 有权
公开(公告)号：US20210151377A1
公开(公告)日：2021-05-20
申请号：US16685192
申请日：2019-11-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Chi-Chun Liu , John C. Arnold , Dominik Metzler , Nelson Felix , Ashim Dutta
IPC分类号： H01L23/538 , H01L21/768 , H01L21/3213 , H01L21/033 , H01L21/762
摘要： A method of forming a self-aligned top via is provided. The method includes forming a metallization layer on a substrate, and forming a hardmask layer on the metallization layer. The method further includes forming a pair of adjacent parallel mandrels on the hardmask layer with sidewall spacers on opposite sides of each mandrel. The method further includes forming a planarization layer on the exposed portions of the hardmask layer, mandrels, and sidewall spacers, and forming an opening in the planarization layer aligned between the adjacent parallel mandrels. The method further includes forming a spacer layer in the opening, and removing portions of the spacer layer to form a pair of spacer plugs between sections of the sidewall spacers.

58. 发明授权

US11004737B2 Field effect device with reduced capacitance and resistance in source/drain contacts at reduced gate pitch 有权
公开(公告)号：US11004737B2
公开(公告)日：2021-05-11
申请号：US16433721
申请日：2019-06-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kangguo Cheng , Chi-Chun Liu , Peng Xu
IPC分类号： H01L23/535 , H01L21/768 , H01L23/532 , H01L29/417
摘要： A method of forming source/drain contacts with reduced capacitance and resistance, including, forming a source/drain and a channel region on an active region of a substrate, forming a dielectric fill on the source/drain, forming a trench in the dielectric fill, forming a source/drain contact in the trench, forming an inner contact mask section on a portion of an exposed top surface of the source/drain contact, removing a portion of the source/drain contact to form a channel between a sidewall of the dielectric fill and a remaining portion of the source/drain contact, where a surface area of the remaining portion of the source/drain contact is greater than the surface area of the exposed top surface of the source/drain contact, and forming a source/drain electrode fill on the remaining portion of the source/drain contact.

59. 发明申请

US20200343342A1 NANOSHEET DEVICES WITH IMPROVED ELECTROSTATIC INTEGRITY 审中-公开
公开(公告)号：US20200343342A1
公开(公告)日：2020-10-29
申请号：US16397541
申请日：2019-04-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Ruilong Xie , Chi-Chun Liu , Cheng Chi , Kangguo Cheng
IPC分类号： H01L29/10 , H01L21/02 , H01L29/16 , H01L29/66 , H01L29/78 , H01L29/06 , H01L21/308
摘要： Semiconductor devices and methods of forming the same include forming spacers on respective sidewalls above a stack of alternating channel layers and sacrificial layers, leaving an opening between the spacers. The stack is etched, between the spacers, to form a central opening in the stack that separates the channel layers into respective pairs of channel structures. The sacrificial material is etched away to expose top and bottom surfaces of the channel structures. A gate stack is formed on, between, and around the channel structures, including in the central opening between pairs of channel structures.

60. 发明申请

US20200286992A1 SOURCE/DRAIN EXTENSION REGIONS AND AIR SPACERS FOR NANOSHEET FIELD-EFFECT TRANSISTOR STRUCTURES 审中-公开
公开(公告)号：US20200286992A1
公开(公告)日：2020-09-10
申请号：US16291443
申请日：2019-03-04
申请人： International Business Machines Corporation
发明人： Yi Song , Zhenxing Bi , Kangguo Cheng , Chi-Chun Liu
IPC分类号： H01L29/08 , H01L29/06 , H01L21/02 , H01L21/8234 , H01L29/66 , H01L21/324 , H01L21/764 , H01L27/088 , H01L29/10
摘要： A method of forming a semiconductor structure includes forming a nanosheet stack over a substrate, the nanosheet stack including alternating sacrificial and channel layers, the channel layers providing nanosheet channels for nanosheet field-effect transistors. The method also includes forming vertical fins in the nanosheet stack and a portion of the substrate, and forming indents in sidewalls of the sacrificial layers at sidewalls of the vertical fins. The method further includes forming nanosheet extension regions in portions of the channel layers which extend from the indented sidewalls of the sacrificial layers to the sidewalls of the vertical fins, the nanosheet extension regions increasing in thickness from the indented sidewalls of the sacrificial layers to the sidewalls of the vertical fins. The method further includes forming inner spacers using a conformal deposition process that forms air gaps in spaces between the nanosheet extension regions and the indented sidewalls of the sacrificial layers.

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