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51. 发明授权

US09395490B2 Variable buried oxide thickness for a waveguide 有权
标题翻译：波导的可变埋氧层厚度
公开(公告)号：US09395490B2
公开(公告)日：2016-07-19
申请号：US14982603
申请日：2015-12-29
申请人： International Business Machines Corporation
发明人： Russell A. Budd , Effendi Leobandung , Ning Li , Jean-Olivier Plouchart , Devendra K. Sadana
IPC分类号： G02B6/43 , G02B6/132 , G02B6/136 , G02B6/12 , G02B6/42 , G02B6/122
CPC分类号： G02B6/132 , G02B6/12004 , G02B6/122 , G02B6/136 , G02B6/42 , G02B6/4214 , G02B6/4246 , G02B6/4295 , G02B6/4296 , G02B6/43 , G02B2006/121 , G02B2006/12121 , G02B2006/12135
摘要： A semiconductor structure is provided in which a plurality of waveguide structures are embedded within a semiconductor handle substrate. Each waveguide structure includes, from bottom to top, a bottom oxide portion, a waveguide core material portion and a top oxide portion. An oxide capping layer is present on topmost surfaces of each waveguide structure and a topmost surface of the semiconductor handle substrate. A plurality of semiconductor devices is located above a topmost surface of the oxide capping layer. The structure has thicker buried oxide regions defined by the combined thicknesses of the top oxide portion and the oxide capping layer located in some areas, while thinner buried oxide regions defined only by the thickness of the oxide capping layer are present in other areas of the structure.
摘要翻译：提供一种半导体结构，其中多个波导结构嵌入在半导体处理衬底内。每个波导结构包括从底部到顶部的底部氧化物部分，波导芯材料部分和顶部氧化物部分。在每个波导结构的最上表面和半导体处理衬底的最上表面上存在氧化物覆盖层。多个半导体器件位于氧化物覆盖层的最上表面之上。该结构具有由位于一些区域中的顶部氧化物部分和氧化物覆盖层的组合厚度限定的较厚的掩埋氧化物区域，而仅由氧化物覆盖层的厚度限定的较薄的掩埋氧化物区域存在于该结构的其它区域中。

52. 发明授权

US09305964B1 Optoelectronic devices with back contact 有权
标题翻译：具有背面接触的光电器件
公开(公告)号：US09305964B1
公开(公告)日：2016-04-05
申请号：US14749067
申请日：2015-06-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Effendi Leobandung , Ning Li , Tak H. Ning , Jean-Olivier Plouchart , Devendra K. Sadana
IPC分类号： H01L21/00 , H01L27/146
CPC分类号： H01L27/14 , H01L25/041 , H01L27/1214 , H01L27/15 , H01L31/02005 , H01L31/022408 , H01L31/18 , H01L33/36 , H01L33/38 , H01L33/62 , H01L2924/0002 , H01L2933/0016 , H01L2933/0066 , H01S5/0206 , H01S5/0421 , H01L2924/00
摘要： A semiconductor structure includes an optoelectronic device located in one region of a substrate. A dielectric material is located adjacent and atop the optoelectronic device. A top contact is located within a region of the dielectric material and contacting a topmost surface of the optoelectronic device. A bottom metal contact is located beneath the optoelectronic device and lining a pair of openings located with other regions of the dielectric material, wherein a portion of the bottom metal contact contacts an entire bottommost surface of the optoelectronic device.
摘要翻译：半导体结构包括位于衬底的一个区域中的光电器件。介电材料位于光电子器件的邻近和顶部。顶部接触件位于电介质材料的区域内并与光电器件的最上表面接触。底部金属触点位于光电子器件的下方并且衬有位于介电材料的其它区域的一对开口，其中底部金属触点的一部分接触光电子器件的整个最底部表面。

53. 发明申请

US20150340765A1 INTEGRATION OF AREA EFFICIENT ANTENNAS FOR PHASED ARRAY OR WAFER SCALE ARRAY ANTENNA APPLICATIONS 有权
标题翻译：用于定时阵列或波长范围阵列天线应用的区域有效天线的集成
公开(公告)号：US20150340765A1
公开(公告)日：2015-11-26
申请号：US14281951
申请日：2014-05-20
申请人： International Business Machines Corporation
发明人： Bing Dang , Duixian Liu , Jean-Olivier Plouchart , Peter Jerome Sorce , Cornelia Kang-I Tsang
IPC分类号： H01Q9/04 , H01Q21/00
CPC分类号： H01Q21/065 , H01L2223/6677 , H01L2224/0401 , H01L2224/0557 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2924/15192 , H01Q1/2208 , H01Q1/2283 , H01Q1/48 , H01Q21/0075
摘要： Package structures are provided for integrally packaging antennas with semiconductor RFIC (radio frequency integrated circuit) chips to form compact integrated radio/wireless communications systems that operate in the millimeter-wave and terahertz frequency ranges. For example, a package structure includes an RFIC chip, and an antenna package bonded to the RFIC chip. The antenna package includes a glass substrate, at least one planar antenna element formed on a first surface of the glass substrate, a ground plane formed on a second surface of the glass substrate, opposite the first surface, and an antenna feed line formed through the glass substrate and connected to the at least one planar antenna element. The antenna package is bonded to a surface of the RFIC chip using a layer of adhesive material.
摘要翻译：提供封装结构，用于将天线与半导体RFIC（射频集成电路）芯片整体封装，以形成在毫米波和太赫兹频率范围内工作的紧凑型集成无线电/无线通信系统。例如，封装结构包括RFIC芯片和结合到RFIC芯片的天线封装。天线封装包括玻璃基板，形成在玻璃基板的第一表面上的至少一个平面天线元件，形成在玻璃基板的与第一表面相对的第二表面上的接地平面和通过玻璃基板并连接到所述至少一个平面天线元件。使用一层粘合剂材料将天线封装结合到RFIC芯片的表面。

54. 发明申请

US20150333051A1 TRANSISTOR STRUCTURE HAVING AN ELECTRICAL CONTACT STRUCTURE WITH MULTIPLE METAL INTERCONNECT LEVELS STAGGERING ONE ANOTHER 有权
标题翻译：具有多个金属互连级别的电气接触结构的晶体管结构分析其他一个
公开(公告)号：US20150333051A1
公开(公告)日：2015-11-19
申请号：US14451493
申请日：2014-08-05
申请人： International Business Machines Corporation
发明人： David R. Greenberg , Jean-Olivier Plouchart , Alberto Valdes-Garcia
IPC分类号： H01L27/02 , H01L23/528 , H01L29/417 , H01L29/423 , H01L27/088
CPC分类号： H01L27/0207 , H01L23/4824 , H01L23/528 , H01L27/088 , H01L29/41758 , H01L29/42376 , H01L29/4238 , H01L29/78 , H01L2924/0002 , H01L2924/14 , H01L2924/30105 , H01L2924/00
摘要： An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width the rectangle on the metal level immediately below. The rectangle on one metal level is shorter in length than and substantially aligned at a first end with the rectangle on the metal level immediately below. Rectangle first ends are substantially aligned. Features of an exemplary FET transistor of this invention are a source and drain terminal electrical contact structure, a multi-level metal ring connecting gate rectangles on both ends, and a wider-than-minimum gate-to-gate spacing. The invention is useful, for example, in an electromigration-compliant, high performance transistor.
摘要翻译：电接触结构沿其长度分布电流。电接触结构包括在n级金属上的多个n个金属矩形。一个金属层上的矩形至少具有宽度的宽度，并且垂直地在宽度上覆盖紧接在下面的金属层上的矩形。一个金属层上的矩形长度短于第一端，并且在紧靠下方的金属层上的矩形基本对齐。矩形的第一端基本对齐。本发明的示例性FET晶体管的特征是源极和漏极端子电接触结构，在两端连接栅极矩形的多级金属环和大于最小栅极至栅极间隔。本发明例如在电迁移兼容的高性能晶体管中是有用的。

55. 发明授权

US09184751B2 Physical unclonable function generation and management 有权
标题翻译：物理不可克隆的功能生成与管理
公开(公告)号：US09184751B2
公开(公告)日：2015-11-10
申请号：US14028880
申请日：2013-09-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Dirk Pfeiffer , Jean-Olivier Plouchart , Peilin Song
IPC分类号： H03K19/003 , H04L9/20
CPC分类号： H03K19/003
摘要： Methods, systems and devices related to authentication of chips using physical physical unclonable functions (PUFs) are disclosed. In accordance one such method, a test voltage is applied to a PUF system including a first subset of PUF elements that are arranged in series and a second subset of PUF elements that are arranged in series, where the first subset of PUF elements is arranged in parallel with respect to the second subset of PUF elements. In addition, the PUF system is measured to obtain at least one differential of states between the first subset of PUF elements and the second subset of PUF elements. Further, the method includes outputting an authentication sequence for the circuit that is based on the one or more differentials of states.
摘要翻译：公开了使用物理不可克隆功能（PUF）的芯片认证相关的方法，系统和设备。根据一种这样的方法，将测试电压施加到包括串联布置的PUF元件的第一子集和串联布置的PUF元件的第二子集的PUF系统，其中PUF元件的第一子集被布置在相对于PUF元件的第二子集平行。此外，测量PUF系统以获得PUF元素的第一子集和PUF元素的第二子集之间的状态的至少一个差异。此外，该方法包括输出基于一个或多个状态差分的电路的认证序列。

56. 发明申请

US20230074376A1 PHASED ARRAY SYSTEM-IN PACKAGE SUPPORTING SPATIO-SPECTRAL DIVISION MULTIPLEXING 有权
公开(公告)号：US20230074376A1
公开(公告)日：2023-03-09
申请号：US17468586
申请日：2021-09-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , FUJIKURA LTD
发明人： Alberto Valdes Garcia , Arun Paidimarri , Bodhisatwa Sadhu , Jean-Olivier Plouchart , Xiaoxiong Gu , Christian Wilhelmus Baks , Yo Yamaguchi , Kiyoshi Kobayashi , Yoshiharu Fujisaku , Ning Guan
IPC分类号： H01Q3/26 , H04B7/06 , H01Q1/24
摘要： A phased array antenna includes an antenna array substrate having a plurality of antenna elements. At least two beamformers are coupled to the plurality of antenna elements. At least two filters support different frequency bands and are respectively coupled to the at least two beamformers. A frequency converter is coupled to the at least two filters, the frequency converter including one intermediate frequency (IF) port and at least two radio frequency (RF) ports. The one IF port of the frequency converter is configured to support the at least two beamformers via the at least two RF ports. A first beamformer of the at least two beamformers is coupled to a first filter of the at least two filters to form a first beam in a direction different than a second beamformer of the first two beamformers coupled to a second filter of the at least two filters.

57. 发明授权

US11587890B2 Tamper-resistant circuit, back-end of the line memory and physical unclonable function for supply chain protection 有权
公开(公告)号：US11587890B2
公开(公告)日：2023-02-21
申请号：US16933549
申请日：2020-07-20
申请人： International Business Machines Corporation
发明人： Jean-Olivier Plouchart , Dirk Pfeiffer , Arvind Kumar , Takashi Ando , Peilin Song
IPC分类号： H01L23/00 , G06F21/78 , H04L9/32
摘要： A tamper-resistant memory is formed by placing a solid-state memory array between metal wiring layers in the upper portion of an integrated circuit (back-end of the line). The metal layers form a mesh that surrounds the memory array to protect it from picosecond imaging circuit analysis, side channel attacks, and delayering with electrical measurement. Interconnections between a memory cell and its measurement circuit are designed to protect each layer below, i.e., an interconnecting metal portion in a particular metal layer is no smaller than the interconnecting metal portion in the next lower layer. The measurement circuits are shrouded by the metal mesh. The substrate, metal layers and memory array are part of a single monolithic structure. In an embodiment adapted for a chip identification protocol, the memory array contains a physical unclonable function identifier that uniquely identifies the tamper-resistant integrated circuit, a symmetric encryption key and a release key.

58. 发明授权

US11231498B1 Concealed object detection 有权
公开(公告)号：US11231498B1
公开(公告)日：2022-01-25
申请号：US16934883
申请日：2020-07-21
申请人： International Business Machines Corporation
发明人： Alberto Valdes Garcia , Jean-Olivier Plouchart , Petar K. Pepeljugoski
IPC分类号： G01S13/88 , G06T7/70 , G06T7/13 , G06T5/50 , H04B7/06 , G06T7/50
摘要： A method for detecting the presence of on-body concealed objects includes receiving a visible-domain camera image for a scene, determining, using the visible-domain camera image, a region of interest where a subject is present, receiving an infrared-domain camera image and a millimeter-wave (mmwave) radar image that each cover the region of interest, determining emissivity information for the region of interest using the infrared-domain camera image, determining reflectivity information for the region of interest using the mmwave radar image and determining a concealed object classification for the subject based on the emissivity information and the reflectivity information. A corresponding system and computer program product for executing the above method are also disclosed herein.

59. 发明授权

US10605985B2 Integration of bonded optoelectronics, photonics waveguide and VLSI SOI 有权
公开(公告)号：US10605985B2
公开(公告)日：2020-03-31
申请号：US15935447
申请日：2018-03-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Russell A. Budd , Effendi Leobandung , Ning Li , Jean-Olivier Plouchart , Devendra K. Sadana
IPC分类号： G02B6/12 , G02B6/122 , G02B6/42 , H01L31/0216 , H01L31/103 , H01L31/18 , G02B6/132
摘要： An optoelectronic device includes an integrated circuit including electronic devices formed on a front side of a semiconductor substrate. A barrier layer is formed on a back side of the semiconductor substrate. A photonics layer is formed on the barrier layer. The photonics layer includes a core for transmission of light and a cladding layer encapsulating the core and including a different index of refraction than the core. The core is configured to couple light generated from a component of the optoelectronic device.

60. 发明授权

US10090340B2 Optoelectronic devices with back contact 有权
公开(公告)号：US10090340B2
公开(公告)日：2018-10-02
申请号：US15406226
申请日：2017-01-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Effendi Leobandung , Ning Li , Tak H. Ning , Jean-Olivier Plouchart , Devendra K. Sadana
IPC分类号： H01L33/00 , H01L21/00 , H01L27/14 , H01L27/15 , H01L33/38 , H01L31/0224 , H01L33/62 , H01S5/02 , H01S5/042 , H01L27/12
摘要： A semiconductor structure includes an optoelectronic device located in one region of a substrate. A dielectric material is located adjacent and atop the optoelectronic device. A top contact is located within a region of the dielectric material and contacting a topmost surface of the optoelectronic device. A bottom metal contact is located beneath the optoelectronic device and lining a pair of openings located with other regions of the dielectric material, wherein a portion of the bottom metal contact contacts an entire bottommost surface of the optoelectronic device.

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