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    • 52. 发明申请
    • Methods of implanting dopant into channel regions
    • 将掺杂剂注入通道区域的方法
    • US20060199340A1
    • 2006-09-07
    • US11406863
    • 2006-04-18
    • Hongmei WangKurt BeigelFred FishburnRongsheng Yang
    • Hongmei WangKurt BeigelFred FishburnRongsheng Yang
    • H01L21/336
    • H01L21/26513H01L21/324H01L21/823412H01L27/0811H01L27/088H01L29/66537H01L29/7833
    • The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
    • 本发明包括同时形成两个晶体管器件的沟道区域植入物的方法,其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。 本发明还涉及形成电容器结构的方法,其中第一电容器电极通过电介质材料与半导体衬底隔开,第二电容器电极包括半导体材料内的导电掺杂扩散区,电容器通道区位置为 在介电材料的下方并与导电掺杂的扩散区相邻。 形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。 当植入掩模就位时,掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。
    • 53. 发明申请
    • Dielectric plug in mosfets to suppress short-channel effects
    • 介质插头在mosfets中抑制短路效应
    • US20060076619A1
    • 2006-04-13
    • US11283015
    • 2005-11-18
    • Hongmei WangZhongze Wang
    • Hongmei WangZhongze Wang
    • H01L29/76
    • H01L29/66628H01L29/0649H01L29/0653H01L29/66636
    • The invention provides a technique to fabricate a dielectric plug in a MOSFET. The invention includes apparatus and systems that include one or more devices including a MOSFET having a dielectric plug. The dielectric plug is fabricated by forming an oxide layer over exposed source and drain regions in the substrate including a gate electrode stack. The formed oxide layer in the source and drain regions are then substantially removed to expose the substrate in the source and drain regions and to leave a portion of the oxide layer under the gate electrode stack to form the dielectric plug and a channel region between the source and drain regions.
    • 本发明提供了一种制造MOSFET中的电介质塞的技术。 本发明包括包括一个或多个器件的器件和系统,该器件和系统包括具有电介质插塞的MOSFET。 通过在包括栅极电极堆叠的衬底中的暴露的源极和漏极区域上形成氧化物层来制造电介质插塞。 然后基本上除去源极和漏极区域中形成的氧化物层以暴露源极和漏极区域中的衬底,并且将氧化物层的一部分留在栅极电极堆叠下方以形成电介质插塞以及源极之间的沟道区域 和漏区。