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51. 发明授权

US08422327B2 Semiconductor device having nonvolatile memory element and manufacturing method thereof 有权
标题翻译：具有非易失性存储元件的半导体器件及其制造方法
公开(公告)号：US08422327B2
公开(公告)日：2013-04-16
申请号：US12801124
申请日：2010-05-24
申请人： Kazuhiro Teramoto , Hiroki Fujisawa , Susumu Takahashi
发明人： Kazuhiro Teramoto , Hiroki Fujisawa , Susumu Takahashi
IPC分类号： G11C17/18
CPC分类号： G11C29/02 , G11C17/165 , G11C29/027 , G11C29/785 , G11C29/846
摘要： To provide a semiconductor device including a pair of antifuse elements at either a high level or a low level, an OR circuit that outputs different logic information for a case that at least one of the antifuse elements is at a high level and a case that both of the antifuse elements are at a low level, and an exclusive OR circuit that outputs different logic information for a case that the logic states are different from each other and a case that they are same as each other.
摘要翻译：为了提供一种包括高电平或低电平的一对反熔丝元件的半导体器件，OR电路为至少一个反熔丝元件处于高电平的情况下输出不同的逻辑信息，以及两个的反熔丝元件为低电平，异或电路输出逻辑状态彼此不同的情况下的不同的逻辑信息以及彼此相同的情况。

52. 发明授权

US08395412B2 Calibration circuit, semiconductor device including the same, and data processing system 有权
标题翻译：校准电路，包括相同的半导体器件和数据处理系统
公开(公告)号：US08395412B2
公开(公告)日：2013-03-12
申请号：US13067644
申请日：2011-06-16
申请人： Fumiyuki Osanai , Hiroki Fujisawa
发明人： Fumiyuki Osanai , Hiroki Fujisawa
IPC分类号： H03K17/16
CPC分类号： H03K19/0005
摘要： A method includes issuing a calibration command and performing a calibration operation in response to the calibration command. The calibration operation includes adjusting an impedance of a first replica buffer with updating a first code, the first replica buffer being substantially identical in circuit configuration to one of pull-up and pull-down circuits included in an output buffer, adjusting impedance of a second replica buffer with updating a second code, the second replica buffer being substantially identical in circuit configuration to the other of the pull-up and pull-down circuits included in the output buffer, controlling a first latch circuit to hold the first code when the impedance of the first replica buffer reaches a first level, and controlling a second latch circuit to hold the second code when the impedance of the second replica buffer reaches a second level.
摘要翻译：一种方法包括发出校准命令并响应于校准命令执行校准操作。校准操作包括通过更新第一代码来调整第一副本缓冲器的阻抗，第一复制缓冲器在电路配置中基本上与包括在输出缓冲器中的上拉和下拉电路中的一个相同，调整第二代阻抗具有更新第二代码的副本缓冲器，所述第二复制缓冲器在电路配置中与包括在所述输出缓冲器中的所述上拉和下拉电路中的另一个基本相同，当所述阻抗的第一复制缓冲器达到第一电平，并且当第二复制缓冲器的阻抗达到第二电平时，控制第二锁存电路以保持第二代码。

53. 发明授权

US08278973B2 Impedance control circuit and semiconductor device including the same 有权
标题翻译：阻抗控制电路和包括其的半导体器件
公开(公告)号：US08278973B2
公开(公告)日：2012-10-02
申请号：US12707354
申请日：2010-02-17
申请人： Shunji Kuwahara , Hiroki Fujisawa
发明人： Shunji Kuwahara , Hiroki Fujisawa
IPC分类号： H03B1/00
CPC分类号： H03K19/017581 , H03K19/0005
摘要： To include two counter circuits that change impedances of two replica circuits, respectively, and an impedance adjustment control circuit that controls the counter circuits to update count values of the counter circuits. The impedance adjustment control circuit controls one of the counter circuits to finish updating the count value of the counter circuit in response to a change of the impedance of the corresponding replica circuit from a state of being lower than an impedance of an external resistor to a state of being higher than the impedance of the external resistor, and controls the other counter circuit to finish updating the count value of the other counter circuit in response to a change of the impedance of the other replica circuit from a state of being higher than the impedance of the former replica circuit to a state of being lower than the impedance of the former replica circuit. With this configuration, the adjust errors generated in the replica circuits are canceled.
摘要翻译：包括分别改变两个复制电路的阻抗的两个计数器电路以及控制计数器电路来更新计数器电路的计数值的阻抗调整控制电路。阻抗调整控制电路控制其中一个计数器电路，以响应于相应的复制电路的阻抗从低于外部电阻器的阻抗的状态改变到状态来完成对计数器电路的计数值的更新高于外部电阻器的阻抗，并且响应于另一个复制电路的阻抗从高于阻抗的状态改变而控制另一个计数器电路来完成另一个计数器电路的计数值的更新的原始复制电路的状态低于前一复制电路的阻抗。利用这种配置，复制电路中产生的调整错误被取消。

54. 发明申请

US20110062984A1 Semiconductor device having plural unit buffers constituting output buffer 有权
标题翻译：具有构成输出缓冲器的多个单位缓冲器的半导体装置
公开(公告)号：US20110062984A1
公开(公告)日：2011-03-17
申请号：US12923249
申请日：2010-09-10
申请人： Shunji Kuwahara , Hiroki Fujisawa
发明人： Shunji Kuwahara , Hiroki Fujisawa
IPC分类号： H03K19/003 , H03K19/094
CPC分类号： H03K19/0005 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C2207/2254
摘要： To include an output terminal, unit buffers, and plural output-wiring paths that respectively connect the unit buffers and the output terminal. The output wiring paths have individual output wiring sections individually allocated to corresponding unit buffers. Unit buffers corresponding to these output wiring paths are common output wiring sections shared by the output wiring paths, and are connected to the output terminal without via a common output wiring section having a higher resistance value than those of the individual output wiring sections. Accordingly, an deviation of impedance due to a parasitic resistance between the output terminal and the unit buffers is suppressed.
摘要翻译：包括分别连接单元缓冲器和输出端子的输出端子，单元缓冲器和多个输出布线路径。输出布线路径具有分别分配给相应单元缓冲器的各个输出布线部分。对应于这些输出布线路径的单元缓冲器是由输出布线路径共享的公共输出布线部分，并且不经由具有比各个输出布线部分的电阻值高的公共输出布线部分连接到输出端子。因此，抑制了由于输出端子和单元缓冲器之间的寄生电阻引起的阻抗的偏差。

55. 发明申请

US20110058444A1 LATENCY COUNTER, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND DATA PROCESSING SYSTEM 有权
标题翻译：延迟计数器，包括其的半导体存储器件和数据处理系统
公开(公告)号：US20110058444A1
公开(公告)日：2011-03-10
申请号：US12875721
申请日：2010-09-03
申请人： Hiroki Fujisawa
发明人： Hiroki Fujisawa
IPC分类号： G11C8/18 , G11C8/04
CPC分类号： G11C11/4094 , G11C11/4076 , G11C2207/2272
摘要： A latency counter includes a counter circuit and a point-shift FIFO circuit. Latch circuits included in the point-shift FIFO circuit are divided into n groups having wired-OR outputs, and an output of a latch circuit that belongs to a group different from a current group is selected each time a count value is updated. Therefore, an output load is reduced compared to a case where outputs of all the latch circuits are bundled in a wired-OR connection. Further, because there is no need to provide a reset circuit corresponding to each wired-OR wire, it is possible to achieve a reduction in the circuit scale. Furthermore, because a waveform of a signal flowing in the wired-OR wire does not change in a state where internal commands are continuously created in n clock cycles, it is possible to achieve a reduction in the power consumption.
摘要翻译：延迟计数器包括计数器电路和点移位FIFO电路。包括在点移位FIFO电路中的锁存电路被分成具有线或输出的n个组，并且每次更新计数值时选择属于与当前组不同的组的锁存电路的输出。因此，与所有锁存电路的输出以有线或并行的方式捆绑的情况相比，输出负载减小。此外，由于不需要提供对应于每根线或线的复位电路，所以可以实现电路规模的减小。此外，由于在n个时钟周期中连续地创建内部命令的状态下在线或线中流动的信号的波形不变化，因此可以实现功耗的降低。

56. 发明授权

US07902858B2 Calibration circuit, semiconductor device including the same, and memory module 有权
标题翻译：校准电路，包括其的半导体器件和存储器模块
公开(公告)号：US07902858B2
公开(公告)日：2011-03-08
申请号：US12216676
申请日：2008-07-09
申请人： Shunji Kuwahara , Hiroki Fujisawa
发明人： Shunji Kuwahara , Hiroki Fujisawa
IPC分类号： H03K17/16 , H03K19/003 , H03K5/12
CPC分类号： G11C29/02 , G11C5/04 , G11C7/04 , G11C7/1051 , G11C7/1057 , G11C29/022 , G11C29/50008 , G11C2207/2254 , H01L2924/0002 , H01L2924/00
摘要： A calibration circuit includes: a replica buffer that drives a calibration terminal; a pre-emphasis circuit connected in parallel to the replica buffer; and an up-down counter that changes impedances of the replica buffer and the pre-emphasis circuit. A replica control circuit causes the replica buffer to conduct based on an impedance code, and a pre-emphasis control circuit causes the pre-emphasis circuit to conduct in an initial stage of a conducting period of the replica buffer. Thereby, even when an external resistor is shared among a plurality of semiconductor devices, for example, a voltage appearing in the calibration terminal can be stabilized at a higher speed.
摘要翻译：校准电路包括：驱动校准终端的副本缓冲器; 与复制缓冲器并联连接的预加重电路; 以及改变复制缓冲器和预加重电路的阻抗的升降计数器。复制控制电路使得复制缓冲器基于阻抗代码进行，并且预加重控制电路使预加重电路在复制缓冲器的导通周期的初始阶段中进行。因此，即使在多个半导体器件中共享外部电阻器的情况下，例如也可以以更高的速度稳定校准端子中出现的电压。

57. 发明授权

US07872493B2 Calibration circuit 有权
标题翻译：校准电路
公开(公告)号：US07872493B2
公开(公告)日：2011-01-18
申请号：US12453730
申请日：2009-05-20
申请人： Shunji Kuwahara , Hiroki Fujisawa
发明人： Shunji Kuwahara , Hiroki Fujisawa
IPC分类号： H03K19/003
CPC分类号： H03K19/0005 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C29/022 , G11C29/028
摘要： In a calibration control circuit, a first clock gate circuit restricts passage of reference update clocks during a calibration period so as to stop a first one of the reference update clocks and supplies the restricted reference update clocks as first update clocks CLK1 to both a hit determination circuit and a second clock gate circuit. The second clock gate circuit 110 passes through the first update clocks CLK1 until reception of a hit signal from the hit determination circuit and delivers second update clocks CLK2 to an up/down counter 106. The up/down counter 106 is operated by the second update clocks CLK2. With this structure, the second update clocks used for adjustment steps can be increased in number during the calibration period.
摘要翻译：在校准控制电路中，第一时钟门电路在校准周期期间限制参考更新时钟的通过，以停止参考更新时钟中的第一个，并将限制参考更新时钟作为第一更新时钟CLK1提供给命中确定电路和第二时钟门电路。第二时钟门电路110通过第一更新时钟CLK1直到从命中确定电路接收到命中信号，并将第二更新时钟CLK2传送到升/降计数器106.升/减计数器106由第二更新时钟CLK2。利用这种结构，在校准期间可以增加用于调整步骤的第二更新时钟的数量。

58. 发明申请

US20100312956A1 Load reduced memory module 审中-公开
标题翻译：减少内存模块
公开(公告)号：US20100312956A1
公开(公告)日：2010-12-09
申请号：US12801325
申请日：2010-06-03
申请人： Atsushi Hiraishi , Toshio Sugano , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa , Shunichi Saito
发明人： Atsushi Hiraishi , Toshio Sugano , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa , Shunichi Saito
IPC分类号： G06F12/00 , G06F3/00
CPC分类号： G11C5/04 , G11C7/1045 , G11C7/1057 , G11C7/1084 , H01L2224/48091 , H01L2224/48227 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： A memory module includes a plurality of memory chips and a plurality of data register buffers mounted on the module substrate. At least two memory chips are allocated to each of the data register buffers. Each of the data register buffers includes M input/output terminals (M is a positive integer equal to or larger than 1) that are connected to the data connectors via a first data line and N input/output terminals (N is a positive integer equal to or larger than 2M) that are connected to corresponding memory chips via second and third data lines, so that the number of the second and third data lines is N/M times the number of the first data lines. According to the present invention, because the load capacities of the second and third data lines are reduced by a considerable amount, it is possible to realize a considerably high data transfer rate.
摘要翻译：存储器模块包括多个存储器芯片和安装在模块基板上的多个数据寄存器缓冲器。至少两个存储器芯片被分配给每个数据寄存器缓冲器。每个数据寄存器缓冲器包括通过第一数据线连接到数据连接器的M个输入/输出端子（M是等于或大于1的正整数）和N个输入/输出端子（N是正整数等于大于2M），其经由第二和第三数据线连接到对应的存储器芯片，使得第二和第三数据线的数量是第一数据线的数量的N / M倍。根据本发明，由于第二和第三数据线的负载容量减少了很多，所以可以实现相当高的数据传输速率。

59. 发明申请

US20100302833A1 Semiconductor device having nonvolatile memory element and manufacturing method thereof 有权
标题翻译：具有非易失性存储元件的半导体器件及其制造方法
公开(公告)号：US20100302833A1
公开(公告)日：2010-12-02
申请号：US12801124
申请日：2010-05-24
申请人： Kazuhiro Teramoto , Hiroki Fujisawa , Susumu Takahashi
发明人： Kazuhiro Teramoto , Hiroki Fujisawa , Susumu Takahashi
IPC分类号： G11C17/00 , G11C29/04
CPC分类号： G11C29/02 , G11C17/165 , G11C29/027 , G11C29/785 , G11C29/846
摘要： To provide a semiconductor device including a pair of antifuse elements at either a high level or a low level, an OR circuit that outputs different logic information for a case that at least one of the antifuse elements is at a high level and a case that both of the antifuse elements are at a low level, and an exclusive OR circuit that outputs different logic information for a case that the logic states are different from each other and a case that they are same as each other.
摘要翻译：为了提供一种包括高电平或低电平的一对反熔丝元件的半导体器件，OR电路为至少一个反熔丝元件处于高电平的情况下输出不同的逻辑信息，以及两个的反熔丝元件为低电平，异或电路输出逻辑状态彼此不同的情况下的不同的逻辑信息以及彼此相同的情况。

60. 发明授权

US07808270B2 Output circuit for semiconductor device, semiconductor device having output circuit, and method of adjusting characteristics of output circuit 有权
标题翻译：用于半导体器件的输出电路，具有输出电路的半导体器件以及调整输出电路特性的方法
公开(公告)号：US07808270B2
公开(公告)日：2010-10-05
申请号：US12364296
申请日：2009-02-02
申请人： Hiroki Fujisawa
发明人： Hiroki Fujisawa
IPC分类号： H03K17/16 , H03K19/003 , H03B1/00
CPC分类号： H03H11/28 , G01R31/31713 , G11C11/4093 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50008 , H03K19/0005
摘要： To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.
摘要翻译：减少校准输出电路所需的电路规模，并减少校准操作所需的时间。本发明包括连接到数据引脚的第一输出缓冲器和第二输出缓冲器以及连接到校准引脚的校准电路。第一输出缓冲器和第二输出缓冲器包括多个单元缓冲器。单元缓冲器具有相互相同的电路结构。利用这种布置，基于使用校准电路的校准操作，可以将第一输出缓冲器和第二输出缓冲器的阻抗设置为共同的。因此，可以减少校准操作所需的电路规模和校准操作所需的时间。

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