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51. 发明授权

US5849612A MOS poly-si thin film transistor with a flattened channel interface and method of producing same 失效
标题翻译：具有扁平沟道界面的MOS多晶硅薄膜晶体管及其制造方法
公开(公告)号：US5849612A
公开(公告)日：1998-12-15
申请号：US794585
申请日：1997-02-03
申请人： Hiroshi Takahashi , Yoshikazu Kojima
发明人： Hiroshi Takahashi , Yoshikazu Kojima
IPC分类号： H01L21/336 , H01L29/786 , H01L21/84
CPC分类号： H01L29/6675 , H01L29/66757 , H01L29/66765 , H01L29/78642 , H01L29/78648 , H01L29/78675 , H01L29/78678
摘要： A thin film field effect transistor has a three-layer structure including a polycrystalline semiconductor layer to be a channel region, a conductive layer to be a gate electrode and a insulating layer to be a gate insulating film between the channel region and the gate electrode. The roughness of an interface between the channel region and the gate insulating film is less than a few nm so that the current drivability of the transistor is improved.
摘要翻译：薄膜场效应晶体管具有包括作为沟道区的多晶半导体层，作为栅电极的导电层和作为沟道区和栅电极之间的栅极绝缘膜的绝缘层的三层结构。沟道区域和栅极绝缘膜之间的界面的粗糙度小于几nm，从而提高了晶体管的电流驱动能力。

52. 发明授权

US5665960A Photoelectric converter device and method of manufacturing the same 失效
标题翻译：光电转换装置及其制造方法
公开(公告)号：US5665960A
公开(公告)日：1997-09-09
申请号：US618837
申请日：1996-03-20
申请人： Satoshi Machida , Yukito Kawahara , Masahiro Yokomichi , Yoshikazu Kojima
发明人： Satoshi Machida , Yukito Kawahara , Masahiro Yokomichi , Yoshikazu Kojima
IPC分类号： H01L27/146 , H01L31/108 , H04N1/028 , H01J40/14
CPC分类号： H04N5/3745 , H01L27/14654 , H04N5/3591 , H04N5/3597
摘要： A photoelectric converter device having improved residual image characteristics and composed of a transistor having a control electrode region made of a semiconductor of a first conductivity type for accumulating carriers generated by an electromagnetic wave emitted by an object to be detected, a first main electrode region made of a semiconductor of a second conductivity type, and a second main electrode region made of a semiconductor of the second conductivity type, for performing an operation to accumulate the carriers, an operation of reading signals based on the carriers, and an operation of extinguishing the carriers, wherein carriers other than those generated by the electromagnetic wave emitted by the object to be detected are generated in or injected into the control electrode region. Thus, since the amount of excess majority carriers in the control electrode region after the extinguishing operation is always kept substantially constant, improved residual image characteristics are obtained.
摘要翻译：一种具有改善的残留图像特性并由具有由第一导电类型的半导体构成的控制电极区域的晶体管的光电转换器装置，用于累积由待检测物体发射的电磁波产生的载流子，第一主电极区域第二导电类型的半导体和由第二导电类型的半导体构成的第二主电极区域，用于执行累积载流子的操作，基于载流子读取信号的操作以及熄灭的操作载体，其中由待检测对象发射的电磁波产生的载流子以外的载流子生成在或控制电极区域中。因此，由于在灭火操作之后的控制电极区域中的多数载流子的量总是保持基本恒定，因此获得了改善的残留图像特性。

53. 发明授权

US4963855A Warning sound generating device 失效
标题翻译：警示声发生装置
公开(公告)号：US4963855A
公开(公告)日：1990-10-16
申请号：US483258
申请日：1990-02-21
申请人： Yoshikazu Kojima
发明人： Yoshikazu Kojima
IPC分类号： G10K9/22
CPC分类号： G10K9/22
摘要： A warning sound generating device includes a sound source member and an enclosure for protecting the sound source member. A front wall of the enclosure and a sound emitting portion of the sound source member face each other. The front wall of the enclosure has at least one continuous projecting wall extending toward the sound source member. The sound source member has at least one continuous projecting wall extending toward the enclosure and surrounding the sound emitting portion. The enclosure has a plurality of sound exits formed outwardly from the outermost projectng wall of the enclosure. The projecting walls of the sound source member and the enclosure cooperate to define a sound passageway through which a sound generated from the sound emitting portion passes. Each of the projecting walls has a thickness decreasing from the base to the forward rim thereof, so that the passageway has a width between the projecting walls increasing from the sound emitting portion to the sound exits.
摘要翻译：警告声产生装置包括声源构件和用于保护声源构件的外壳。外壳的前壁和声源构件的发声部分彼此面对。外壳的前壁具有朝向声源构件延伸的至少一个连续的突出壁。声源构件具有至少一个连续的突出壁，其朝着外壳延伸并围绕发声部分。外壳具有从外壳的最外侧的投影壁向外形成的多个声音出口。声源构件和外壳的突出壁协作以形成声音通道，声音从声发射部分产生的声音通过该通道。每个突出壁的厚度从基部向其前边缘减小，使得通道具有从发声部分到声音出口的突出壁之间的宽度。

54. 发明授权

US06498376B1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06498376B1
公开(公告)日：2002-12-24
申请号：US08459831
申请日：1995-06-02
申请人： Masanori Miyagi , Haruo Konishi , Kazuaki Kubo , Yoshikazu Kojima , Toru Shimizu , Yutaka Saitoh , Toru Machida , Tetsuya Kaneko
发明人： Masanori Miyagi , Haruo Konishi , Kazuaki Kubo , Yoshikazu Kojima , Toru Shimizu , Yutaka Saitoh , Toru Machida , Tetsuya Kaneko
IPC分类号： H01L2976
CPC分类号： H01L29/78696 , H01L21/3226 , H01L21/823462 , H01L27/0705 , H01L29/1041 , H01L29/1045 , H01L29/66757
摘要： A MISFET is provided with a segmented channel comprising regions in which the channel is inverted by a first gate voltage and regions in which the channel is inverted by a second gate voltage. The MISFET is formed in a semiconductor substrate having a first conductivity type and the first inversion region of the channel has a first impurity concentration determined by the surface concentration of the substrate. The second inversion region of the channel has a second impurity concentration determined by doping an impurity to the region selected by a photolithographic process. The first and second inversion regions may be divided into a plurality of plane shapes and the threshold voltage of the MISFET is set to a desired value in accordance with the plane area ratio of the first and second inversion regions.
摘要翻译： MISFET设置有分段通道，该分段通道包括其中通道被第一栅极电压反相的区域和通道以第二栅极电压反相的区域。 MISFET形成在具有第一导电类型的半导体衬底中，沟道的第一反相区域具有由衬底的表面浓度确定的第一杂质浓度。通道的第二反转区域具有通过将杂质掺杂到通过光刻工艺选择的区域而确定的第二杂质浓度。第一反转区域和第二反转区域可以被划分成多个平面形状，并且根据第一和第二反转区域的平面面积比将MISFET的阈值电压设置为期望值。

55. 发明授权

US06242890B1 Charge/discharge control circuit and chargeable electric power source apparatus 有权
标题翻译：充放电控制电路和充电电源装置
公开(公告)号：US06242890B1
公开(公告)日：2001-06-05
申请号：US09553873
申请日：2000-04-20
申请人： Minoru Sudo , Takayuki Takashina , Yoshikazu Kojima , Sadashi Shimoda , Hiroshi Mukainakano
发明人： Minoru Sudo , Takayuki Takashina , Yoshikazu Kojima , Sadashi Shimoda , Hiroshi Mukainakano
IPC分类号： H02J700
CPC分类号： H02J7/0063
摘要： A charge/discharge control circuit is provided for an electric power source apparatus in which a service life is prolonged. A voltage dividing circuit, an overcharge voltage detection circuit, an overdischarge voltage detection circuit and a control circuit are connected in parallel to a secondary cell which is an electric power source, wherein the control circuit detects a condition of the secondary cell from the overcharge/overdischarge voltage detection circuits and outputs a signal Vs for controlling a power supply to an external equipment and a charge by an external power source and controls a switching element provided in series with the voltage dividing circuit and reduces a current which flows through the voltage dividing circuit.
摘要翻译：为延长使用寿命的电源装置提供充放电控制电路。分压电路，过充电电压检测电路，过放电电压检测电路和控制电路并联连接到作为电源的二次电池，其中控制电路从过充电/过电压检测电路检测二次电池的状态，过放电电压检测电路，输出用于控制外部设备的电力供给的信号Vs和外部电源的电荷，并控制与分压电路串联设置的开关元件，并减少流过分压电路的电流。

56. 发明授权

US06222235B1 Small geometry high voltage semiconductor device 失效
标题翻译：小几何高压半导体器件
公开(公告)号：US06222235B1
公开(公告)日：2001-04-24
申请号：US08677541
申请日：1996-07-10
申请人： Yoshikazu Kojima , Kazutoshi Ishii , Masaaki Kamiya , Yasuhiro Moya
发明人： Yoshikazu Kojima , Kazutoshi Ishii , Masaaki Kamiya , Yasuhiro Moya
IPC分类号： H01L2362
CPC分类号： H01L29/7834 , H01L27/0266 , H01L27/092 , H01L29/0847 , H01L29/105 , H01L29/42364 , H01L29/42368 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including multiple high-voltage drive transistors in its output section is improved in electrostatic withstand voltage by connecting electrostatic protection transistors in parallel with the high-voltage drive transistors connected to the output pads. The drain withstand voltage of the electrostatic protection transistors is made lower than the drain withstand voltage of the high-voltage drive transistors. In addition, the channel length of electrostatic protection transistors is made short to enable efficient bipolar operation of the electrostatic protection transistors.
摘要翻译：在其输出部分中包括多个高电压驱动晶体管的半导体器件通过将静电保护晶体管与连接到输出焊盘的高电压驱动晶体管并联连接来提高静电耐受电压。使静电保护晶体管的漏极耐受电压低于高电压驱动晶体管的漏极耐受电压。此外，静电保护晶体管的沟道长度变短，以实现静电保护晶体管的高效双极性操作。

57. 发明授权

US06087807A Charge/discharge control circuit and chargeable electric power source apparatus 失效
标题翻译：充放电控制电路和充电电源装置
公开(公告)号：US06087807A
公开(公告)日：2000-07-11
申请号：US94037
申请日：1998-06-09
申请人： Minoru Sudo , Takayuki Takashina , Yoshikazu Kojima , Sadashi Shimoda , Hiroshi Mukainakano
发明人： Minoru Sudo , Takayuki Takashina , Yoshikazu Kojima , Sadashi Shimoda , Hiroshi Mukainakano
IPC分类号： G01R31/36 , H01M10/44 , H02H7/18 , H02J7/00 , H02J7/02 , H02J7/10 , H02J7/14
CPC分类号： H02J7/1438 , H02J7/0011 , H02J7/0018 , H02J7/0026 , H02J7/0031 , H02J7/0034 , H02J7/0063 , H02J7/008 , H02J7/0086 , H02J2007/004
摘要： A charge/discharge control circuit is provided for an electric power source apparatus in which a service life is prolonged. A voltage dividing circuit, an overcharge voltage detection circuit, an overdischarge voltage detection circuit and a control circuit are connected in parallel to a secondary cell which is an electric power source, wherein the control circuit detects a condition of the secondary cell from the overcharge/overdischarge voltage detection circuits and outputs a signal Vs for controlling a power supply to an external equipment and a charge by an external power source and controls a switching element provided in series with the voltage dividing circuit and reduces a current which flows through the voltage dividing circuit.
摘要翻译：为延长使用寿命的电源装置提供充放电控制电路。分压电路，过充电电压检测电路，过放电电压检测电路和控制电路并联连接到作为电源的二次电池，其中控制电路从过充电/过电压检测电路检测二次电池的状态，过放电电压检测电路，输出用于控制外部设备的电力供给的信号Vs和外部电源的电荷，并控制与分压电路串联设置的开关元件，并减少流过分压电路的电流。

58. 发明授权

US6022792A Semiconductor dicing and assembling method 失效
标题翻译：半导体切割和组装方法
公开(公告)号：US6022792A
公开(公告)日：2000-02-08
申请号：US815907
申请日：1997-03-12
申请人： Kazutoshi Ishii , Naoto Inoue , Koushi Maemura , Shoji Nakanishi , Yoshikazu Kojima , Kiyoaki Kadoi , Takao Akiba , Yasuhiro Moya , Kentaro Kuhara
发明人： Kazutoshi Ishii , Naoto Inoue , Koushi Maemura , Shoji Nakanishi , Yoshikazu Kojima , Kiyoaki Kadoi , Takao Akiba , Yasuhiro Moya , Kentaro Kuhara
IPC分类号： H01L21/301 , H01L21/78 , H01L23/485 , H01L23/532
CPC分类号： H01L24/05 , H01L21/78 , H01L23/53228 , H01L23/53238 , H01L24/03 , H01L24/13 , H01L24/16 , H01L24/48 , H01L2224/02126 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05012 , H01L2224/05022 , H01L2224/05073 , H01L2224/05166 , H01L2224/05552 , H01L2224/05556 , H01L2224/05557 , H01L2224/05558 , H01L2224/05572 , H01L2224/05599 , H01L2224/05624 , H01L2224/06051 , H01L2224/13017 , H01L2224/13027 , H01L2224/13099 , H01L2224/13144 , H01L2224/4807 , H01L2224/48453 , H01L2224/48463 , H01L2224/75252 , H01L2224/85201 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/10253 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025
摘要： To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.
摘要翻译：为了减小芯片的面积，提高制造效率，降低诸如具有多个输出焊盘的驱动器集成电路等半导体装置以及诸如电子时钟之类的电子电路装置的成本。在驱动晶体管或连接到其的逻辑电路上分别布置有两个重叠的输出焊盘。此外，不仅铝互连而且凸起电极或阻挡金属用于半导体器件的互连。在将半导体集成电路以面朝下的方式电粘接到印刷电路板的情况下，设置在半导体集成电路上的焊料凸块和印刷电路板的互连直接连接，从而实现电气连接。在这种情况下，作为半导体集成电路的外部连接端子的突起电极层叠在晶体管上。

59. 发明授权

US6013940A Poly-crystalline silicon film ladder resistor 失效
标题翻译：多晶硅膜梯形电阻
公开(公告)号：US6013940A
公开(公告)日：2000-01-11
申请号：US516627
申请日：1995-08-18
申请人： Hirofumi Harada , Jun Osanai , Yoshikazu Kojima , Yutaka Saitoh
发明人： Hirofumi Harada , Jun Osanai , Yoshikazu Kojima , Yutaka Saitoh
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L27/06 , H01L27/08 , H01L29/00
CPC分类号： H01L28/20 , H01L27/0629 , H01L27/0802
摘要： A resistor ladder network may be formed with a reduced space on a semiconductor substrate by patterning a plurality of layers of resistive polycrystalline silicon films spaced by insulating layers. Such a device includes a first insulating film formed on a semiconductor substrate, one or more serial-connected first resistors formed in a first polycrystalline silicon film provided on the semiconductor substrate via the first insulating film, a second insulating film provided on the first polycrystalline silicon film, one or more series-connected second resistors formed in a second polycrystalline silicon film provided apart from the first polycrystalline silicon film via the second insulating film, the second polycrystalline silicon film being connected to the first polycrystalline silicon film. A third insulating film is provided over the second polycrystalline silicon film, and metal wires provided on a surface of the second polycrystalline silicon film via contact holes formed in the third insulating film. Preferably, the first polycrystalline silicon film is thicker than the second polycrystalline silicon film, the impurity concentration of the first polycrystalline silicon film is lower than the impurity concentration of the second polycrystalline silicon film, and the grain size of the first polycrystalline silicon film is smaller than that of the second polycrystalline silicon film.
摘要翻译：可以通过对由绝缘层隔开的多层电阻多晶硅膜进行构图而在半导体衬底上形成具有减小的空间的电阻梯形网络。这种器件包括形成在半导体衬底上的第一绝缘膜，经由第一绝缘膜形成在设置在半导体衬底上的第一多晶硅膜中的一个或多个串联连接的第一电阻器，设置在第一多晶硅上的第二绝缘膜膜，一个或多个串联连接的第二电阻器，形成在通过第二绝缘膜与第一多晶硅膜分开设置的第二多晶硅膜中，第二多晶硅膜连接到第一多晶硅膜。在第二多晶硅膜上设置第三绝缘膜，通过形成在第三绝缘膜中的接触孔，设置在第二多晶硅膜的表面上的金属线。优选地，第一多晶硅膜比第二多晶硅膜厚，第一多晶硅膜的杂质浓度低于第二多晶硅膜的杂质浓度，第一多晶硅膜的晶粒尺寸较小比第二多晶硅膜的厚度大。

60. 发明授权

US5982150A Charge/discharge control circuit and chargeable electric power source apparatus 有权
公开(公告)号：US5982150A
公开(公告)日：1999-11-09
申请号：US196697
申请日：1998-11-20
申请人： Minoru Sudo , Takayuki Takashina , Yoshikazu Kojima , Sadashi Shimoda , Hiroshi Mukainakano
发明人： Minoru Sudo , Takayuki Takashina , Yoshikazu Kojima , Sadashi Shimoda , Hiroshi Mukainakano
IPC分类号： G01R31/36 , H01M10/44 , H02H7/18 , H02J7/00 , H02J7/02 , H02J7/10 , H02J7/14 , H01M10/46
CPC分类号： H02J7/1438 , H02J7/0011 , H02J7/0018 , H02J7/0026 , H02J7/0031 , H02J7/0034 , H02J7/0063 , H02J7/008 , H02J7/0086 , H02J2007/004
摘要： A charge/discharge control circuit is provided for an electric power source apparatus in which a service life is prolonged. A voltage dividing circuit, an overcharge voltage detection circuit, an overdischarge voltage detection circuit and a control circuit are connected in parallel to a secondary cell which is an electric power source, wherein the control circuit detects a condition of the secondary cell from the overcharge/overdischarge voltage detection circuits and outputs a signal Vs for controlling a power supply to an external equipment and a charge by an external power source and controls a switching element provided in series with the voltage dividing circuit and reduces a current which flows through the voltage dividing circuit.

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