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51. 发明申请

US20120005513A1 PERFORMANCE CONTROL OF FREQUENCY-ADAPTING PROCESSORS BY VOLTAGE DOMAIN ADJUSTMENT 有权
标题翻译：通过电压调整对频率适配处理器进行性能控制
公开(公告)号：US20120005513A1
公开(公告)日：2012-01-05
申请号：US12827432
申请日：2010-06-30
申请人： Bishop C. Brock , John B. Carter , Alan J. Drake , Michael S. Floyd , Charles R. Lefurgy , Malcolm S. Ware
发明人： Bishop C. Brock , John B. Carter , Alan J. Drake , Michael S. Floyd , Charles R. Lefurgy , Malcolm S. Ware
IPC分类号： G06F1/26 , G06F1/04
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A performance control technique for a processing system that includes one or more adaptively-clocked processor cores provides improved performance/power characteristics. An outer feedback loop adjusts the power supply voltage(s) provided to the power supply voltage domain(s) powering the core(s), which may be on a per-core basis or include multiple cores per voltage domain. The outer feedback loop operates to ensure that each core is meeting specified performance, while the cores also include an inner feedback loop that adjusts their processor clock or other performance control mechanism to maximize performance under present operating conditions and within a margin of safety. The performance of each core is measured and compared to a target performance. If the target performance is not met for each core in a voltage domain, the voltage is raised for the voltage domain until all cores meet the target performance.
摘要翻译：包括一个或多个自适应时钟的处理器核心的处理系统的性能控制技术提供了改进的性能/功率特性。外部反馈环路调整提供给供电核心的电源电压域的电源电压（其可以是基于每个核心的或者每个电压域包括多个核心）。外部反馈环路用于确保每个核心满足指定的性能，而核心还包括一个内部反馈回路，调整其处理器时钟或其他性能控制机制，以最大限度地提高现有操作条件下的性能并在安全范围之内。测量每个核心的性能并将其与目标性能进行比较。如果电压域中的每个核心的目标性能不能满足，则电压域的电压将升高，直到所有核心满足目标性能。

52. 发明授权

US07840825B2 Method for autonomous dynamic voltage and frequency scaling of microprocessors 有权
标题翻译：微处理器自主动态电压和频率缩放的方法
公开(公告)号：US07840825B2
公开(公告)日：2010-11-23
申请号：US11838331
申请日：2007-08-14
申请人： Peter Altevogt , Hans Boettiger , Wesley M. Felter , Charles R. Lefurgy , Lutz Stiege , Malcolm S. Ware
发明人： Peter Altevogt , Hans Boettiger , Wesley M. Felter , Charles R. Lefurgy , Lutz Stiege , Malcolm S. Ware
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method for autonomous dynamic voltage (v) and frequency (f) scaling (DVFS) of a microprocessor, wherein autonomous detection of phases of high microprocessor workload and prediction of their duration is performed (PID). The microprocessor frequency (f) will be temporarily increased (LUT) to an appropriate safe value (even beyond its nominal frequency) consistent with technological and ambient constraints in order to improve performance when the computer system comprising the microprocessor benefits most, while during phases of low microprocessor workload its frequency (f) and voltage (v) will be decreased to save energy. This technique exploits hidden performance capabilities and improves the total performance of a computer system without compromising operational stability. No additional hardware such as service processors is needed for contemporary computer systems supporting performance counters and DFVS already. The invention allows significantly increasing the total computer system performance with only minimal impact on power (PMAX, PACTUAL) consumption.
摘要翻译：一种用于微处理器的自主动态电压（v）和频率（f）缩放（DVFS）的方法，其中执行高微处理器工作负载的相位的自主检测及其持续时间的预测（PID）。微处理器频率（f）将临时增加（LUT）到与技术和环境约束一致的适当安全值（甚至超过其标称频率），以便当包括微处理器的计算机系统受益最大时，提高性能，同时在低微处理器工作负载，其频率（f）和电压（v）将降低以节省能源。该技术利用隐藏的性能功能，并提高计算机系统的总体性能，而不会影响操作稳定性。不需要支持性能计数器和DFVS的现代计算机系统等附加硬件，如服务处理器。本发明允许显着地增加总计算机系统性能，而对功率（PMAX，PACTUAL）消耗的影响最小。

53. 发明授权

US07260487B2 Histogram difference method and system for power/performance measurement and management 有权
公开(公告)号：US07260487B2
公开(公告)日：2007-08-21
申请号：US11289249
申请日：2005-11-29
申请人： Thomas M. Brey , Charles R. Lefurgy , Mark A. Rinaldi , Malcolm S. Ware
发明人： Thomas M. Brey , Charles R. Lefurgy , Mark A. Rinaldi , Malcolm S. Ware
IPC分类号： G06F19/00
CPC分类号： G06F1/3203 , G06F11/3452 , G06F2201/88 , Y02D10/34
摘要： A histogram difference method and system for power/performance measurement and management has low data storage requirements while supporting multiple monitoring applications having different update rates. Histogram data for power usage and/or performance mode is collected at a predetermined rate and the histogram data is read out at periodic intervals by the monitoring applications. The monitoring applications subtract the histogram data from previously read histogram data set to determine a interval difference histogram. The minimum and maximum values for the interval are the lowest-valued and highest-valued bin in the interval difference histogram that have a count greater than zero. The average value for the interval is the mean of the interval difference histogram. A conservative bound of the maximum and minimum values for a system can be determined by adding the values of the maximum and minimum values determined for each subsystem in the system.

54. 发明授权

US08527801B2 Performance control of frequency-adapting processors by voltage domain adjustment 有权
标题翻译：通过电压域调整对频率适配处理器进行性能控制
公开(公告)号：US08527801B2
公开(公告)日：2013-09-03
申请号：US12827432
申请日：2010-06-30
申请人： Bishop C. Brock , John B. Carter , Alan J. Drake , Michael S. Floyd , Charles R. Lefurgy , Malcolm S. Ware
发明人： Bishop C. Brock , John B. Carter , Alan J. Drake , Michael S. Floyd , Charles R. Lefurgy , Malcolm S. Ware
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A performance control technique for a processing system that includes one or more adaptively-clocked processor cores provides improved performance/power characteristics. An outer feedback loop adjusts the power supply voltage(s) provided to the power supply voltage domain(s) powering the core(s), which may be on a per-core basis or include multiple cores per voltage domain. The outer feedback loop operates to ensure that each core is meeting specified performance, while the cores also include an inner feedback loop that adjusts their processor clock or other performance control mechanism to maximize performance under present operating conditions and within a margin of safety. The performance of each core is measured and compared to a target performance. If the target performance is not met for each core in a voltage domain, the voltage is raised for the voltage domain until all cores meet the target performance.
摘要翻译：包括一个或多个自适应时钟的处理器核心的处理系统的性能控制技术提供了改进的性能/功率特性。外部反馈环路调整提供给供电核心的电源电压域的电源电压（其可以是基于每个核心的或者每个电压域包括多个核心）。外部反馈环路用于确保每个核心满足指定的性能，而核心还包括一个内部反馈回路，调整其处理器时钟或其他性能控制机制，以最大限度地提高现有操作条件下的性能并在安全范围之内。测量每个核心的性能并将其与目标性能进行比较。如果电压域中的每个核心的目标性能不能满足，则电压域的电压将升高，直到所有核心满足目标性能。

55. 发明申请

US20080098254A1 Method for Autonomous Dynamic Voltage and Frequency Scaling of Microprocessors 有权
标题翻译：微处理器的自动动态电压和频率调节方法
公开(公告)号：US20080098254A1
公开(公告)日：2008-04-24
申请号：US11838331
申请日：2007-08-14
申请人： Peter Altevogt , Hans Boettiger , Wesley M. Felter , Charles R. Lefurgy , Lutz Stiege , Malcolm S. Ware
发明人： Peter Altevogt , Hans Boettiger , Wesley M. Felter , Charles R. Lefurgy , Lutz Stiege , Malcolm S. Ware
IPC分类号： G06F1/08
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method for autonomous dynamic voltage (v) and frequency (f) scaling (DVFS) of a microprocessor, wherein autonomous detection of phases of high microprocessor workload and prediction of their duration is performed (PID). The microprocessor frequency (f) will be temporarily increased (LUT) to an appropriate safe value (even beyond its nominal frequency) consistent with technological and ambient constraints in order to improve performance when the computer system comprising the microprocessor benefits most, while during phases of low microprocessor workload its frequency (f) and voltage (v) will be decreased to save energy. This technique exploits hidden performance capabilities and improves the total performance of a computer system without compromising operational stability. No additional hardware such as service processors is needed for contemporary computer systems supporting performance counters and DFVS already. The invention allows significantly increasing the total computer system performance with only minimal impact on power (PMAX, PACTUAL) consumption.
摘要翻译：一种用于微处理器的自主动态电压（v）和频率（f）缩放（DVFS）的方法，其中执行高微处理器工作负载的相位的自主检测及其持续时间的预测（PID）。微处理器频率（f）将临时增加（LUT）到与技术和环境约束一致的适当的安全值（甚至超过其标称频率），以便当包括微处理器的计算机系统受益最大时，提高性能，同时在低微处理器工作负载，其频率（f）和电压（v）将降低以节省能源。该技术利用隐藏的性能功能，并提高计算机系统的总体性能，而不会影响操作稳定性。不需要支持性能计数器和DFVS的现代计算机系统等附加硬件，如服务处理器。本发明允许显着地增加总计算机系统的性能，而对功率（P MAX），功耗（P <

56. 发明授权

US08832479B2 Optimizing energy consumption and application performance in a multi-core multi-threaded processor system 有权
标题翻译：在多核多线程处理器系统中优化能耗和应用性能
公开(公告)号：US08832479B2
公开(公告)日：2014-09-09
申请号：US13416583
申请日：2012-03-09
申请人： Elmootazbellah N. Elnozahy , Heather L. Hanson , Freeman L. Rawson , Malcolm S. Ware
发明人： Elmootazbellah N. Elnozahy , Heather L. Hanson , Freeman L. Rawson , Malcolm S. Ware
IPC分类号： G06F1/32
CPC分类号： G06F9/4893 , G06F1/3203 , G06F1/329 , G06F9/5044 , G06F9/5094 , G06F2209/508 , Y02D10/126 , Y02D10/22 , Y02D10/24
摘要： A mechanism is provided for scheduling application tasks. A scheduler receives a task that identifies a desired frequency and a desired maximum number of competing hardware threads. The scheduler determines whether a user preference designates either maximization of performance or minimization of energy consumption. Responsive to the user preference designating the performance, the scheduler determines whether there is an idle processor core in a plurality of processor cores available. Responsive to no idle processor being available, the scheduler identifies a subset of processor cores having a smallest load coefficient. From the subset of processor cores, the scheduler determines whether there is at least one processor core that matches desired parameters of the task. Responsive to at least one processor core matching the desired parameters of the task, the scheduler assigns the task to one of the at least one processor core that matches the desired parameters.
摘要翻译：提供了一种调度应用程序任务的机制。调度器接收标识期望频率和期望的最大数量的竞争硬件线程的任务。调度器确定用户偏好是指性能的最大化还是能量消耗的最小化。响应于指定性能的用户偏好，调度器确定在多个处理器核心中是否存在可用的空闲处理器核心。响应于没有空闲处理器可用，调度器识别具有最小负载系数的处理器核心的子集。从处理器核心的子集中，调度器确定是否存在与任务的期望参数匹配的至少一个处理器核心。响应于至少一个与任务的期望参数匹配的处理器核心，调度器将该任务分配给与期望参数匹配的至少一个处理器核心中的一个。

57. 发明授权

US08635478B2 Establishing an operating range for dynamic frequency and voltage scaling 有权
标题翻译：建立动态频率和电压调整的工作范围
公开(公告)号：US08635478B2
公开(公告)日：2014-01-21
申请号：US13340640
申请日：2011-12-29
申请人： Harold W. Chase , Joshua D. Friedrich , Andrew J. Geissler , Soraya Ghiasi , Norman K. James , Jagat V. Pokala , Malcolm S. Ware
发明人： Harold W. Chase , Joshua D. Friedrich , Andrew J. Geissler , Soraya Ghiasi , Norman K. James , Jagat V. Pokala , Malcolm S. Ware
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： During manufacture, an operating range for dynamic voltage and frequency scaling can be established. A nominal operating point is identified based on a design nominal operating frequency for a computer processor. The nominal operating point comprises a nominal operating voltage identified for the design nominal operating frequency. In dependence upon the nominal operating point, an operating range of frequency and voltage over which the computer processor is to function is determined. Information specifying the nominal operating point and the operating range is stored in non-volatile storage associated with the computer processor.
摘要翻译：在制造过程中，可以建立动态电压和频率缩放的工作范围。基于计算机处理器的设计标称工作频率来识别标称工作点。标称工作点包括为设计额定工作频率确定的标称工作电压。根据标称工作点，确定计算机处理器在其上工作的频率和电压的工作范围。指定名义操作点和操作范围的信息存储在与计算机处理器相关联的非易失性存储器中。

58. 发明授权

US08032334B2 Sensor subset selection for reduced bandwidth and computation requirements 失效
标题翻译：用于降低带宽和计算要求的传感器子集选择
公开(公告)号：US08032334B2
公开(公告)日：2011-10-04
申请号：US12342054
申请日：2008-12-22
申请人： Andreas Bieswanger , Michael S. Floyd , Andrew J. Geissler , Soraya Ghiasi , Hye-Young McCreary , Guillermo J. Silva , Malcolm S. Ware
发明人： Andreas Bieswanger , Michael S. Floyd , Andrew J. Geissler , Soraya Ghiasi , Hye-Young McCreary , Guillermo J. Silva , Malcolm S. Ware
IPC分类号： G06F11/00 , G06F19/00
CPC分类号： G06F11/30
摘要： A system for identifying a subset of sensors to sample to reduce the frequency of sensor access. The system determines rise times and records values for the sensors in the system. A time criticality of the sensors is determined based on the rise times. The system processes the sensors by first creating sensor subsets based on one or more constraints on the sensors. The system monitors the values of the sensors in a sensor subset and flags a sensor when it makes a determination that, prior to a next scheduled sampling of the sensor subset, the value of a sensor in the monitored sensor subset will exceed a threshold constraint. The system moves those flagged sensors to a second sensor subset which complies with the sensor's constraints.
摘要翻译：用于识别要采样的传感器子集以减少传感器访问频率的系统。系统确定系统中传感器的上升时间和记录值。基于上升时间确定传感器的时间关键度。该系统通过首先基于传感器上的一个或多个约束创建传感器子集来处理传感器。系统监测传感器子集中的传感器的值，并且当传感器确定在传感器子集的下次调度采样之前，所述传感器子集中的传感器的值将超过阈值约束时，对传感器进行标记。系统将标记的传感器移动到符合传感器约束的第二个传感器子集。

59. 发明授权

US08909383B2 Proactive cooling of chips using workload information and controls 有权
标题翻译：使用工作负载信息和控制来主动冷却芯片
公开(公告)号：US08909383B2
公开(公告)日：2014-12-09
申请号：US13334903
申请日：2011-12-22
申请人： Scott J. Hadderman , Daniel J. Kearney , Wei Huang , K. Paul Muller , William J. Rooney , Guillermo J. Silva , Malcolm S. Ware , Emmanuel Yashchin , Peter B. Yocom
发明人： Scott J. Hadderman , Daniel J. Kearney , Wei Huang , K. Paul Muller , William J. Rooney , Guillermo J. Silva , Malcolm S. Ware , Emmanuel Yashchin , Peter B. Yocom
IPC分类号： G05D23/00 , G01K7/00 , H01L35/00 , H01L37/00 , H03K3/42 , H03K17/78
CPC分类号： G05D23/1919 , G06F1/206 , Y02D10/16
摘要： A method to reduce large temperature over/undershoot in a computer system. Using workload data, the method proactively modifies controls of mechanical cooling system to anticipate power and take appropriate actions to maintain temperature. Workload control modifies workload and scheduling to reduce power transients and subsequent temperature deviations. In addition, workload control allows more even distribution of temp across chips, allowing for even wear and reduction of small/ripple/noise temp oscillations. A system and program product for carrying out the method are also provided.
摘要翻译：一种减少计算机系统中温度过高/欠冲击的方法。使用工作负载数据，该方法主动修改机械冷却系统的控制以预测功率并采取适当的措施来保持温度。工作负载控制可以修改工作负载和调度，以减少电力瞬变和随后的温度偏差。此外，工作负载控制可以更均匀地分配芯片间的温度，从而可以均匀磨损和减少小/纹波/噪声温度振荡。还提供了一种用于执行该方法的系统和程序产品。

60. 发明申请

US20130166095A1 Proactive Cooling Of Chips Using Workload Information and Controls 有权
标题翻译：使用工作负载信息和控件主动冷却芯片
公开(公告)号：US20130166095A1
公开(公告)日：2013-06-27
申请号：US13334903
申请日：2011-12-22
申请人： Scott J. Hadderman , Daniel J. Kearney , Wei Huang , K. Paul Muller , William J. Rooney , Guillermo J. Silva , Malcolm S. Ware , Emmanuel Yashchin , Peter B. Yocom
发明人： Scott J. Hadderman , Daniel J. Kearney , Wei Huang , K. Paul Muller , William J. Rooney , Guillermo J. Silva , Malcolm S. Ware , Emmanuel Yashchin , Peter B. Yocom
IPC分类号： G05D23/19
CPC分类号： G05D23/1919 , G06F1/206 , Y02D10/16
摘要： A method to reduce large temperature over/undershoot in a computer system. Using workload data, the method proactively modifies controls of mechanical cooling system to anticipate power and take appropriate actions to maintain temperature. Workload control modifies workload and scheduling to reduce power transients and subsequent temperature deviations. In addition, workload control allows more even distribution of temp across chips, allowing for even wear and reduction of small/ripple/noise temp oscillations. A system and program product for carrying out the method are also provided.
摘要翻译：一种减少计算机系统中温度过高/欠冲击的方法。使用工作负载数据，该方法主动修改机械冷却系统的控制以预测功率并采取适当的措施来保持温度。工作负载控制可以修改工作负载和调度，以减少电力瞬变和随后的温度偏差。此外，工作负载控制可以更均匀地分配芯片间的温度，从而可以均匀磨损和减少小/纹波/噪声温度振荡。还提供了一种用于执行该方法的系统和程序产品。

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