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51. 发明申请

US20060289925A1 NON-VOLATILE MEMORY, MANUFACTURING METHOD AND OPERATING METHOD THEREOF 有权
标题翻译：非易失性存储器，制造方法及其工作方法
公开(公告)号：US20060289925A1
公开(公告)日：2006-12-28
申请号：US11306093
申请日：2005-12-15
申请人： Wei-Zhe Wong , Ching-Sung Yang
发明人： Wei-Zhe Wong , Ching-Sung Yang
IPC分类号： H01L29/788 , H01L21/8238
CPC分类号： H01L29/7887 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L29/4232 , H01L29/42324 , H01L29/42328 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/7923
摘要： A non-volatile memory including at least a substrate, a memory cell and source/drain regions is provided. The memory cell is disposed on the substrate and includes at least a first memory unit and a second memory unit. Wherein, the first memory unit, from the substrate up, includes a floating gate and a first control gate. The second memory unit is disposed on a sidewall of the first memory unit and includes a charge trapping layer and a second control gate. The two source/drain regions are disposed in the substrate at both sides of the memory cell.
摘要翻译：提供至少包括衬底，存储单元和源极/漏极区域的非易失性存储器。存储单元设置在基板上，并且至少包括第一存储单元和第二存储单元。其中，第一存储单元从衬底向上包括浮动栅极和第一控制栅极。第二存储器单元设置在第一存储器单元的侧壁上，并且包括电荷捕获层和第二控制栅极。两个源极/漏极区域设置在存储单元两侧的衬底中。

52. 发明申请

US20060186481A1 NON-VOLATILE MEMORY AND MANUFACTURING METHOD AND OPERATING METHOD THEREOF 审中-公开
标题翻译：非易失性存储器及其制造方法及其工作方法
公开(公告)号：US20060186481A1
公开(公告)日：2006-08-24
申请号：US11161312
申请日：2005-07-29
申请人： Ching-Sung Yang , Wei-Zhe Wong , Chih-Chen Cho
发明人： Ching-Sung Yang , Wei-Zhe Wong , Chih-Chen Cho
IPC分类号： H01L29/76
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A non-volatile memory having many memory cell columns is provided. Each memory cell column includes a plurality of memory cells formed on a substrate. A deep p-type well is disposed in the substrate and an n-type well is disposed on the deep p-type well. A shallow p-type well isolated by device isolation structures is disposed on the n-type well. A select unit is disposed on one side of each memory cell column. An n-type source region is disposed in the substrate adjacent to the select unit. An n-type drain region is disposed in the substrate on the other side of the memory cell column. A bit line is disposed on the substrate. The bit line connects with the n-type drain region through a conductive plug. The conductive plug penetrates the junction between the n-type drain region and the shallow p-type well and forms a short between them.
摘要翻译：提供了具有许多存储单元列的非易失性存储器。每个存储单元列包括形成在基板上的多个存储单元。在衬底中设置深p型阱，在深p型阱上设置n型阱。通过器件隔离结构隔离的浅P型阱设置在n型阱上。选择单元设置在每个存储单元列的一侧。 n型源极区域设置在与选择单元相邻的衬底中。在存储单元列的另一侧的衬底中设置n型漏极区。位线设置在基板上。位线通过导电插头与n型漏极区域连接。导电插塞穿透n型漏极区和浅P型阱之间的结，并在它们之间形成短路。

53. 发明申请

US20060170038A1 NON-VOLATILE MEMORY AND MANUFACTURING AND OPERATING METHOD THEREOF 有权
标题翻译：非易失性存储器及其制造和操作方法
公开(公告)号：US20060170038A1
公开(公告)日：2006-08-03
申请号：US11161398
申请日：2005-08-02
申请人： Wei-Zhe Wong , Ching-Sung Yang
发明人： Wei-Zhe Wong , Ching-Sung Yang
IPC分类号： H01L29/94
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521
摘要： A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjacent trenches respectively. A plurality of select gate dielectric layers are disposed between the select gates and the substrate. A plurality of composite layers are disposed over the surface of the trenches and each composite layer has a charge trapping layer. A plurality of word lines are arranged in parallel in a second direction, wherein each of the word lines fills the trenches between adjacent select gates and is disposed over the composite layers.
摘要翻译：提供非易失性存储器。提供具有多个沟槽和多个选择栅极的衬底。沟槽平行布置并沿第一方向延伸。每个选择栅极分别设置在两个相邻沟槽之间的衬底上。在选择栅极和衬底之间设置多个选择栅极电介质层。多个复合层设置在沟槽的表面上，并且每个复合层具有电荷捕获层。多个字线在第二方向上平行布置，其中每条字线填充相邻选择栅之间的沟槽并且设置在复合层之上。

54. 发明申请

US20060170026A1 NON-VOLATILE MEMORY AND FABRICATING METHOD AND OPERATING METHOD THEREOF 有权
标题翻译：非挥发性记忆及其制作方法及其操作方法
公开(公告)号：US20060170026A1
公开(公告)日：2006-08-03
申请号：US11162116
申请日：2005-08-29
申请人： Wei-Zhe Wong , Ching-Sung Yang , Chih-Chen Cho
发明人： Wei-Zhe Wong , Ching-Sung Yang , Chih-Chen Cho
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： G11C16/0416 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7887
摘要： A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are located in the substrate at the peripheries of the stacked gate structures; each of the pocket doped regions extends under the stacked gate structure. Drain regions are located in the pocket doped regions at the peripheries of the stacked gate structures. An auxiliary gate layer is located on the substrate between the stacked gate structures. A gate dielectric layer is located between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structure. Plugs are located on the substrate and extended to connect with the pocket doped region and the drain regions therein.
摘要翻译：提供非易失性存储器。衬底在其中具有至少两个隔离结构以限定有效区域。一个井位于基板中。浅掺杂区域位于井中。至少两个堆叠的栅极结构位于衬底上。袋状掺杂区域位于堆叠栅极结构的周边的衬底中; 每个口袋掺杂区域在堆叠的栅极结构之下延伸。漏极区位于堆叠栅极结构的周边的口袋掺杂区域中。辅助栅极层位于堆叠栅极结构之间的衬底上。栅极电介质层位于辅助栅极层和衬底之间，并且位于辅助栅极层和堆叠栅极结构之间。插头位于衬底上并延伸以与其中的口袋掺杂区域和漏极区域连接。

55. 发明申请

US20060097325A1 One-time programmable read only memory and operating method thereof 有权
标题翻译：一次性可编程只读存储器及其操作方法
公开(公告)号：US20060097325A1
公开(公告)日：2006-05-11
申请号：US11144471
申请日：2005-06-02
申请人： Ching-Sung Yang , Wei-Zhe Wong , Chih-Chen Cho
发明人： Ching-Sung Yang , Wei-Zhe Wong , Chih-Chen Cho
IPC分类号： H01L29/94
CPC分类号： H01L27/112 , H01L27/11206
摘要： A one-time programmable read only memory is provided. The memory includes a substrate, a select transistor, an electrode and a dielectric layer. The select transistor is formed on the substrate. The electrode is formed over the source region of the select transistor. The dielectric layer is formed between the electrode and the source region of the select transistor. Digital data is stored in the memory through the breakdown or not of the dielectric layer.
摘要翻译：提供一次性可编程只读存储器。存储器包括衬底，选择晶体管，电极和电介质层。选择晶体管形成在基板上。电极形成在选择晶体管的源极区域上。介电层形成在选择晶体管的电极和源极区之间。数字数据通过绝缘层的击穿而不是存储在存储器中。

56. 发明申请

US20060060910A1 NONVOLATILE MEMORY AND MANUFACTURING METHOD AND OPERATING METHOD THEREOF 有权
标题翻译：非易失性存储器及其制造方法及其工作方法
公开(公告)号：US20060060910A1
公开(公告)日：2006-03-23
申请号：US11160175
申请日：2005-06-13
申请人： Ching-Sung Yang , Wei-Zhe Wong , Chih-Chen Cho
发明人： Ching-Sung Yang , Wei-Zhe Wong , Chih-Chen Cho
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： G11C16/0466 , H01L27/10861 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792 , Y10S257/905 , Y10S257/906 , Y10S257/908
摘要： A nonvolatile memory is provided. The memory includes a select transistor and a trench transistor. The select transistor is formed on the substrate. The select transistor includes a first gate formed on the substrate and first and second source/drain regions formed in the substrate next to the first gate. The trench transistor is formed in the substrate. The trench transistor includes a second gate formed in the trench of substrate, an electron trapping layer formed between the second gate and the trench and second and third source/drain regions formed in the substrate next to the second gate. The select transistor and the trench transistor share the second source/drain region.
摘要翻译：提供非易失性存储器。存储器包括选择晶体管和沟槽晶体管。选择晶体管形成在基板上。选择晶体管包括形成在衬底上的第一栅极和形成在第一栅极旁边的衬底中的第一和第二源极/漏极区域。在衬底中形成沟槽晶体管。沟槽晶体管包括形成在衬底的沟槽中的第二栅极，形成在第二栅极和沟槽之间的电子俘获层以及形成在第二栅极旁边的衬底中的第二和第三源/漏区。选择晶体管和沟槽晶体管共享第二源极/漏极区域。

57. 发明申请

US20060024887A1 FLASH MEMORY CELL AND FABRICATING METHOD THEREOF 失效
标题翻译：闪存存储单元及其制作方法
公开(公告)号：US20060024887A1
公开(公告)日：2006-02-02
申请号：US10904749
申请日：2004-11-25
申请人： Wei-Zhe Wong , Ching-Sung Yang
发明人： Wei-Zhe Wong , Ching-Sung Yang
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0433 , G11C16/3468 , H01L21/28273 , H01L27/11521 , H01L27/11526 , H01L27/11529 , H01L29/42328 , H01L29/66825 , H01L29/7881
摘要： A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked gate structure. A select gate is disposed between the stacked gate structure and the source region. A first gate dielectric layer is disposed between the select gate and the stacked gate structure. A second gate dielectric layer is disposed between the select gate and the substrate. A shallow doped region is disposed in the substrate under the stacked gate structure and the select gate. A deep doped region is disposed in the substrate on one side of the stacked gate structure. The conductive plug on the substrate extends through the drain region and the deep doped region.
摘要翻译：提供闪存单元。将深井设置在基板中，并将井设置在深井内。层叠栅极结构设置在基板上。源极区域和漏极区域设置在堆叠栅极结构的每一侧上的衬底中。选择栅极设置在堆叠的栅极结构和源极区域之间。第一栅极介电层设置在选择栅极和堆叠栅极结构之间。第二栅极电介质层设置在选择栅极和衬底之间。在堆叠栅极结构和选择栅极之下的衬底中设置浅掺杂区域。在堆叠栅极结构的一侧上的衬底中设置深掺杂区域。衬底上的导电插塞延伸穿过漏区和深掺杂区。

58. 发明授权

US06710397B1 Nonvolatile semiconductor memory device having divided bit lines 失效
标题翻译：具有划分位线的非易失性半导体存储器件
公开(公告)号：US06710397B1
公开(公告)日：2004-03-23
申请号：US10604406
申请日：2003-07-17
申请人： Ching-Hsiang Hsu , Ching-Sung Yang
发明人： Ching-Hsiang Hsu , Ching-Sung Yang
IPC分类号： H01L29788
CPC分类号： G11C16/24
摘要： A non-volatile semiconuctor memory device having divided bit lines. A main bit line controlled by at least one bit line selection device to transfer its potential selected sub bit line, such that memory cells in a selected work and overloading of the bit line generated by a parasitic capacitance can be prevented. The memory cells and the bit line selection device arranged in parallel in a P-well and a N-well, respectively, thereby preventing disturbances during programming or erasing the bit line.
摘要翻译：具有划分位线的非易失性半导体存储器件。由至少一个位线选择装置控制的主位线传送其潜在的选择的子位线，使得可以防止所选择的工作中的存储器单元和由寄生电容产生的位线的过载。存储单元和位线选择装置分别并排布置在P阱和N阱中，从而防止在编程或擦除位线期间的干扰。

59. 发明授权

US06678190B2 Single poly embedded eprom 有权
标题翻译：单聚嵌入eprom
公开(公告)号：US06678190B2
公开(公告)日：2004-01-13
申请号：US10055047
申请日：2002-01-25
申请人： Ching-Sung Yang , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Ching-Sung Yang , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/0433 , G11C2216/10 , H01L27/11558
摘要： An erasable programmable read only memory comprising two serially connected P-type metal-oxide semiconductor (MOS) transistors wherein the control gate is omitted in the structure for layout as the bias is not necessary to apply to the floating gate during the programming mode.
摘要翻译：一种可擦除可编程只读存储器，包括两个串联连接的P型金属氧化物半导体（MOS）晶体管，其中在布局结构中省略了控制栅极，因为在编程模式期间偏置不需要应用于浮动栅极。

60. 发明授权

US06677198B2 Structure of a low-voltage channel write/erase flash memory cell and fabricating method thereof 失效
标题翻译：低电压通道写入/擦除闪存单元的结构及其制造方法
公开(公告)号：US06677198B2
公开(公告)日：2004-01-13
申请号：US10064109
申请日：2002-06-12
申请人： Ching-Hsiang Hsu , Ching-Sung Yang
发明人： Ching-Hsiang Hsu , Ching-Sung Yang
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/7883
摘要： The present invention relates to a structure of a low-voltage channel write/erase flash memory cell and a fabricating method thereof, which structure comprises an N-substrate, a deep P-well formed on the substrate, and an N-well formed on the deep P-well. A deep p-type region and a shallow p-type region are ion-implanted in the N-well. The deep p-type region is connected to the shallow p-type region. An n-type region is ion-implanted in the deep p-type region to be electrically shorted with the deep p-type region and be used as a drain. Another n-type region is also ion-implanted at one side of the shallow p-type region to be used as a source. The present invention can apply the same voltage to the deep P-well and the N-well on the N-substrate by adding in a triple well architecture so that the leakage current capably generated can be reduced to minimum, thereby effectively reducing end voltages when performing the operation of erasing, simplifying the design complexity of a charge pump circuit required by the whole structure, and enhancing the operating efficiency.
摘要翻译：本发明涉及一种低电压通道写入/擦除闪速存储单元的结构及其制造方法，该结构包括N衬底，在衬底上形成的深P阱以及形成在N阱上的N阱深P井。将深P型区域和浅P型区域离子注入到N阱中。深P型区域连接到浅P型区域。在深p型区域中离子注入n型区域，与深p型区域电短路并用作漏极。另一个n型区域也被离子注入在用作源的浅P型区域的一侧。本发明可以通过添加三阱结构将相同的电压施加在N衬底上的深P阱和N阱上，使得可以产生的泄漏电流可以减小到最小，从而有效地减少最终电压，当执行擦除操作，简化了整个结构所需的电荷泵电路的设计复杂度，提高了运行效率。

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