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51. 发明申请

US20060258060A1 Gate controlled floating well vertical MOSFET 审中-公开
标题翻译：门控浮动阱垂直MOSFET
公开(公告)号：US20060258060A1
公开(公告)日：2006-11-16
申请号：US11487809
申请日：2006-07-17
申请人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang
发明人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang
IPC分类号： H01L21/339
CPC分类号： H01L27/10864 , H01L27/0214 , H01L27/10841
摘要： A novel transistor structure for a DRAM cell includes two deep trenches, one trench including a vertical storage cell for storing the data and the second trench including a vertical control cell for controlling the p-well voltage, which, in effect, places part of the p-well in a floating condition thus decreasing the threshold voltage as compared to when the vertical pass transistor is in an off-state. This enables the transistor to exhibit increased gate over-drive and drive current during an active wordline voltage commonly applied to both gates of the storage and control cells.
摘要翻译：用于DRAM单元的新型晶体管结构包括两个深沟槽，一个沟槽包括用于存储数据的垂直存储单元，第二沟槽包括用于控制p阱电压的垂直控制单元，其实际上将部分 p阱处于浮置状态，从而与垂直传输晶体管处于截止状态时相比降低阈值电压。这使得晶体管在通常施加到存储和控制单元的两个门的有效字线电压期间表现出增加的栅极过驱动和驱动电流。

52. 发明授权

US07005744B2 Conductor line stack having a top portion of a second layer that is smaller than the bottom portion 失效
标题翻译：导体线堆叠具有小于底部的第二层的顶部
公开(公告)号：US07005744B2
公开(公告)日：2006-02-28
申请号：US10605308
申请日：2003-09-22
申请人： Xiangdong Chen , Li Wang
发明人： Xiangdong Chen , Li Wang
IPC分类号： H01L29/41 , H01L29/49
CPC分类号： H01L27/10888 , H01L21/76897 , H01L23/485 , H01L27/10861 , H01L27/10873 , H01L2924/0002 , H01L2924/00
摘要： A structure and method are provided for a conductor line stack of an integrated circuit. The conductor line stack includes a layer of a first material such as heavily doped polysilicon or a metal silicide. A layer of a second material such as a metal is formed over the layer of first material, the layer of second material having an upper portion and a lower portion. A pair of first spacers is disposed on sidewalls of the upper portion, wherein the lower portion has width defined by a combined width of the upper portion and the pair of first spacers. A pair of second spacers is formed on sidewalls of the first spacers, the lower portion and the layer of first material. The conductor line stack structure is well adapted for formation of a borderless bitline contact in contact therewith.
摘要翻译：为集成电路的导线堆叠提供了一种结构和方法。导线堆叠包括第一材料层，例如重掺杂多晶硅或金属硅化物。在第一材料层上形成诸如金属的第二材料层，第二材料层具有上部和下部。一对第一间隔件设置在上部的侧壁上，其中下部具有由上部和第一对间隔件的组合宽度限定的宽度。在第一间隔件，下部和第一材料层的侧壁上形成一对第二间隔件。导体线堆叠结构很好地适于形成与其接触的无边界位线接触。

53. 发明授权

US06744083B2 Submicron MOSFET having asymmetric channel profile 有权
标题翻译：具有不对称沟道轮廓的亚微米MOSFET
公开(公告)号：US06744083B2
公开(公告)日：2004-06-01
申请号：US10263111
申请日：2002-10-01
申请人： Xiangdong Chen , Sanjay Kumar Banerjee
发明人： Xiangdong Chen , Sanjay Kumar Banerjee
IPC分类号： H01L29768
CPC分类号： H01L29/78642 , B82Y10/00 , H01L29/1045 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/66666 , H01L29/7827 , H01L29/7833
摘要： A MOSFET semiconductor device having an asymmetric channel region between the source region and the drain region. In one embodiment, the device comprises a mesa structure on a silicon substrate with the source region being in the substrate and the mesa structure extending from the source region and substrate. The asymmetric channel region can include silicon abutting the source region and a heterostructure material such as Si1-xGex extending to and abutting the drain region. The mole fraction of Ge can increase towards the drain region either uniformly or in steps. In one embodiment, the doping profile of the channel region is non-uniform with higher doping near the source region and lower doping near the drain region.
摘要翻译： MOSFET源极区和漏极区之间具有不对称沟道区的MOSFET半导体器件。在一个实施例中，该器件包括在硅衬底上的台面结构，其中源极区位于衬底中，并且台面结构从源极区域和衬底延伸。不对称沟道区可以包括邻接源极区域的硅和延伸到漏极区域并邻接漏极区域的异质结构材料，例如Si1-xGex。 Ge的摩尔分数可以均匀地或逐步地朝向漏极区域增加。在一个实施例中，沟道区域的掺杂分布不均匀，源极区附近具有更高的掺杂，而在漏极区附近具有较低的掺杂。

54. 发明授权

US09153507B2 Semiconductor package with improved testability 有权
标题翻译：半导体封装具有改进的可测试性
公开(公告)号：US09153507B2
公开(公告)日：2015-10-06
申请号：US13362344
申请日：2012-01-31
申请人： Sam Ziqun Zhao , Kevin Kunzhong Hu , Sampath K. V. Karikalan , Rezaur Rahman Khan , Pieter Vorenkamp , Xiangdong Chen
发明人： Sam Ziqun Zhao , Kevin Kunzhong Hu , Sampath K. V. Karikalan , Rezaur Rahman Khan , Pieter Vorenkamp , Xiangdong Chen
IPC分类号： G01R31/02 , H01L21/66 , H01L23/31 , H01L23/498 , H01L21/56 , H01L23/00
CPC分类号： H01L22/32 , H01L21/561 , H01L23/3128 , H01L23/49811 , H01L23/49827 , H01L23/49833 , H01L24/16 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/97 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/1533 , H01L2924/15331 , H01L2224/81 , H01L2924/014
摘要： An exemplary implementation of the present disclosure includes a testable semiconductor package that includes an active die having interface contacts and dedicated testing contacts. An interposer is situated adjacent a bottom surface of the active die, the interposer providing electrical connections between the interface contacts and a bottom surface of the testable semiconductor package. At least one conductive medium provides electrical connection between at least one of the dedicated testing contacts and a top surface of the testable semiconductor package. The at least one conductive medium can be coupled to a package-top testing connection, which may include a solder ball.
摘要翻译：本公开的示例性实现包括可测试的半导体封装，其包括具有接口触点和专用测试触点的有源裸片。插入器位于有源裸片的底表面附近，插入器提供接口触点之间的电连接和可测试的半导体封装的底表面。至少一个导电介质提供至少一个专用测试触点和可测半导体封装的顶表面之间的电连接。所述至少一个导电介质可以耦合到封装顶部测试连接，其可以包括焊球。

55. 发明授权

US08890288B2 MOM capacitor having local interconnect metal plates and related method 有权
标题翻译：具有局部互连金属板的MOM电容器及相关方法
公开(公告)号：US08890288B2
公开(公告)日：2014-11-18
申请号：US13270452
申请日：2011-10-11
申请人： Xiangdong Chen , Henry Kuo-Shun Chen
发明人： Xiangdong Chen , Henry Kuo-Shun Chen
IPC分类号： H01L21/02 , H01L23/522 , H01L27/06 , H01L49/02
CPC分类号： H01L28/86 , H01L23/5223 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： According to one exemplary embodiment, a metal-oxide-metal (MOM) capacitor in a semiconductor die comprises a first plurality of capacitor plates and a second plurality of capacitor plates sharing a plane parallel to and below a plane of a first metallization layer of the semiconductor die. The MOM capacitor further comprises a local interlayer dielectric between the first plurality of capacitor plates and the second plurality of capacitor plates. The first and second plurality of capacitor plates are made from a local interconnect metal for connecting devices formed in a device layer of the semiconductor die situated below the first metallization layer.
摘要翻译：根据一个示例性实施例，半导体管芯中的金属氧化物金属（MOM）电容器包括第一多个电容器板和第二多个电容器板，第二多个电容器板共享平行于第一金属化层半导体芯片。 MOM电容器还包括在第一多个电容器板和第二多个电容器板之间的局部层间电介质。第一和第二多个电容器板由局部互连金属制成，用于连接形成在位于第一金属化层下方的半导体管芯的器件层中的器件。

56. 发明授权

US08866258B2 Interposer structure with passive component and method for fabricating same 有权
标题翻译：具有无源元件的内插器结构及其制造方法
公开(公告)号：US08866258B2
公开(公告)日：2014-10-21
申请号：US12587482
申请日：2009-10-06
申请人： Wei Xia , Xiangdong Chen , Akira Ito
发明人： Wei Xia , Xiangdong Chen , Akira Ito
IPC分类号： H01L27/08 , H01L23/498 , H01L21/768 , H01L21/48 , H01L23/14
CPC分类号： H01L23/49827 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L23/49822 , H01L2223/6677 , H01L2224/16225 , H01L2924/15311
摘要： According to an exemplary embodiment, an interposer structure for electrically coupling a semiconductor die to a support substrate in a semiconductor package includes at least one through-wafer via extending through a semiconductor substrate, where the at least one through-wafer via provides an electrical connection between the semiconductor die and the support substrate. The interposer structure further includes a passive component including a trench conductor, where the trench conductor extends through the semiconductor substrate. The passive component further includes a dielectric liner situated between the trench conductor and the semiconductor substrate. The passive component can further include at least one conductive pad for electrically coupling the trench conductor to the semiconductor die. The passive component can be, for example, an inductor or an antenna.
摘要翻译：根据示例性实施例，用于将半导体管芯电耦合到半导体封装中的支撑衬底的插入器结构包括延伸穿过半导体衬底的至少一个贯通晶片，其中至少一个贯通晶片通孔提供电连接在半导体管芯和支撑衬底之间。插入器结构还包括无源部件，其包括沟槽导体，其中沟槽导体延伸穿过半导体衬底。无源部件还包括位于沟槽导体和半导体衬底之间的电介质衬垫。无源部件还可以包括至少一个用于将沟槽导体电耦合到半导体管芯的导电焊盘。无源部件可以是例如电感器或天线。

57. 发明授权

US08853746B2 CMOS devices with stressed channel regions, and methods for fabricating the same 有权
标题翻译：具有应力沟道区的CMOS器件及其制造方法
公开(公告)号：US08853746B2
公开(公告)日：2014-10-07
申请号：US11427495
申请日：2006-06-29
申请人： Xiangdong Chen , Thomas W. Dyer , Kenneth Settlemyer , Haining S. Yang
发明人： Xiangdong Chen , Thomas W. Dyer , Kenneth Settlemyer , Haining S. Yang
IPC分类号： H01L29/76 , H01L27/148 , H01L29/66 , H01L29/165 , H01L29/786 , H01L29/78 , H01L27/12 , H01L21/84 , H01L29/04 , H01L29/10 , H01L21/762 , H01L21/8238
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/30604 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/045 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/78 , H01L29/78684 , H01L29/78696
摘要： The present invention relates to improved complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.
摘要翻译：本发明涉及具有应力通道区域的改进的互补金属氧化物半导体（CMOS）器件。具体地，每个改进的CMOS器件包括具有位于半导体器件结构中的沟道区的场效应晶体管（FET），其具有沿着第一组等效晶面中的一个取向的顶表面和沿着第二，不同组的等效晶面。这种附加表面可以通过晶体蚀刻容易地形成。此外，具有固有压缩或拉伸应力的一个或多个应力层位于半导体器件结构的附加表面上，并且被布置和构造成将拉应力或压应力施加到FET的沟道区。这种应力层可以通过具有与半导体器件结构不同的晶格常数的半导体材料的假晶生长来形成。

58. 发明授权

US08836032B2 Fin-based adjustable resistor 有权
标题翻译：鳍式可调电阻
公开(公告)号：US08836032B2
公开(公告)日：2014-09-16
申请号：US13277547
申请日：2011-10-20
申请人： Wei Xia , Xiangdong Chen
发明人： Wei Xia , Xiangdong Chen
IPC分类号： H01L27/12 , H01L29/78
CPC分类号： H01L29/785 , H01L2029/7857
摘要： According to one exemplary embodiment, a fin-based adjustable resistor includes a fin channel of a first conductivity type, and a gate surrounding the fin channel. The fin-based adjustable resistor also includes first and second terminals of the first conductivity type being contiguous with the fin channel, and being situated on opposite sides of the fin channel. The fin channel is lower doped relative to the first and second terminals. The resistance of the fin channel between the first and second terminals is adjusted by varying a voltage applied to the gate so as to achieve the fin-based adjustable resistor. The gate can be on at least two sides of the fin channel. Upon application of a depletion voltage, the fin channel can be depleted before an inversion is formed in the fin channel.
摘要翻译：根据一个示例性实施例，鳍状可调电阻器包括第一导电类型的鳍状沟道和围绕鳍状沟道的栅极。鳍状可调电阻器还包括第一导电类型的第一和第二端子，其与鳍状通道邻接并位于翅片通道的相对侧上。翅片通道相对于第一和第二端子较低掺杂。通过改变施加到栅极的电压来调节第一和第二端子之间的鳍状通道的电阻，从而实现基于鳍片的可调电阻器。门可以在鳍通道的至少两侧。在施加耗尽电压时，在鳍式通道中形成反转之前，可以耗尽鳍通道。

59. 发明授权

US08791533B2 Semiconductor package having an interposer configured for magnetic signaling 有权
标题翻译：具有配置用于磁信令的插入器的半导体封装
公开(公告)号：US08791533B2
公开(公告)日：2014-07-29
申请号：US13361598
申请日：2012-01-30
申请人： Xiangdong Chen , Sam Ziqun Zhao , Kevin Kunzhong Hu , Sampath K. V. Karikalan , Rezaur Rahman Khan , Pieter Vorenkamp
发明人： Xiangdong Chen , Sam Ziqun Zhao , Kevin Kunzhong Hu , Sampath K. V. Karikalan , Rezaur Rahman Khan , Pieter Vorenkamp
IPC分类号： H01L29/82
CPC分类号： H01L23/48 , H01L23/49827 , H01L25/0655 , H01L2225/06531 , H01L2924/0002 , H01L2924/00
摘要： There are disclosed herein various implementations of semiconductor packages having an interposer configured for magnetic signaling. One exemplary implementation includes a die transmit pad in an active die for transmitting a magnetic signal corresponding to a die electrical signal produced by the active die, and an interposer magnetic tunnel junction (MTJ) pad in the interposer for receiving the magnetic signal. A sensing circuit is coupled to the interposer MTJ pad for producing a receive electrical signal corresponding to the magnetic signal. In one implementation, the sensing circuit is configured to sense a resistance of the interposer MTJ pad and to produce the receive electrical signal according to the sensed resistance.
摘要翻译：这里公开了具有配置用于磁信令的插入器的半导体封装的各种实施方式。一个示例性实施例包括用于传输对应于由有源管芯产生的管芯电信号的磁信号的有源管芯中的管芯发射焊盘以及用于接收磁信号的插入器磁隧道结（MTJ）焊盘。感测电路耦合到插入器MTJ焊盘，用于产生对应于磁信号的接收电信号。在一个实现中，感测电路被配置为感测插入器MTJ焊盘的电阻并且根据所感测的电阻产生接收电信号。

60. 发明申请

US20130193996A1 Semiconductor Package with Improved Testability 有权
标题翻译：具有提高可测性的半导体封装
公开(公告)号：US20130193996A1
公开(公告)日：2013-08-01
申请号：US13362344
申请日：2012-01-31
申请人： Sam Ziqun Zhao , Kevin Kunzhong Hu , Sampath K.V. Karikalan , Rezaur Rahman Khan , Pieter Vorenkamp , Xiangdong Chen
发明人： Sam Ziqun Zhao , Kevin Kunzhong Hu , Sampath K.V. Karikalan , Rezaur Rahman Khan , Pieter Vorenkamp , Xiangdong Chen
IPC分类号： G01R31/26 , H01L23/544
CPC分类号： H01L22/32 , H01L21/561 , H01L23/3128 , H01L23/49811 , H01L23/49827 , H01L23/49833 , H01L24/16 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/97 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/1533 , H01L2924/15331 , H01L2224/81 , H01L2924/014
摘要： An exemplary implementation of the present disclosure includes a testable semiconductor package that includes an active die having interface contacts and dedicated testing contacts. An interposer is situated adjacent a bottom surface of the active die, the interposer providing electrical connections between the interface contacts and a bottom surface of the testable semiconductor package. At least one conductive medium provides electrical connection between at least one of the dedicated testing contacts and a top surface of the testable semiconductor package. The at least one conductive medium can be coupled to a package-top testing connection, which may include a solder ball.
摘要翻译：本公开的示例性实现包括可测试的半导体封装，其包括具有接口触点和专用测试触点的有源裸片。插入器位于有源裸片的底表面附近，插入器提供接口触点之间的电连接和可测试的半导体封装的底表面。至少一个导电介质提供至少一个专用测试触点和可测半导体封装的顶表面之间的电连接。所述至少一个导电介质可以耦合到封装顶部测试连接，其可以包括焊球。

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