专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US07478201B2 Data processing system, cache system and method for passively scrubbing a domain indication 失效
标题翻译：数据处理系统，缓存系统和被动清理域指示的方法
公开(公告)号：US07478201B2
公开(公告)日：2009-01-13
申请号：US11136652
申请日：2005-05-24
申请人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： Scrubbing logic in a local coherency domain issues a domain query request to at least one cache hierarchy in a remote coherency domain. The domain query request is a non-destructive probe of a coherency state associated with a target memory block by the at least one cache hierarchy. A coherency response to the domain query request is received. In response to the coherency response indicating that the target memory block is not cached in the remote coherency domain, a domain indication in the local coherency domain is updated to indicate that the target memory block is cached, if at all, only within the local coherency domain.
摘要翻译：本地一致性域中的擦除逻辑向远程一致性域中的至少一个缓存层次结构发出域查询请求。域查询请求是由至少一个高速缓存层次结构与目标存储器块相关联的一致性状态的非破坏性探测。接收到域查询请求的一致性响应。响应于指示目标存储器块未被缓存在远程一致性域中的相关性响应，本地一致性域中的域指示被更新以指示目标存储器块被缓存，如果完全只在本地一致性内域。

52. 发明授权

US07447845B2 Data processing system, processor and method of data processing in which local memory access requests are serviced by state machines with differing functionality 失效
标题翻译：数据处理系统，处理器和数据处理方法，其中本地存储器访问请求由具有不同功能的状态机服务
公开(公告)号：US07447845B2
公开(公告)日：2008-11-04
申请号：US11457333
申请日：2006-07-13
申请人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0817 , G06F12/1416
摘要： A data processing system includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array, at least one snoop machine that services memory access requests of a remote processor core, and multiple state machines that service memory access requests of the local processor core. The multiple state machines include a first state machine that has a first set of memory access requests of the local processor core that it is capable of servicing and a second state machine that has a different second set of memory access requests of the local processor core that it is capable of servicing.
摘要翻译：数据处理系统包括本地处理器核心和耦合到本地处理器核心的高速缓存存储器。高速缓冲存储器包括数据阵列，数据阵列的内容目录，至少一个服务于远程处理器核的存储器访问请求的窥探机器，以及服务于本地处理器核心的存储器访问请求的多个状态机。多状态机包括第一状态机，其具有能够服务的本地处理器核心的第一组存储器访问请求;以及第二状态机，其具有本地处理器核心的不同的第二组存储器访问请求，它能够维修。

53. 发明申请

US20080016278A1 Data Processing System, Processor and Method of Data Processing in which Local Memory Access Requests are Serviced on a Fixed Schedule 失效
标题翻译：数据处理系统，处理器和数据处理方法，其中本地存储器访问请求在固定时间表上服务
公开(公告)号：US20080016278A1
公开(公告)日：2008-01-17
申请号：US11457322
申请日：2006-07-13
申请人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/1425 , G06F12/0817 , G06F12/0897
摘要： A processing unit includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array. The cache memory further includes one or more state machines that service a first set of memory access requests, an arbiter that directs servicing of a second set of memory access requests by reference to the data array and the directory on a fixed schedule, address collision logic that protects memory access requests in the second set by detecting and signaling address conflicts between active memory access requests in the second set and subsequent memory access requests, and dispatch logic coupled to the address collision logic. The dispatch logic dispatches memory access requests in the first set to the one or more state machines for servicing and signals the arbiter to direct servicing of memory access requests in the second set according to the fixed schedule.
摘要翻译：处理单元包括本地处理器核心和耦合到本地处理器核心的高速缓存存储器。高速缓冲存储器包括数据阵列，数据阵列的内容目录。缓存存储器还包括服务于第一组存储器访问请求的一个或多个状态机，通过参考数据阵列和固定时间表上的目录来指导第二组存储器访问请求的服务的仲裁器，地址冲突逻辑其通过检测和发出第二组中的活动存储器访问请求与后续存储器访问请求之间的地址冲突以及耦合到地址冲突逻辑的调度逻辑来保护第二组中的存储器访问请求。调度逻辑将第一组中的存储器访问请求分派到一个或多个状态机用于服务，并且向仲裁器发出信号，以根据固定的时间表对第二组中的存储器访问请求进行直接服务。

54. 发明授权

US09189403B2 Selective cache-to-cache lateral castouts 有权
标题翻译：选择性高速缓存到缓存横向转义
公开(公告)号：US09189403B2
公开(公告)日：2015-11-17
申请号：US12650018
申请日：2009-12-30
申请人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams , Thomas R. Puzak
发明人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams , Thomas R. Puzak
IPC分类号： G06F12/00 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0811 , G06F12/12
摘要： A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be castout from the first lower level cache is selected, and the first lower level cache selects between performing a lateral castout (LCO) of the victim cache line to the second lower level cache and a castout of the victim cache line to the system memory based upon a confidence indicator associated with the victim cache line. In response to selecting an LCO, the first processing unit issues an LCO command on the interconnect fabric and removes the victim cache line from the first lower level cache, and the second lower level cache holds the victim cache line.
摘要翻译：数据处理系统包括第一和第二处理单元和系统存储器。第一处理单元具有第一上层和第一下层高速缓存，第二处理单元具有第二上层和下层高速缓存。响应于数据请求，选择要从第一较低级高速缓存丢弃的受害者高速缓存行，并且第一较低级高速缓存选择在执行到第二低级高速缓存的受害者高速缓存行的横向流出（LCO）基于与受害者高速缓存行相关联的置信指示，将受害者缓存行的丢弃发送到系统存储器。响应于选择LCO，第一处理单元在互连结构上发布LCO命令，并从第一低级缓存中移除受害者高速缓存行，并且第二下级缓存保存受害缓存行。

55. 发明授权

US08874852B2 Data cache block deallocate requests in a multi-level cache hierarchy 有权
标题翻译：数据缓存块在多级缓存层次结构中释放请求
公开(公告)号：US08874852B2
公开(公告)日：2014-10-28
申请号：US13433048
申请日：2012-03-28
申请人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
发明人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0804 , G06F12/121 , G06F12/122 , G06F12/126
摘要： In response to executing a deallocate instruction, a deallocation request specifying a target address of a target cache line is sent from a processor core to a lower level cache. In response, a determination is made if the target address hits in the lower level cache. If so, the target cache line is retained in a data array of the lower level cache, and a replacement order field of the lower level cache is updated such that the target cache line is more likely to be evicted in response to a subsequent cache miss in a congruence class including the target cache line. In response to the subsequent cache miss, the target cache line is cast out to the lower level cache with an indication that the target cache line was a target of a previous deallocation request of the processor core.
摘要翻译：响应于执行取消分配指令，将指定目标高速缓存行的目标地址的解除分配请求从处理器核发送到较低级高速缓存。作为响应，确定目标地址是否在较低级别高速缓存中。如果是这样，则目标高速缓存行被保留在较低级高速缓存的数据阵列中，并且更新较低级高速缓存的替换顺序字段，使得目标高速缓存行更可能响应于后续高速缓存未命中而被驱逐在包含目标缓存行的同余类中。响应于随后的高速缓存未命中，目标高速缓存行被推出到较低级缓存，指示目标高速缓存行是处理器核心的先前释放请求的目标。

56. 发明申请

US20130262777A1 DATA CACHE BLOCK DEALLOCATE REQUESTS 有权
标题翻译：数据缓存块解析请求
公开(公告)号：US20130262777A1
公开(公告)日：2013-10-03
申请号：US13433022
申请日：2012-03-28
申请人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
发明人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/12
CPC分类号： G06F12/0815 , G06F12/0804 , G06F12/0817 , G06F12/0897 , G06F12/126
摘要： A data processing system includes a processor core supported by upper and lower level caches. In response to executing a deallocate instruction in the processor core, a deallocation request is sent from the processor core to the lower level cache, the deallocation request specifying a target address associated with a target cache line. In response to receipt of the deallocation request at the lower level cache, a determination is made if the target address hits in the lower level cache. In response to determining that the target address hits in the lower level cache, the target cache line is retained in a data array of the lower level cache and a replacement order field in a directory of the lower level cache is updated such that the target cache line is more likely to be evicted from the lower level cache in response to a subsequent cache miss.
摘要翻译：数据处理系统包括由上层和下层高速缓存支持的处理器核心。响应于在处理器核心中执行取消分配指令，从处理器核心向下级高速缓存发送解除分配请求，所述释放请求指定与目标高速缓存行相关联的目标地址。响应于在较低级别高速缓存处接收到解除分配请求，确定目标地址是否在较低级别高速缓存中。为了响应于确定目标地址在较低级别高速缓存中的命中，目标高速缓存行被保留在较低级别高速缓存的数据阵列中，并且更新下级高速缓存的目录中的替换顺序字段，使得目标高速缓存线路可能会响应于后续的高速缓存未命中而从较低级别的缓存中逐出。

57. 发明授权

US08504779B2 Memory coherence directory supporting remotely sourced requests of nodal scope 失效
标题翻译：内存一致性目录支持远程请求节点范围
公开(公告)号：US08504779B2
公开(公告)日：2013-08-06
申请号：US13445010
申请日：2012-04-12
申请人： Paul A. Ganfield , Guy L. Guthrie , David J. Krolak , Michael S. Siegel , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
发明人： Paul A. Ganfield , Guy L. Guthrie , David J. Krolak , Michael S. Siegel , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/0817
摘要： A data processing system includes at least a first through third processing nodes coupled by an interconnect fabric. The first processing node includes a master, a plurality of snoopers capable of participating in interconnect operations, and a node interface that receives a request of the master and transmits the request of the master to the second processing unit with a nodal scope of transmission limited to the second processing node. The second processing node includes a node interface having a directory. The node interface of the second processing node permits the request to proceed with the nodal scope of transmission if the directory does not indicate that a target memory block of the request is cached other than in the second processing node and prevents the request from succeeding if the directory indicates that the target memory block of the request is cached other than in the second processing node.
摘要翻译：数据处理系统至少包括通过互连结构耦合的第一至第三处理节点。第一处理节点包括主机，能够参与互连操作的多个侦听器，以及接收主机请求的节点接口，并将主机的请求传送到第二处理单元，传送范围限于第二处理节点。第二处理节点包括具有目录的节点接口。第二处理节点的节点接口允许请求继续进行节点传输范围，如果该目录没有指示该请求的目标存储器块不是在第二处理节点中被缓存，并且如果该请求成功目录指示除第二处理节点之外的请求的目标存储块被缓存。

58. 发明授权

US08499124B2 Handling castout cache lines in a victim cache 失效
标题翻译：在受害者缓存中处理castout缓存行
公开(公告)号：US08499124B2
公开(公告)日：2013-07-30
申请号：US12336048
申请日：2008-12-16
申请人： Guy L. Guthrie , Alvan W. Ng , Michael S. Siegel , William J. Starke , Derek E. Williams , Phillip G. Williams
发明人： Guy L. Guthrie , Alvan W. Ng , Michael S. Siegel , William J. Starke , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F12/0811 , G06F12/0862
摘要： A victim cache memory includes a cache array, a cache directory of contents of the cache array, and a cache controller that controls operation of the victim cache memory. The cache controller, responsive to receiving a castout command identifying a victim cache line castout from another cache memory, causes the victim cache line to be held in the cache array. If the other cache memory is a higher level cache in the cache hierarchy of the processor core, the cache controller marks the victim cache line in the cache directory so that it is less likely to be evicted by a replacement policy of the victim cache, and otherwise, marks the victim cache line in the cache directory so that it is more likely to be evicted by the replacement policy of the victim cache.
摘要翻译：受害者缓存存储器包括缓存阵列，高速缓存阵列的内容的高速缓存目录以及控制受害者缓存存储器的操作的高速缓存控制器。高速缓存控制器响应于从另一高速缓冲存储器接收识别受害者高速缓存线路突发的丢弃命令，使受害者高速缓存行保持在高速缓存阵列中。如果其他高速缓冲存储器是处理器核心的高速缓存层级中的较高级缓存，则高速缓存控制器将高速缓存目录中的受害者高速缓存行标记为不太可能被受害缓存的替换策略驱逐，否则，将缓存目录中的受害者缓存行标记为更有可能被受害者缓存的替换策略驱逐。

59. 发明授权

US08327074B2 Synchronizing access to data in shared memory via upper level cache queuing 失效
标题翻译：通过高级缓存排队同步访问共享内存中的数据
公开(公告)号：US08327074B2
公开(公告)日：2012-12-04
申请号：US13445080
申请日：2012-04-12
申请人： Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3834
摘要： A processing unit includes a store-in lower level cache having reservation logic that determines presence or absence of a reservation and a processor core including a store-through upper level cache, an instruction execution unit, a load unit that, responsive to a hit in the upper level cache on a load-reserve operation generated through execution of a load-reserve instruction by the instruction execution unit, temporarily buffers a load target address of the load-reserve operation, and a flag indicating that the load-reserve operation bound to a value in the upper level cache. If a storage-modifying operation is received that conflicts with the load target address of the load-reserve operation, the processor core sets the flag to a particular state, and, responsive to execution of a store-conditional instruction, transmits an associated store-conditional operation to the lower level cache with a fail indication if the flag is set to the particular state.
摘要翻译：处理单元包括具有确定存在或不存在预留的预约逻辑的存储下位缓存和包括存储通过上级缓存，指令执行单元，负载单元的处理器核心，该负载单元响应于由指令执行单元通过执行装载预约指令而产生的加载备用操作的上级缓存暂时缓冲加载备用操作的加载目标地址，以及指示载入预约操作被绑定到上级缓存中的值。如果接收到与加载保留操作的加载目标地址冲突的存储修改操作，则处理器核心将该标志设置为特定状态，并且响应于执行存储条件指令，发送关联的存储 - 如果该标志被设置为特定状态，则向低级缓存进行条件操作，并显示故障指示。

60. 发明申请

US20120198167A1 SYNCHRONIZING ACCESS TO DATA IN SHARED MEMORY VIA UPPER LEVEL CACHE QUEUING 失效
标题翻译：通过上级缓存队列同步访问共享存储器中的数据
公开(公告)号：US20120198167A1
公开(公告)日：2012-08-02
申请号：US13445080
申请日：2012-04-12
申请人： Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3834
摘要： A processing unit includes a store-in lower level cache having reservation logic that determines presence or absence of a reservation and a processor core including a store-through upper level cache, an instruction execution unit, a load unit that, responsive to a hit in the upper level cache on a load-reserve operation generated through execution of a load-reserve instruction by the instruction execution unit, temporarily buffers a load target address of the load-reserve operation, and a flag indicating that the load-reserve operation bound to a value in the upper level cache. If a storage-modifying operation is received that conflicts with the load target address of the load-reserve operation, the processor core sets the flag to a particular state, and, responsive to execution of a store-conditional instruction, transmits an associated store-conditional operation to the lower level cache with a fail indication if the flag is set to the particular state.
摘要翻译：处理单元包括具有确定存在或不存在预留的预约逻辑的存储下位缓存和包括存储通过上级缓存，指令执行单元，负载单元的处理器核心，该负载单元响应于由指令执行单元通过执行装载预约指令而产生的加载备用操作的上级缓存暂时缓冲加载备用操作的加载目标地址，以及指示载入预约操作被绑定到上级缓存中的值。如果接收到与加载保留操作的加载目标地址冲突的存储修改操作，则处理器核心将该标志设置为特定状态，并且响应于执行存储条件指令，发送关联的存储 - 如果该标志被设置为特定状态，则向低级缓存进行条件操作，并显示故障指示。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式