专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US09430015B2 Method and system for setting power supply mode of a multiple-core processor system based on condition of a time bin during a number of time intervals within the time bin is equal to or larger than a second threshold 有权
标题翻译：基于时间段内的多个时间间隔内的基于时间段的条件设定多核处理器系统的供电方式的方法和系统等于或大于第二阈值
公开(公告)号：US09430015B2
公开(公告)日：2016-08-30
申请号：US13654863
申请日：2012-10-18
申请人： FUJITSU LIMITED
发明人： Takahisa Suzuki , Koichiro Yamashita , Hiromasa Yamauchi , Koji Kurihara
IPC分类号： G06F1/00 , G06F1/32 , G06F11/34 , H04W52/02
CPC分类号： G06F1/3203 , G06F1/3284 , G06F1/3287 , G06F11/3423 , G06F2201/81 , H04W52/028 , Y02D10/126 , Y02D10/171
摘要： A multiple-core processor system includes a memory unit storing the number of time intervals within a time bin, a time interval being a time interval between two consecutive operations; and a processor configured to: update the number of time intervals, specify a time stretch during which the number of time intervals stays above a threshold, and set, based on the number of time intervals, a power supply mode in which the multiple-core processor is supplied with power.
摘要翻译：多核处理器系统包括：存储单元，存储时间段内的时间间隔数;时间间隔;两个连续操作之间的时间间隔; 以及处理器，其被配置为：更新所述时间间隔的数量，指定所述时间间隔数保持在阈值以上的时间延长，并且基于所述时间间隔的数量来设定所述多个核心处理器供电。

52. 发明授权

US09219636B2 Data sharing system, terminal, and data sharing method 有权
标题翻译：数据共享系统，终端和数据共享方法
公开(公告)号：US09219636B2
公开(公告)日：2015-12-22
申请号：US13801783
申请日：2013-03-13
申请人： FUJITSU LIMITED
发明人： Hiromasa Yamauchi , Koichiro Yamashita , Takahisa Suzuki , Koji Kurihara
IPC分类号： G06F15/16 , H04L29/08 , G06F13/00
CPC分类号： H04L29/08522 , G06F13/00 , G06F13/4265 , H04L67/1091 , Y02D10/14 , Y02D10/151
摘要： A data sharing system includes communicable terminals and selects a server-client system in which a first terminal is designated as a server and other terminals are designated as clients, when a sum of estimated time for transferring data to the first terminal from the other terminals, estimated time for performing, by the first terminal, arithmetic processing of the data in the first terminal, and estimated time for transferring arithmetically processed data from the first terminal to the other terminals satisfies a real time restriction, and power estimated to be consumed at a time of performing, by the first terminal, the arithmetic processing of the data in the first terminal is less than power estimated to be consumed at a time of performing the arithmetic processing by the other terminals. The data sharing system selects a peer-to-peer system, when the sum does not satisfy the real time restriction in any terminal.
摘要翻译：数据共享系统包括可通信终端，并且当从其他终端传送数据到第一终端的估计时间的总和时，选择其中将第一终端指定为服务器并且其他终端被指定为客户端的服务器 - 客户端系统，由第一终端执行第一终端中的数据的算术处理以及从第一终端向其他终端传送算术处理数据的估计时间的估计时间满足实时限制，并且估计在一由第一终端执行第一终端中的数据的算术处理的时间小于在其他终端执行算术处理时估计消耗的功率。当总和不满足任何终端的实时限制时，数据共享系统选择对等系统。

53. 发明授权

US09218201B2 Multicore system and activating method 有权
标题翻译：多核系统和激活方法
公开(公告)号：US09218201B2
公开(公告)日：2015-12-22
申请号：US13622536
申请日：2012-09-19
申请人： FUJITSU LIMITED
发明人： Koichiro Yamashita , Hiromasa Yamauchi
IPC分类号： G06F9/50 , G06F9/46 , G06F9/48 , G06F9/52
CPC分类号： G06F9/4881 , G06F9/505 , G06F9/52
摘要： A multicore system includes multiple processor cores; a scheduler in each of the processor cores and allocating a process to the processor cores when having a master authority that is an authority to assign processes; and a master controller performing control to repeat until a process to be executed no longer exists, a cycle in which the schedulers transfer the master authority to another processor core after receiving the master authority and before assigning a process to the processor cores, discards the master authority after assigning the process to the processor cores, and enters a state of waiting to receive the master authority.
摘要翻译：多核系统包括多个处理器内核; 每个处理器核心中的调度器，并且当具有作为分配进程的权限的主控制器时，向处理器核心分配进程; 执行控制的主控制器，直到执行的处理不再存在为止，其中调度器在接收到主管理机构之后并且在向处理器核心分配处理之前将主控制器传送到另一个处理器核心的周期，丢弃主设备将进程分配给处理器核心，并进入等待接收主机的状态。

54. 发明授权

US09189359B2 Computer product, control apparatus, and control method 有权
标题翻译：计算机产品，控制装置和控制方法
公开(公告)号：US09189359B2
公开(公告)日：2015-11-17
申请号：US13759435
申请日：2013-02-05
申请人： FUJITSU LIMITED
发明人： Hiromasa Yamauchi , Koichiro Yamashita , Takahisa Suzuki , Koji Kurihara
IPC分类号： G06F1/26 , G06F1/32 , G06F11/30 , G06F9/44 , G06F9/48 , G06F9/50 , G06F9/46
CPC分类号： G06F11/3058 , G06F1/26 , G06F1/3203 , G06F1/329 , G06F9/44 , G06F9/461 , G06F9/4856 , G06F9/4893 , G06F9/5094 , Y02D10/24
摘要： A computer-readable recording medium stores a control program causing a processor of a first terminal to execute a process that includes detecting that a remaining battery level of the first terminal has become less than or equal to a first threshold while a task is under execution by the first terminal; suspending execution of the task upon detecting that the remaining battery level of the first terminal has become less than or equal to the first threshold; transmitting identification information of the task to a second terminal upon detecting that the remaining battery level of the first terminal has become less than or equal to the first threshold; receiving from the second terminal and after transmitting the identification information of the task, information related to a potential of executing the task; and transmitting to the second terminal, information corresponding to the information related to the potential of executing the task.
摘要翻译：计算机可读记录介质存储使第一终端的处理器执行包括检测第一终端的剩余电池电量已经变得小于或等于第一阈值的处理的控制程序，而任务正在执行时由第一个终端; 在检测到第一终端的剩余电池电量已经变得小于或等于第一阈值的情况下暂停执行任务; 在检测到第一终端的剩余电池电平已经变得小于或等于第一阈值的情况下，将任务的识别信息发送到第二终端; 从所述第二终端接收并发送所述任务的识别信息之后，与执行所述任务的可能性相关的信息; 并向第二终端发送与执行任务的可能性相关的信息的信息。

55. 发明授权

US09189301B2 Data processing method and data processing system 有权
标题翻译：数据处理方法和数据处理系统
公开(公告)号：US09189301B2
公开(公告)日：2015-11-17
申请号：US14085141
申请日：2013-11-20
申请人： FUJITSU LIMITED
发明人： Takahisa Suzuki , Koichiro Yamashita , Hiromasa Yamauchi , Koji Kurihara , Toshiya Otomo , Naoki Odate
IPC分类号： G06F9/46 , G06F9/54 , G06F9/52
CPC分类号： G06F9/542 , G06F9/528
摘要： A data processing method executed by a first data processing apparatus and includes acquiring process information concerning a first process, in response to a process request for the first process; setting a first process flag included in the process information concerning the first process to indicate “true”; setting a first end flag of the process information concerning the first process to indicate “true” after executing the first process; acquiring process information concerning a second process that is to be executed before a third process that is to be executed subsequent the first process; and determining a process to be executed, based on a second process flag and a second end flag included in the process information concerning the second process.
摘要翻译：一种由第一数据处理装置执行的数据处理方法，包括响应于第一处理的处理请求而获取关于第一处理的处理信息; 设置关于第一处理的处理信息中包括的表示“真”的第一处理标志; 在执行第一处理之后，设置关于第一处理的处理信息的第一结束标志以指示“真”; 获取关于在第一处理之后执行的第三处理之前要执行的第二处理的处理信息; 以及基于包括在关于第二处理的处理信息中的第二处理标志和第二结束标志来确定要执行的处理。

56. 发明授权

US09141429B2 Multicore processor system, computer product, and control method 有权
标题翻译：多核处理器系统，计算机产品和控制方法
公开(公告)号：US09141429B2
公开(公告)日：2015-09-22
申请号：US13624353
申请日：2012-09-21
申请人： FUJITSU LIMITED
发明人： Hiromasa Yamauchi , Koichiro Yamashita , Kiyoshi Miyazaki , Hitoshi Ikeda
IPC分类号： G06F9/50 , G06F13/14 , G06F13/16 , G06F13/362
CPC分类号： G06F9/5027 , G06F13/1605 , G06F13/362 , G06F13/3625 , G06F2209/5021
摘要： A multicore processor system includes a core configured to detect a change in a state of assignment of a multicore processor; obtain, upon detecting the change in the state of assignment, number of accesses of a common resource shared by the multicore processor by each of process that are assigned to cores of the multicore processor; calculate an access ratio based on the obtained number of accesses; and notify an arbitration circuit of the calculated access ratio, the arbitration circuit arbitrating accesses of the common resource by the multicore processor.
摘要翻译：多核处理器系统包括被配置为检测多核处理器的分配状态的变化的核心; 在分配给所述多核处理器的核心的每个进程检测到所述分配状态的变化时，获取由所述多核处理器共享的共同资源的访问次数; 基于获得的访问次数计算访问比率; 并通知仲裁电路计算出的访问比率，仲裁电路通过多核处理器仲裁公用资源的访问。

57. 发明授权

US09110886B2 Data transfer control apparatus, data transfer control method, and computer product 有权
标题翻译：数据传输控制装置，数据传输控制方法和计算机产品
公开(公告)号：US09110886B2
公开(公告)日：2015-08-18
申请号：US13718302
申请日：2012-12-18
申请人： FUJITSU LIMITED
发明人： Hiromasa Yamauchi , Koichiro Yamashita , Takahisa Suzuki , Koji Kurihara
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F13/30
摘要： A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.
摘要翻译：数据传输控制装置包括：传送单元，其根据来自第一处理器的指令将数据从传送源存储器传送到传送目的地存储器; 以及第一处理器，被配置为基于所检测到的处理的类型来检测由所述第一处理器执行的处理，确定所述数据的传送是否紧急，并且基于所述第一处理器的控制来控制所述传送单元或所述第一处理器传送所述数据确定结果。

58. 发明申请

US20150220362A1 MULTI-CORE PROCESSOR SYSTEM, ELECTRICAL POWER CONTROL METHOD, AND COMPUTER PRODUCT FOR MIGRATING PROCESS FROM ONE CORE TO ANOTHER 审中-公开
标题翻译：多核处理器系统，电力控制方法以及从一个核心到另一个核心的移动过程的计算机产品
公开(公告)号：US20150220362A1
公开(公告)日：2015-08-06
申请号：US14689603
申请日：2015-04-17
申请人： FUJITSU LIMITED
发明人： Koji KURIHARA , Koichiro Yamashita , Kazumi Miyako
IPC分类号： G06F9/48 , G06F9/52
CPC分类号： G06F9/4881 , G06F9/5044 , G06F9/5094 , G06F9/52 , Y02D10/22
摘要： A multi-core processor system includes a core configured to detect that among cores different from a specific core executing a specific process, a given software different from specific software having a function equivalent to the specific process, is under execution; extract, from a database storing required computing capacities for the plural software and upon detecting that a given software is under execution, requirement values indicating the required computing capacity of the specific software and of the given software; judge for each the cores, whether a sum of the required computing capacities of the specific software and the software is at most a computing capacity value of the core; assign the specific software to a core for which the sum of the required computing capacities is judged to be at most the computing capacity value of the core; and suspend the specific core, upon assigning the specific software to the core.
摘要翻译：多核处理器系统包括被配置为检测在与执行特定处理的特定核心不同的核心之间的核心，正在执行与具有与特定进程相当的功能的特定软件不同的给定软件; 从存储多个软件的所需计算能力的数据库中提取，并且在检测到给定软件正在执行时，提供指示特定软件和给定软件所需的计算能力的需求值; 对每个核心进行判断，特定软件和软件所需的计算能力的总和是否至多为核心的计算能力值; 将特定软件分配给核心，所述核心将所需计算能力的总和判断为至多核心的计算能力值; 并将具体的软件分配给核心，暂停具体的核心。

59. 发明授权

US09015369B2 Data transferring apparatus and data transferring method 有权
标题翻译：数据传输装置和数据传输方法
公开(公告)号：US09015369B2
公开(公告)日：2015-04-21
申请号：US13624337
申请日：2012-09-21
申请人： Fujitsu Limited
发明人： Takahisa Suzuki , Koichiro Yamashita , Hiromasa Yamauchi , Koji Kurihara
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： A memory stores data generated by a processor and a transferring unit burst transfers the data from the memory unit to a processing unit. Based on an access capability of the processor when accessing the memory, a prescribed value for a burst width and information concerning the time that the processing unit consumes to process the data are set in advance at the data transferring apparatus. When the transferring unit performs data transfer, the time allowed for data transfer is calculated based on the information concerning the time that the processing unit consumes to process the data, and the burst width is determined as a value greater than or equal to the prescribed value for the burst width and is as close as possible to the prescribed value for the burst width within a range in which data transfer can be finished within the allowed time.
摘要翻译：存储器存储由处理器生成的数据和传送单元突发将数据从存储器单元传送到处理单元。基于访问存储器时的处理器的访问能力，在数据传送装置上预先设置突发宽度的规定值和处理单元消耗处理数据的时间的信息。当传送单元执行数据传送时，基于处理单元消耗处理数据的时间的信息来计算数据传送所需的时间，突发宽度被确定为大于或等于规定值的值对于突发宽度，并且在允许的时间内可以完成数据传送的范围内，对于突发宽度尽可能接近规定值。

60. 发明授权

US09015364B2 Data transfer control apparatus, data transfer control method, and computer product 有权
公开(公告)号：US09015364B2
公开(公告)日：2015-04-21
申请号：US13718302
申请日：2012-12-18
申请人： Fujitsu Limited
发明人： Hiromasa Yamauchi , Koichiro Yamashita , Takahisa Suzuki , Koji Kurihara
IPC分类号： G06F13/28
摘要： A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式