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51. 发明授权

US07913034B2 DRAM access command queuing 有权
标题翻译： DRAM访问命令排队
公开(公告)号：US07913034B2
公开(公告)日：2011-03-22
申请号：US11832220
申请日：2007-08-01
申请人： Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
发明人： Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing dead cycles. The arbiter first divides DRAM accesses into write accesses and read accesses. The access requests are divided into accesses per memory bank with a threshold limit imposed on the number of accesses to each memory bank. The write receive packets are rotated among the banks based on the write queue status. The status of the write queue for each memory bank may also be used for system flow control. The arbiter also typically includes the ability to determine access windows based on the status of the command queues, and to perform arbitration on each access window.
摘要翻译：访问仲裁器被用于将对DRAM存储器件，特别是快速循环DRAM中的各个存储体的读取和写入访问请求进行优先级排序。这用于通过避免对同一存储体的连续访问并且通过最小化死循环来优化用于读取和写入操作的存储器带宽。仲裁器首先将DRAM访问划分为写访问和读访问。访问请求被划分为每个存储体的访问，并且对每个存储体的访问次数施加了阈值限制。基于写入队列状态，写入接收数据包在存储体之间旋转。每个存储体的写入队列的状态也可以用于系统流控制。仲裁器还通常包括基于命令队列的状态来确定访问窗口的能力，并且在每个访问窗口上执行仲裁。

52. 发明申请

US20080298372A1 STRUCTURE AND METHOD FOR SCHEDULER PIPELINE DESIGN FOR HIERARCHICAL LINK SHARING 失效
标题翻译：用于分层链路共享的调度器管道设计的结构和方法
公开(公告)号：US20080298372A1
公开(公告)日：2008-12-04
申请号：US12175479
申请日：2008-07-18
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
IPC分类号： H04L12/56
CPC分类号： H04L47/60 , H04L47/15 , H04L47/50 , H04L47/52 , H04L49/90
摘要： A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.
摘要翻译：描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。该配置通过最小化外部SRAM存储器件的使用来降低成本。这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。

53. 发明授权

US07380065B2 Performance of a cache by detecting cache lines that have been reused 有权
标题翻译：通过检测已被重用的高速缓存行来执行缓存的性能
公开(公告)号：US07380065B2
公开(公告)日：2008-05-27
申请号：US11094399
申请日：2005-03-30
申请人： Gordon T. Davis , Santiago A. Leon , Hans-Werner Tast
发明人： Gordon T. Davis , Santiago A. Leon , Hans-Werner Tast
IPC分类号： G06F13/00
CPC分类号： G06F12/127
摘要： A method and system for improving the performance of a cache. The cache may include an array of tag entries where each tag entry includes an additional bit (“reused bit”) used to indicate whether its associated cache line has been reused, i.e., has been requested or referenced by the processor. By tracking whether a cache line has been reused, data (cache line) that may not be reused may be replaced with the new incoming cache line prior to replacing data (cache line) that may be reused. By replacing data in the cache memory that might not be reused prior to replacing data that might be reused, the cache hit may be improved thereby improving performance.
摘要翻译：一种用于提高缓存性能的方法和系统。高速缓存可以包括标签条目的阵列，其中每个标签条目包括用于指示其相关联的高速缓存行是否被重用，即被处理器请求或引用的附加位（“重用位”）。通过跟踪高速缓存行是否被重用，在替换可被重用的数据（高速缓存行）之前，可以用新的传入高速缓存行替换可能不被重用的数据（高速缓存行）。通过在替换可能被重用的数据之前替换高速缓冲存储器中可能不被重用的数据，可以提高高速缓存命中，从而提高性能。

54. 发明申请

US20080114964A1 Apparatus and Method for Cache Maintenance 审中-公开
标题翻译：缓存维护的设备和方法
公开(公告)号：US20080114964A1
公开(公告)日：2008-05-15
申请号：US11559512
申请日：2006-11-14
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F9/305
CPC分类号： G06F12/0893 , G06F9/3808 , G06F9/3844 , G06F12/0862
摘要： A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Control is exercised over which lines are contained within the cache. This invention avoids inefficiencies in the cache by removing trace lines experiencing early exits from the cache, or trace lines that are short, by maintaining a few bits of information about the accuracy of the control flow in a trace cache line and using that information in addition to the LRU (Least Recently Used) bits that maintain the recency information of a cache line, in order to make a replacement decision.
摘要翻译：单个统一的一级指令高速缓存，其中一些行可以包含跟踪和同一同余类中的其他行可以包含与常规高速缓存行一致的指令块。对缓存中包含哪些行进行控制。本发明通过在跟踪高速缓存行中维护关于控制流的准确度的几位信息并且使用该信息来避免高速缓存中的低效率，通过删除经历来自缓存的早期退出的跟踪线或短路的跟踪线到保持高速缓存行的新近度信息的LRU（最近使用的）位，以便进行替换判定。

55. 发明授权

US5459843A RISC-type pipeline processor having N slower execution units operating in parallel interleaved and phase offset manner with a faster fetch unit and a faster decoder 失效
标题翻译：具有N个较慢执行单元的RISC型流水线处理器以并行交错和相位偏移方式工作，具有更快的提取单元和更快的解码器
公开(公告)号：US5459843A
公开(公告)日：1995-10-17
申请号：US282412
申请日：1994-07-28
申请人： Gordon T. Davis , Sebastian T. Ventrone , John J. Reilly , Baiju D. Mandalia , Michael G. Holung , William R. Robinson, Jr.
发明人： Gordon T. Davis , Sebastian T. Ventrone , John J. Reilly , Baiju D. Mandalia , Michael G. Holung , William R. Robinson, Jr.
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3885 , G06F9/3851
摘要： A pipelined, RISC-type processor operated in parallel mode and its associated processing methods for separately handling instructions from multiple program instruction sets. The pipelined processor includes an instruction fetch unit, an instruction decode unit and n execution units. Each execution unit operates at substantially the same process cycle time, while the speed of operation of the instruction fetch unit and instruction decode unit is at least n times the cycle time of the execution units such that each phase of the pipeline separately processes n instructions substantially within one machine cycle. Timing and control circuitry is coupled to each of the principle elemental units for controlling the timing and sequence of operations on instructions.
摘要翻译：以并行模式运行的流水线RISC型处理器及其相关处理方法，用于分别处理来自多个程序指令集的指令。流水线处理器包括指令提取单元，指令解码单元和n个执行单元。每个执行单元以基本上相同的处理周期时间操作，而指令获取单元和指令解码单元的操作速度至少为执行单元的周期时间的n倍，使得流水线的每个相分别基本上处理n个指令在一个机器周期内。定时和控制电路耦合到每个主要元件单元，用于控制指令上的操作的时序和顺序。

56. 发明授权

US5010476A Time multiplexed system for tightly coupling pipelined processors to separate shared instruction and data storage units 失效
标题翻译：时间复用系统，用于紧密耦合流水线处理器以分离共享指令和数据存储单元
公开(公告)号：US5010476A
公开(公告)日：1991-04-23
申请号：US876625
申请日：1986-06-20
申请人： Gordon T. Davis
发明人： Gordon T. Davis
IPC分类号： G06F15/167 , G06F12/00 , G06F13/16 , G06F13/18
CPC分类号： G06F9/3885 , G06F13/1663 , G06F9/3867
摘要： This invention speeds up the execution of instructions in an information processing system by tightly coupling two or more processors to a random access storage mechanism in such a manner that no arbitration is required and no processor is forced to wait while another processor accesses the storage mechanism. This is accomplished by coupling the processors to the storage mechanism in a time multiplexed manner which enables each processor to have a periodic regularly occurring turn at accessing the storage mechanism.
摘要翻译：本发明通过将两个或更多个处理器紧密地耦合到随机存取存储机制来加速信息处理系统中的指令的执行，使得不需要仲裁并且在另一个处理器访问存储机制时不强制处理器等待。这通过以时间复用方式将处理器耦合到存储机构来实现，这使得每个处理器能够在访问存储机制时具有周期性的定期发生的转弯。

57. 发明授权

US4972342A Programmable priority branch circuit 失效
标题翻译：可编程优先支路
公开(公告)号：US4972342A
公开(公告)日：1990-11-20
申请号：US254985
申请日：1988-10-07
申请人： Gordon T. Davis , Baiju D. Mandalia
发明人： Gordon T. Davis , Baiju D. Mandalia
IPC分类号： G06F9/32 , G06F9/38 , G06F9/48
CPC分类号： G06F9/3885 , G06F9/30058 , G06F9/30094 , G06F9/3804
摘要： A special purpose circuit unit, responsive to a special BBD instruction, provides for more efficient execution of program branches required in poll and test type routines used by data processors. This unit can easily be added to almost any contemporary processing system to speed up performance of priority branch operations. It includes: a stack of registers loadable with branch addresses designating locations of branch target instructions, an input register for holding bits representing branch conditions accessible from immediate (programmable) storage, and a programmable priority encoder responsive to the BBD instruction to select an address from the stack in accordance with the position in the input register of a highest priority one of the bits representing an active request for instruction branching. The selected address is used to fetch an instruction representing the start of a program segment for attending to the selected branch condition. Contents of the branch address stack are alterable by program to allow for varying selections of branch routines to fulfill conditions denotable by different sets of bits loadable into the input register. The priority encoder includes a stack of selection control registers which are also loadable by programs, to allow for variability in the priority ordering accorded to the bit positions of the input register. By dynamically loading information into the branch address and priority selection stacks, subject BBD unit can be shared dynamically for resolving sequence branching relative to multiple different classes of conditions or events depending on system requirements. The unit is configurable to execute its priority and branch address selection operations together in a single clock cycle of the system. In pipelined systems, the BBD function can be conveniently accommodated in parallel with other system functions.

58. 发明授权

US07934081B2 Apparatus and method for using branch prediction heuristics for determination of trace formation readiness 失效
标题翻译：使用分支预测启发式方法确定痕量形成准备的装置和方法
公开(公告)号：US07934081B2
公开(公告)日：2011-04-26
申请号：US11538831
申请日：2006-10-05
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F9/40 , G06F12/08
CPC分类号： G06F12/0862 , G06F12/0875 , G06F2212/6028
摘要： A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.
摘要翻译：单个统一的一级指令高速缓存，其中一些行可以包含跟踪和同一同余类中的其他行可以包含与常规高速缓存行一致的指令块。缓存中的跟踪行的形成在系统的初始操作中被延迟，以确保存储的跟踪线的质量。

59. 发明授权

US07929438B2 Scheduler pipeline design for hierarchical link sharing 失效
标题翻译：调度器管道设计用于分层链路共享
公开(公告)号：US07929438B2
公开(公告)日：2011-04-19
申请号：US12175479
申请日：2008-07-18
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
IPC分类号： H04J1/16
CPC分类号： H04L47/60 , H04L47/15 , H04L47/50 , H04L47/52 , H04L49/90
摘要： A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.
摘要翻译：描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。该配置通过最小化外部SRAM存储器件的使用来降低成本。这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。

60. 发明授权

US07855966B2 Network congestion detection and automatic fallback: methods, systems and program products 失效
标题翻译：网络拥塞检测和自动回退：方法，系统和程序产品
公开(公告)号：US07855966B2
公开(公告)日：2010-12-21
申请号：US11348417
申请日：2006-02-07
申请人： Youssef Abdelilah , Gordon T. Davis , Jeffrey H. Derby , Dongming Hwang , Clark D. Jeffries , Malcolm S. Ware , Hua Ye
发明人： Youssef Abdelilah , Gordon T. Davis , Jeffrey H. Derby , Dongming Hwang , Clark D. Jeffries , Malcolm S. Ware , Hua Ye
IPC分类号： H04L12/26
CPC分类号： H04L47/10 , H04L12/6418 , H04L29/06027 , H04L47/12 , H04L47/2425 , H04L47/263 , H04L47/70 , H04L47/745 , H04L47/748 , H04L47/762 , H04L65/1009 , H04L65/607 , H04L65/80 , H04L2012/6481 , H04L2012/6497
摘要： A codec detects congestion in a packet network and responds via a session control protocol to re-negotiate codec-type and/or parameters with the receiving codec to reduce bit rate for supporting a session. Once the connection and session are established, encoded packets start flowing between the two codecs. A control entity sends and receives network congestion control packets periodically in the session. The congestion control packets provide a “heartbeat” signal to the receiving codec. When the network is not congested, all “heartbeat” packets will be passed through the network. As network congestion increases, routers within the network discard excess packets to prevent network failure. The codecs respond to the missing packets by slowing down the bit rate or proceeding to renegotiate a lower bit rate via the session control protocol. If there are no missing packets, the codecs detect if the session is operating at the highest bit rate, and if not, re-negotiate a higher bit rate.
摘要翻译：编解码器检测分组网络中的拥塞，并通过会话控制协议进行响应，以使用接收编解码器重新协商编解码器类型和/或参数，以减少支持会话的比特率。一旦建立了连接和会话，编码的数据包将在两个编解码器之间开始流动。控制实体在会话中定期发送和接收网络拥塞控制报文。拥塞控制分组向接收编解码器提供“心跳”信号。当网络不拥塞时，所有“心跳”数据包将通过网络传递。随着网络拥塞的增加，网络内的路由器丢弃多余的数据包，防止网络故障。编解码器通过减慢比特率或通过会话控制协议进行重新协商较低的比特率来响应丢失的分组。如果没有丢失数据包，则编解码器检测会话是否以最高比特率运行，如果不是，则重新协商更高的比特率。

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