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51. 发明授权

US06278636B1 Nonvolatile semiconductor memory device having improved page buffers 失效
标题翻译：具有改进的页面缓冲器的非易失性半导体存储器件
公开(公告)号：US06278636B1
公开(公告)日：2001-08-21
申请号：US09521168
申请日：2000-03-08
申请人： Jin-Yub Lee
发明人： Jin-Yub Lee
IPC分类号： G11C700
CPC分类号： G11C7/106 , G11C7/1012 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C16/10
摘要： Disclosed herein is a nonvolatile semiconductor memory device which comprises a memory cell array, page buffers and Y-pass gate circuit. Each page buffer according to the present invention contains its latch which has a first current driving capacity during a sensing period of a read operation and a second current driving capacity during a data output period of the read operation. Similar adjustable current drive capacity is provided during a program operation of the memory device. Preferably, such additional current drive capacity is provided via dual parallel pull-up transistors provided within a data latch circuit corresponding with each bit line of the memory device. Provision of the second parallel transistor and associated gating eliminates the need for one of the prior art circuit inverters in the latch, thereby reducing layout space over-all within the page buffer circuit region of the device.
摘要翻译：本文公开了一种非易失性半导体存储器件，其包括存储单元阵列，页缓冲器和Y遍门电路。根据本发明的每个页缓冲器包含其锁存器，其在读操作的感测周期期间具有第一电流驱动能力，并且在读操作的数据输出周期期间具有第二电流驱动能力。在存储器件的编程操作期间提供类似的可调电流驱动能力。优选地，通过设置在对应于存储器件的每个位线的数据锁存电路内的双并联上拉晶体管提供这种额外的电流驱动能力。提供第二并联晶体管和相关门控消除了对锁存器中的现有技术电路逆变器之一的需要，从而在设备的页缓冲器电路区域内全部减少布局空间。

52. 发明授权

US08760919B2 Nonvolatile memory device and method of reading data in nonvolatile memory device 有权
标题翻译：非易失性存储器件和非易失性存储器件中的数据读取方法
公开(公告)号：US08760919B2
公开(公告)日：2014-06-24
申请号：US13598892
申请日：2012-08-30
申请人： Jung-Ho Song , Jin-Yub Lee , Jae-Woo Im , Seung-Jae Lee , Sang-So Park
发明人： Jung-Ho Song , Jin-Yub Lee , Jae-Woo Im , Seung-Jae Lee , Sang-So Park
IPC分类号： G11C11/56 , G11C16/04
CPC分类号： G11C11/56 , G11C11/5642 , G11C16/04 , G11C16/0483 , G11C16/26 , G11C16/3404 , G11C2211/56
摘要： A method is provided for reading data in a nonvolatile memory device. The method includes performing a first read operation on multiple multi-level memory cells (MLCs), performing a first sensing operation on at least one flag cell corresponding to the MLCs, selectively performing a second read operation on the MLCs based on a result of the first sensing operation, and performing a second sensing operation on the at least one flag cell when the second read operation is performed. Read data is output based on results of the first read operation and the first sensing operation when the second read operation is not performed, and the read data is output based on result of the first read operation, the first sensing operation, the second read operation and the second sensing operation when the second read operation is performed. The read data corresponds to programmed data in the MLCs.
摘要翻译：提供了一种用于在非易失性存储器件中读取数据的方法。该方法包括：对多个多电平存储器单元（MLC），在对应于MLC中的至少一个标志单元，基于所述结果选择性地执行上的MLC的第二读取操作执行第一读出操作的第一次读操作第一感测操作，并且当执行第二读取操作时对所述至少一个标志单元执行第二感测操作。在不执行第二读取操作时，基于第一读取操作和第一感测操作的结果输出读取数据，并且基于第一读取操作，第一感测操作，第二读取操作的结果来输出读取数据以及执行第二读取操作时的第二感测操作。读取数据对应于MLC中的编程数据。

53. 发明授权

US07772910B2 Internal clock generator, system and method 有权
标题翻译：内部时钟发生器，系统和方法
公开(公告)号：US07772910B2
公开(公告)日：2010-08-10
申请号：US12045125
申请日：2008-03-10
申请人： Chul-Ho Lee , Jin-Yub Lee
发明人： Chul-Ho Lee , Jin-Yub Lee
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3275 , Y02D10/126 , Y02D10/14
摘要： An internal clock generator, system and method of generating the internal clock are disclosed. The method comprises detecting the level of an operating voltage within the system, comparing the level of the operating voltage to a target voltage level and generating a corresponding detection signal, and selecting between a normal clock and an alternate clock having a period longer than the period of the normal clock in relation to the detection signal and generating an internal clock on the basis of the selection.
摘要翻译：公开了一种产生内部时钟的内部时钟发生器，系统和方法。该方法包括检测系统内的工作电压的电平，将工作电压的电平与目标电压电平进行比较，并产生相应的检测信号，以及选择正常时钟和具有比周期长的周期的备用时钟的相对于检测信号的正常时钟，并且基于该选择产生内部时钟。

54. 发明授权

US07719897B2 Program verification for non-volatile memory 有权
标题翻译：非易失性存储器的程序验证
公开(公告)号：US07719897B2
公开(公告)日：2010-05-18
申请号：US11297779
申请日：2005-12-07
申请人： Chul-Ho Lee , Jin-Yub Lee
发明人： Chul-Ho Lee , Jin-Yub Lee
IPC分类号： G11C16/26
CPC分类号： G11C16/3454 , G11C16/04 , G11C16/10 , G11C29/52 , G11C29/804 , G11C2029/0409 , G11C2216/14
摘要： A non-volatile memory device includes page buffers arranged in groups, each group being coupled to a corresponding data output line so that data from more than one of the page buffers in each group may be simultaneously represented on the corresponding data output line during a program verification operation. Page buffers may be arranged in repair units with data from more than one page buffer simultaneously coupled to a data output line during a column scan operation.
摘要翻译：非易失性存储器件包括以组为单位布置的页缓冲器，每个组耦合到对应的数据输出线，使得每个组中来自多个页缓冲器中的数据可以在程序期间在相应的数据输出行上同时表示验证操作。在列扫描操作期间，页缓冲器可以被布置成具有来自多于一个页缓冲器的数据同时耦合到数据输出线的修复单元。

55. 发明授权

US07652948B2 Nonvolatile memory devices and programming methods using subsets of columns 失效
标题翻译：非易失性存储器件和使用子集的编程方法
公开(公告)号：US07652948B2
公开(公告)日：2010-01-26
申请号：US11282237
申请日：2005-11-18
申请人： Ho-Kil Lee , Jin-Yub Lee
发明人： Ho-Kil Lee , Jin-Yub Lee
IPC分类号： G11C8/00
CPC分类号： G11C16/10 , G11C16/3454 , G11C2216/14
摘要： Nonvolatile memory devices include a memory cell array having memory cells arranged in rows and columns, and an address storing unit that is configured to store therein an indicator of an initial column address and an indicator of an end column address, to identify a subset of the columns that extends from the initial column address to the end column address. A program circuit is configured to verify a programming operation for a selected row at the subset of the columns that extends from the initial column address to the end column address. Analogous methods of programming a nonvolatile memory device also may be provided.
摘要翻译：非易失性存储器件包括具有以行和列排列的存储器单元的存储单元阵列，以及配置为在其中存储初始列地址的指示符和结束列地址的指示符的地址存储单元，以识别从初始列地址延伸到结束列地址的列。程序电路被配置为验证在从初始列地址延伸到结束列地址的列的子集处的所选行的编程操作。也可以提供类似的非易失性存储器件编程方法。

56. 发明授权

US07643351B2 Erase voltage generator circuit for providing uniform erase execution time and nonvolatile memory device having the same 有权
标题翻译：擦除电压发生器电路以提供均匀的擦除执行时间，并具有相同的非易失性存储器件
公开(公告)号：US07643351B2
公开(公告)日：2010-01-05
申请号：US12115827
申请日：2008-05-06
申请人： Dae-Sik Park , Jin-Yub Lee
发明人： Dae-Sik Park , Jin-Yub Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/30 , G11C16/16
摘要： An erase voltage generation circuit providing a uniform erase execution time and a non-volatile semiconductor memory device having the same, in which the erase voltage generation circuit includes a high voltage generation unit, a voltage level detection unit, an execution time checking unit and a discharging unit. The high voltage generation unit generates an erase voltage. The voltage level detection unit detects the erase voltage and generates a level detection signal. The level detection signal is activated when the erase voltage reaches a target voltage. The execution time checking unit generates an execution end signal that is activated in response to the lapse of an erase execution time from the activation of the level detection signal. The discharging unit discharges the erase voltage as a discharge voltage. The high voltage generation unit is disabled in response to the activation of the execution end signal, and the discharging unit is enabled in response to the activation of the execution end signal.
摘要翻译：提供均匀擦除执行时间的擦除电压产生电路和具有该擦除执行时间的非易失性半导体存储器件，其中擦除电压产生电路包括高电压产生单元，电压电平检测单元，执行时间检查单元和放电单元高电压产生单元产生擦除电压。电压电平检测单元检测擦除电压并产生电平检测信号。当擦除电压达到目标电压时，电平检测信号被激活。执行时间检查单元生成响应于从电平检测信号的激活而经过擦除执行时间而被激活的执行结束信号。放电单元将擦除电压作为放电电压放电。响应于执行结束信号的激活，高电压生成单元被禁用，并且放电单元响应于执行结束信号的激活而被使能。

57. 发明授权

US07545680B2 Flash memory device and word line enable method thereof 有权
标题翻译：闪存装置及其字线使能方法
公开(公告)号：US07545680B2
公开(公告)日：2009-06-09
申请号：US11599434
申请日：2006-11-15
申请人： Jin-Kook Kim , Jin-Yub Lee
发明人： Jin-Kook Kim , Jin-Yub Lee
IPC分类号： G11C16/04
CPC分类号： G11C8/08 , G11C8/10 , G11C16/0483 , G11C16/08 , G11C16/30
摘要： In one aspect, a word line enable method in a flash memory device includes driving a signal line corresponding to a selected word line with a word line voltage, and stepwise increasing a gate voltage of a switch transistor connected between the selected word line and the signal line during a program execute period.
摘要翻译：一方面，闪速存储装置中的字线使能方法包括用字线电压驱动与选定字线对应的信号线，并且逐步增加连接在选定字线与信号之间的开关晶体管的栅极电压在程序执行期间。

58. 发明申请

US20090135658A1 Flash memory device and read method thereof 有权
标题翻译：闪存设备及其读取方法
公开(公告)号：US20090135658A1
公开(公告)日：2009-05-28
申请号：US12292741
申请日：2008-11-25
申请人： Dae-Sik Park , Jin-Yub Lee
发明人： Dae-Sik Park , Jin-Yub Lee
IPC分类号： G11C16/26
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/3427
摘要： A flash memory device includes a memory block including word lines arranged between a first selection line and a second selection line, the word lines being divided into a first group and a second group, a control logic configured to determine an activation order of the first and second selection lines and determine first and second read voltages to be supplied to unselected word lines, the control logic determining the activation order according to whether a selected word line belongs to the first group or the second group, and a row selection circuit configured to, during a read operation, drive the unselected word lines with the first and second read voltages, and activate the first and second selection lines, according to the control logic.
摘要翻译：闪速存储器件包括存储块，其包括布置在第一选择线和第二选择线之间的字线，所述字线被分成第一组和第二组，控制逻辑被配置为确定第一和第二组的激活顺序，第二选择线，并且确定要提供给未选字线的第一和第二读取电压，所述控制逻辑根据所选择的字线是否属于所述第一组或所述第二组来确定所述激活顺序;以及行选择电路，在读取操作期间，利用第一和第二读取电压驱动未选择的字线，并根据控制逻辑激活第一和第二选择线。

59. 发明申请

US20080310226A1 Multi-Bit Flash Memory Devices Having a Single Latch Structure and Related Programming Methods, Systems and Memory Cards 有权
标题翻译：具有单个锁存结构的多位闪存器件和相关编程方法，系统和存储卡
公开(公告)号：US20080310226A1
公开(公告)日：2008-12-18
申请号：US12182274
申请日：2008-07-30
申请人： Sang-Chul Kang , Ho-Kil Lee , Jin-Yub Lee
发明人： Sang-Chul Kang , Ho-Kil Lee , Jin-Yub Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454 , G11C2211/5621 , G11C2211/5642
摘要： Multi-bit flash memory devices are provided. The multi-bit flash memory device includes an array of memory cells and a page buffer block including page buffers. Each of the page buffers has a single latch structure and performs a write operation with respect to memory cells according to loaded data. A buffer random access memory (RAM) is configured to store program data provided from an external host device during a multi-bit program operation. Control logic is provided that is configured to control the page buffer block and the buffer RAM so that program data stored in the buffer RAM is reloaded into the page buffer block whenever data programmed before the multi-bit program operation is compared with data to be currently programmed. The control logic is configured to store data to be programmed next in the buffer RAM before the multi-bit program operation is completed.
摘要翻译：提供多位闪存设备。该多位闪存器件包括存储单元阵列和包括页缓冲器的页缓冲块。每个页面缓冲器具有单个锁存结构，并且根据加载的数据对存储器单元执行写入操作。缓冲随机存取存储器（RAM）被配置为在多位程序操作期间存储从外部主机设备提供的程序数据。提供了控制逻辑，其被配置为控制页面缓冲区块和缓冲器RAM，使得存储在缓冲器RAM中的程序数据被重新加载到页面缓冲器块中，每当在多位程序操作之前编程的数据与当前的数据进行比较程序。控制逻辑被配置为在多位程序操作完成之前存储要在缓冲RAM中接下来被编程的数据。

60. 发明授权

US07460403B2 Flash memory devices and methods of operating the same 失效
公开(公告)号：US07460403B2
公开(公告)日：2008-12-02
申请号：US11606283
申请日：2006-11-30
申请人： Jin-Yub Lee
发明人： Jin-Yub Lee
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3418 , G11C16/3427
摘要： A memory cell array includes a NAND string formed of a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor. The string selection transistor controls an electrical connection between the NAND string and a bit line based on a string selection voltage in a read operation. A row selection circuit is coupled to the memory cell array through a string selection line, ground selection line and a plurality of word lines. The row selection circuit selects a word line which is coupled to the read memory cell among the plurality of word lines based on a row address signal and a read voltage in a read operation. A voltage generation circuit generates the string selection voltage and the read voltage.

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