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51. 发明授权

US07329940B2 Semiconductor structure and method of manufacture 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US07329940B2
公开(公告)日：2008-02-12
申请号：US11163882
申请日：2005-11-02
申请人： Douglas D. Coolbaugh , Alvin J. Joseph , Seong-dong Kim , Louis D. Lanzerotti , Xuefeng Liu , Robert M. Rassel
发明人： Douglas D. Coolbaugh , Alvin J. Joseph , Seong-dong Kim , Louis D. Lanzerotti , Xuefeng Liu , Robert M. Rassel
IPC分类号： H01L27/082
CPC分类号： H01L27/0814 , H01L27/0664 , H01L27/0823 , H01L29/0821 , H01L29/7371 , H01L29/868
摘要： A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.
摘要翻译：一种结构包括具有形成在具有第一厚度的第一区域中的第一子集电极的单晶片和形成在具有不同于第一厚度的第二厚度的第二区域中的第二子集电极。还可以设想一种方法，其包括提供包括第一层并在第一层中形成第一掺杂区的衬底。该方法还包括在第一层上形成第二层并在第二层中形成第二掺杂区域。第二掺杂区形成在与第一掺杂区不同的深度。该方法还包括在第一层中形成第一通道并在第二层中形成第二通道以将第一通道连接到表面。

52. 发明授权

US08871600B2 Schottky barrier diodes with a guard ring formed by selective epitaxy 有权
标题翻译：具有通过选择性外延形成的保护环的肖特基势垒二极管
公开(公告)号：US08871600B2
公开(公告)日：2014-10-28
申请号：US13294760
申请日：2011-11-11
申请人： David L. Harame , Qizhi Liu , Robert M. Rassel
发明人： David L. Harame , Qizhi Liu , Robert M. Rassel
IPC分类号： H01L21/8222 , H01L29/47 , H01L27/07 , H01L29/66 , H01L29/732 , H01L29/872 , H01L29/08 , H01L29/161
CPC分类号： H01L29/0684 , H01L27/0766 , H01L29/0821 , H01L29/161 , H01L29/47 , H01L29/66143 , H01L29/66234 , H01L29/7322 , H01L29/872
摘要： Schottky barrier diodes, methods for fabricating Schottky barrier diodes, and design structures for a Schottky barrier diode. A guard ring for a Schottky barrier diode is formed with a selective epitaxial growth process. The guard ring for the Schottky barrier diode and an extrinsic base of a vertical bipolar junction diode on a different device region than the Schottky barrier diode may be concurrently formed using the same selective epitaxial growth process.
摘要翻译：肖特基势垒二极管，肖特基势垒二极管的制造方法以及肖特基势垒二极管的设计结构。用选择性外延生长工艺形成用于肖特基势垒二极管的保护环。可以使用相同的选择性外延生长工艺同时形成用于肖特基势垒二极管的保护环和与肖特基势垒二极管不同的器件区上的垂直双极结二极管的外部基极。

53. 发明授权

US08754455B2 Junction field effect transistor structure with P-type silicon germanium or silicon germanium carbide gate(s) and method of forming the structure 有权
标题翻译：具有P型硅锗或硅碳化硅栅的结型场效应晶体管结构和形成该结构的方法
公开(公告)号：US08754455B2
公开(公告)日：2014-06-17
申请号：US12983489
申请日：2011-01-03
申请人： Xuefeng Liu , Richard A. Phelps , Robert M. Rassel , Xiaowei Tian
发明人： Xuefeng Liu , Richard A. Phelps , Robert M. Rassel , Xiaowei Tian
IPC分类号： H01L29/80
CPC分类号： H01L29/66916 , H01L27/14679 , H01L29/0649 , H01L29/16 , H01L29/42316 , H01L29/66462 , H01L29/808 , H01L29/8086
摘要： Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure.
摘要翻译：公开了具有一个或多个P型硅锗（SiGe）或硅碳化硅（SiGeC）栅极（即，SiGe或SiGeC基异质结JFET）的结型场效应晶体管（JFET）结构的实施例。 P型SiGe或SiGeC栅极允许较低的截止电压（即，较低的Voff），而不增加导通电阻（Ron）。具体来说，P型栅极中的SiGe或SiGeC材料限制了P型掺杂物的扩散，从而确保了P型栅极与N型沟道区域结的关系更明确（即，与分级相反的突发性）。通过明确定义该结，N型沟道区中的耗尽层延伸。延伸耗尽层依次允许更快的夹断（即，需要更低的Voff）。 P型SiGe或SiGeC栅极可以结合到常规的横向JFET结构和/或垂直JFET结构中。本文还公开了形成这种JFET结构的方法的实施例。

54. 发明授权

US08618588B2 Anti-blooming pixel sensor cell with active neutral density filter, methods of manufacture, and design structure 有权
标题翻译：具有活性中性密度滤光片的防晕像素传感器单元，制造方法和设计结构
公开(公告)号：US08618588B2
公开(公告)日：2013-12-31
申请号：US12915888
申请日：2010-10-29
申请人： Kristin M. Ackerson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Richard J. Rassel , Robert M. Rassel
发明人： Kristin M. Ackerson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Richard J. Rassel , Robert M. Rassel
IPC分类号： H01L31/062 , H01L31/113
CPC分类号： H04N5/238 , H01L27/14623 , H01L27/14625 , H01L27/14685 , H04N5/3591
摘要： A method of preventing blooming in a pixel array includes affecting an amount of light that impinges on a photoelectric conversion element by adjusting a transmissivity of an electrochromic element based on an output of the photoelectric conversion element.
摘要翻译：防止像素阵列中的起霜的方法包括通过基于光电转换元件的输出调节电致变色元件的透射率来影响照射到光电转换元件上的光量。

55. 发明授权

US08519478B2 Schottky barrier diode, a method of forming the diode and a design structure for the diode 有权
标题翻译：肖特基势垒二极管，形成二极管的方法和二极管的设计结构
公开(公告)号：US08519478B2
公开(公告)日：2013-08-27
申请号：US13019716
申请日：2011-02-02
申请人： Robert M. Rassel , Mark E. Stidham
发明人： Robert M. Rassel , Mark E. Stidham
IPC分类号： H01L29/06
CPC分类号： H01L29/66143 , G06F17/5068 , H01L29/872
摘要： Disclosed are embodiments of a Schottky barrier diode. This diode can be formed in a semiconductor substrate having a doped region with a first conductivity type. A trench isolation structure can laterally surround a section of the doped region at the top surface of the substrate. A semiconductor layer can be positioned on the top surface of the substrate. This semiconductor layer can have a Schottky barrier portion over the defined section of the doped region and a guardring portion over the trench isolation structure laterally surrounding the Schottky barrier portion. The Schottky barrier portion can have the first conductivity type and the guarding portion can have a second conductivity type different from the first conductivity type. A metal silicide layer can overlie the semiconductor layer. Also disclosed are embodiments of a method of forming this Schottky barrier diode and of a design structure for the Schottky barrier diode.
摘要翻译：公开了肖特基势垒二极管的实施例。该二极管可以形成在具有第一导电类型的掺杂区域的半导体衬底中。沟槽隔离结构可以横向围绕衬底顶表面处的掺杂区域的一部分。半导体层可以位于衬底的顶表面上。该半导体层可以在掺杂区域的限定部分上方具有肖特基势垒部分，并且在沟槽隔离结构之上的护套部分横向围绕肖特基势垒部分。肖特基势垒部分可以具有第一导电类型，并且防护部分可以具有不同于第一导电类型的第二导电类型。金属硅化物层可以覆盖半导体层。还公开了形成该肖特基势垒二极管的方法和肖特基势垒二极管的设计结构的实施例。

56. 发明授权

US08518782B2 Semiconductor device including asymmetric lightly doped drain (LDD) region, related method and design structure 有权
标题翻译：半导体器件包括非对称轻掺杂漏极（LDD）区域，相关方法和设计结构
公开(公告)号：US08518782B2
公开(公告)日：2013-08-27
申请号：US12963054
申请日：2010-12-08
申请人： Alan B. Botula , Robert M. Rassel , Yun Shi , Mark E. Stidham
发明人： Alan B. Botula , Robert M. Rassel , Yun Shi , Mark E. Stidham
IPC分类号： H01L21/426
CPC分类号： H01L29/7833 , H01L21/26586 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including a first source drain region, a second source drain region, and an intrinsic region therebetween; an asymmetric lightly doped drain (LDD) region within the substrate, wherein the asymmetric LDD region extends from the first source drain region into the intrinsic region between the first source drain region and the second source drain region; and a gate positioned atop the semiconductor substrate, wherein an outer edge of the gate overlaps the second source drain region. A related method and design structure are also disclosed.
摘要翻译：公开了一种半导体器件。半导体器件包括：半导体衬底，包括第一源极漏极区域，第二源极漏极区域及其之间的固有区域; 在所述衬底内的不对称轻掺杂漏极（LDD）区域，其中所述不对称LDD区域从所述第一源极漏极区域延伸到所述第一源极漏极区域和所述第二源极漏极区域之间的本征区域; 以及位于所述半导体衬底顶部的栅极，其中所述栅极的外边缘与所述第二源极漏极区重叠。还公开了相关的方法和设计结构。

57. 发明授权

US08466501B2 Asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method of forming the asymmetrical SOI JFET 有权
标题翻译：非对称绝缘体上硅（SOI）结场效应晶体管（JFET）和形成非对称SOI JFET的方法
公开(公告)号：US08466501B2
公开(公告)日：2013-06-18
申请号：US12784583
申请日：2010-05-21
申请人： Douglas B. Hershberger , Richard A. Phelps , Robert M. Rassel , Stephen A. St. Onge , Michael J. Zierak
发明人： Douglas B. Hershberger , Richard A. Phelps , Robert M. Rassel , Stephen A. St. Onge , Michael J. Zierak
IPC分类号： H01L29/808
CPC分类号： G06F17/5068 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/0843 , H01L29/66901 , H01L29/8086
摘要： An asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method. The JFET includes a bottom gate on an insulator layer, a channel region on the bottom gate and, on the channel region, source/drain regions and a top gate between the source/drain regions. STIs isolate the source/drain regions from the top gate and a DTI laterally surrounds the JFET to isolate it from other devices. Non-annular well(s) are positioned adjacent to the channel region and bottom gate (e.g., a well having the same conductivity type as the top and bottom gates can be connected to the top gate and can extend down to the insulator layer, forming a gate contact on only a portion of the channel region, and/or another well having the same conductivity type as the channel and source/drain regions can extend from the source region to the insulator layer, forming a source-to-channel strap).
摘要翻译：不对称绝缘体上硅（SOI）结场效应晶体管（JFET）及其方法。 JFET包括在绝缘体层上的底栅极，底栅上的沟道区，以及沟道区上的源/漏区和源/漏区之间的顶栅。 STI将源极/漏极区域与顶部栅极隔离，并且DTI横向围绕JFET以将其与其它器件隔离。非环形阱位于与沟道区域和底部栅极相邻的位置（例如，具有与顶部和底部栅极相同的导电类型的阱可以连接到顶部栅极并且可以向下延伸到绝缘体层，形成在沟道区域的仅一部分上的栅极接触和/或具有与沟道和源极/漏极区相同的导电类型的另一个阱可以从源极区域延伸到绝缘体层，形成源极至沟道的带）。

58. 发明申请

US20130140668A1 Forming Structures on Resistive Substrates 有权
标题翻译：电阻基板上的形成结构
公开(公告)号：US20130140668A1
公开(公告)日：2013-06-06
申请号：US13312442
申请日：2011-12-06
申请人： Alan B. Botula , Renata Camillo-Castillo , James S. Dunn , Jeffrey P. Gambino , Douglas B. Hershberger , Alvin J. Joseph , Mark E. Stidham , Robert M. Rassel
发明人： Alan B. Botula , Renata Camillo-Castillo , James S. Dunn , Jeffrey P. Gambino , Douglas B. Hershberger , Alvin J. Joseph , Mark E. Stidham , Robert M. Rassel
IPC分类号： H01L27/04 , H01L21/76
CPC分类号： H01L21/76224 , H01L21/26506 , H01L21/823892 , H01L27/04 , H01L27/0623 , H01L27/0635 , H01L27/0802 , H01L27/0811 , H01L27/0928
摘要： A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.
摘要翻译：衬底包括具有第一电阻率的第一区域，用于优化场效应晶体管，具有第二电阻率的第二区域，用于优化双极晶体管器件和三阱的npn子集电极，具有第三电阻率的第三区域，具有第三电阻率用于无源器件的高电阻率，第四区域，基本上没有植入，以为器件提供低周边电容。

59. 发明申请

US20130119505A1 Schottky Barrier Diodes With a Guard Ring Formed by Selective Epitaxy 有权
标题翻译：肖特基势垒二极管与选择性外延形成的保护环
公开(公告)号：US20130119505A1
公开(公告)日：2013-05-16
申请号：US13294760
申请日：2011-11-11
申请人： David L. Harame , Qizhi Liu , Robert M. Rassel
发明人： David L. Harame , Qizhi Liu , Robert M. Rassel
IPC分类号： H01L29/47 , G06F9/45 , H01L21/329
CPC分类号： H01L29/0684 , H01L27/0766 , H01L29/0821 , H01L29/161 , H01L29/47 , H01L29/66143 , H01L29/66234 , H01L29/7322 , H01L29/872
摘要： Schottky barrier diodes, methods for fabricating Schottky barrier diodes, and design structures for a Schottky barrier diode. A guard ring for a Schottky barrier diode is formed with a selective epitaxial growth process. The guard ring for the Schottky barrier diode and an extrinsic base of a vertical bipolar junction diode on a different device region than the Schottky barrier diode may be concurrently formed using the same selective epitaxial growth process.
摘要翻译：肖特基势垒二极管，肖特基势垒二极管的制造方法以及肖特基势垒二极管的设计结构。用选择性外延生长工艺形成用于肖特基势垒二极管的保护环。可以使用相同的选择性外延生长工艺同时形成用于肖特基势垒二极管的保护环和与肖特基势垒二极管不同的器件区上的垂直双极结二极管的外部基极。

60. 发明授权

US08242584B2 Structure and method to create stress trench 有权
标题翻译：构造应力沟的结构和方法
公开(公告)号：US08242584B2
公开(公告)日：2012-08-14
申请号：US12647796
申请日：2009-12-28
申请人： Renata A. Camillo-Castillo , Robert J. Gauthier, Jr. , Richard A. Phelps , Robert M. Rassel , Andreas D. Stricker
发明人： Renata A. Camillo-Castillo , Robert J. Gauthier, Jr. , Richard A. Phelps , Robert M. Rassel , Andreas D. Stricker
IPC分类号： H01L29/06
CPC分类号： H01L29/8086 , H01L21/76283 , H01L29/66901 , H01L29/7846
摘要： An integrated circuit (IC) chip is provided comprising at least one trench including a stress-inducing material which imparts a stress on a channel region of a device, such as a junction gate field-effect transistor (JFET) or a metal-oxide-semiconductor field-effect transistor (MOSFET). A related method is also disclosed.
摘要翻译：提供了一种集成电路（IC）芯片，其包括至少一个沟槽，该至少一个沟槽包括在器件的沟道区域上施加应力的应力诱导材料，诸如结栅场效应晶体管（JFET）或金属氧化物 - 半导体场效应晶体管（MOSFET）。还公开了相关方法。

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