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51. 发明授权

US07975170B2 Memory refresh system and method 有权
标题翻译：内存刷新系统和方法
公开(公告)号：US07975170B2
公开(公告)日：2011-07-05
申请号：US11763593
申请日：2007-06-15
申请人： Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Josef Schnell , Octavian Beldiman , Lee Ward Collins
发明人： Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Josef Schnell , Octavian Beldiman , Lee Ward Collins
IPC分类号： G06F11/00
CPC分类号： G11C29/02 , G11C7/1039 , G11C11/401 , G11C11/406 , G11C29/028 , G11C29/50016 , G11C2211/4062 , G11C2211/4065
摘要： A refresh scheduler is configured to refresh memory cells of a memory device according to a plurality of refresh intervals. The various refresh intervals are determined in response to refresh errors.
摘要翻译：刷新调度器被配置为根据多个刷新间隔刷新存储器设备的存储单元。响应于刷新错误确定各种刷新间隔。

52. 发明授权

US07721010B2 Method and apparatus for implementing memory enabled systems using master-slave architecture 有权
标题翻译：使用主 - 从体系结构实现启用内存的系统的方法和装置
公开(公告)号：US07721010B2
公开(公告)日：2010-05-18
申请号：US11930450
申请日：2007-10-31
申请人： Josef Schnell , Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Octavian Beldiman , Lee Ward Collins
发明人： Josef Schnell , Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Octavian Beldiman , Lee Ward Collins
IPC分类号： G06F12/00
CPC分类号： G11C7/10 , G11C7/1051 , G11C7/1063 , G11C7/1078 , G11C7/109
摘要： Embodiments of the invention generally provide a system, method, and memory device for accessing memory. In one embodiment, a first memory device includes command decoding logic configured to decode commands issued to the first memory device and a second memory device, while command decoding logic of the second memory device is bypassed.
摘要翻译：本发明的实施例通常提供用于访问存储器的系统，方法和存储器装置。在一个实施例中，第一存储器设备包括命令解码逻辑，其被配置为解码发出到第一存储器设备的命令和第二存储器设备，同时绕过第二存储器设备的命令解码逻辑。

53. 发明授权

US07694196B2 Self-diagnostic scheme for detecting errors 失效
标题翻译：用于检测错误的自诊断方案
公开(公告)号：US07694196B2
公开(公告)日：2010-04-06
申请号：US11943428
申请日：2007-11-20
申请人： Josef Schnell , Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Octavian Beldiman , Lee Ward Collins
发明人： Josef Schnell , Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Octavian Beldiman , Lee Ward Collins
IPC分类号： G11C29/00
CPC分类号： G11C5/04 , G11C29/44 , G11C29/789 , G11C2029/0401 , G11C2029/1208 , G11C2229/726 , G11C2229/743 , H01L25/0657 , H01L25/18 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： The present invention is generally related to integrated circuit devices, and more particularly, to methods and systems of a multi-chip package (MCP) containing a self-diagnostic scheme for detecting errors in the MCP. The MCP generally comprises a controller, at least one volatile memory chip having error detection logic, at least one non-volatile memory chip, and at least one fail signature register for storing fail signature data related to memory errors detected in the MCP. The controller can poll the fail signature register for fail signature data related to memory errors stored therein. Upon detection of fail signature data, the controller can store the fail signature data on a fail signature register located on a non-volatile memory.
摘要翻译：本发明通常涉及集成电路器件，更具体地说，涉及包含用于检测MCP中的错误的自诊断方案的多芯片封装（MCP）的方法和系统。 MCP通常包括控制器，具有错误检测逻辑的至少一个易失性存储器芯片，至少一个非易失性存储器芯片以及用于存储与在MCP中检测到的存储器错误相关的失败签名数据的至少一个故障签名寄存器。控制器可以轮询失败签名寄存器以获取与其中存储的存储器错误有关的失败签名数据。在检测到失败签名数据时，控制器可以将故障签名数据存储在位于非易失性存储器上的故障签名寄存器上。

54. 发明申请

US20070178864A1 Electronic subsystem assembly including radio frequency interface 审中-公开
标题翻译：电子子系统组装包括射频接口
公开(公告)号：US20070178864A1
公开(公告)日：2007-08-02
申请号：US11345422
申请日：2006-02-01
申请人： Oliver Kiehl , Katja Kienzl
发明人： Oliver Kiehl , Katja Kienzl
IPC分类号： H04B1/18 , G06F12/00
CPC分类号： G06F13/385
摘要： An electronic subsystem assembly including a subsystem circuit, a contact interface, a memory circuit, and a radio frequency interface. The subsystem circuit is configured to provide a system function. The contact interface is configured to receive input signals and output signals. The memory circuit is configured to receive the input signals via the contact interface and to transmit the output signals via the contact interface. The radio frequency interface is configured to receive data signals from the memory circuit and to provide a radio frequency transmission that includes the data signals.
摘要翻译：包括子系统电路，接触接口，存储器电路和射频接口的电子子系统组件。子系统电路被配置为提供系统功能。触点界面配置为接收输入信号和输出信号。存储器电路被配置为经由接触接口接收输入信号并且经由接触接口传送输出信号。无线电频率接口被配置为从存储器电路接收数据信号并提供包括数据信号的射频传输。

55. 发明申请

US20070094554A1 Chip specific test mode execution on a memory module 审中-公开
标题翻译：在内存模块上执行芯片特定的测试模式
公开(公告)号：US20070094554A1
公开(公告)日：2007-04-26
申请号：US11253716
申请日：2005-10-20
申请人： Martin Versen , Oliver Kiehl
发明人： Martin Versen , Oliver Kiehl
IPC分类号： G11C29/00
CPC分类号： G11C29/46 , G11C5/04 , G11C2029/4402
摘要： A test mode for component-specific testing of a memory module. Data is written to and stored in each memory component of a memory module, which data indicates whether the memory component is to execute a particular test mode. Upon receiving a test mode command supplied in common to all of the memory components on the memory module, each memory component examines the data to determine whether it is to execute a test mode command supplied contemporaneously therewith or subsequently supplied test mode commands.
摘要翻译：用于内存模块组件特定测试的测试模式。将数据写入并存储在存储器模块的每个存储器组件中，该数据指示存储器组件是否要执行特定的测试模式。在接收到对存储器模块中的所有存储器组件共同提供的测试模式命令时，每个存储器组件检查数据以确定是否执行与其同时提供的测试模式命令或随后提供的测试模式命令。

56. 发明授权

US07060529B2 Multiple chip semiconductor arrangement having electrical components in separating regions 失效
标题翻译：在分离区域中具有电气部件的多芯片半导体布置
公开(公告)号：US07060529B2
公开(公告)日：2006-06-13
申请号：US10841162
申请日：2004-05-07
申请人： Manfred Reithinger , Mike Killian , Gerd Frankowsky , Oliver Kiehl , Gerhard Mueller , Ernst Stahl , Hartmud Terletzki , Thomas Vogelsang
发明人： Manfred Reithinger , Mike Killian , Gerd Frankowsky , Oliver Kiehl , Gerhard Mueller , Ernst Stahl , Hartmud Terletzki , Thomas Vogelsang
IPC分类号： H01L21/50 , H01L21/30
CPC分类号： H01L25/18 , H01L23/50 , H01L23/5382 , H01L27/105 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.
摘要翻译：半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。晶片的分数部分具有电连接到芯片的多个电触点。封装还包括其上具有电导体的电介质构件。电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

57. 发明授权

US06937058B2 Methods and apparatus for active termination of high-frequency signals 有权
公开(公告)号：US06937058B2
公开(公告)日：2005-08-30
申请号：US10620989
申请日：2003-07-16
申请人： Hans-Heinrich Viehmann , Oliver Kiehl
发明人： Hans-Heinrich Viehmann , Oliver Kiehl
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H04L25/0298
摘要： An integrated circuit, comprising: at least one main circuit operable to perform one or more functions, and including at least one I/O node for receiving or transmitting an operating signal; an active termination circuit having first and second MOSFETs of the same type coupled in series across a Vdd node of a first source potential and a Vss node of a second source potential, the at least one I/O node being coupled to a common node between the first and second MOSFETs; and a control circuit operable to bias the first and second MOSFETs such that they exhibit a controlled impedance at the common node.

58. 发明授权

US06927709B2 Transmission and reception interface and method of data transmission 失效
标题翻译：数据传输接收和接收方式
公开(公告)号：US06927709B2
公开(公告)日：2005-08-09
申请号：US10196676
申请日：2002-07-16
申请人： Oliver Kiehl
发明人： Oliver Kiehl
IPC分类号： H04L7/00 , H04L7/02 , H04L25/49 , H03M7/00 , H03M7/20
CPC分类号： H04L25/4908 , H04L7/0066 , H04L25/4904
摘要： An N-bit word is produced from an M-bit code received on an M-bit line, M being larger than N, the M-bit code comprising at least an M-bit code word and a previous M-bit code word, the M-bit code word comprising different levels at at least two bit positions, and the previous M-bit code word comprising levels opposite to the different levels at the corresponding bit positions, by comparing the levels at the two bit positions of the M-bit code word to obtain a first value, comparing the levels at the two corresponding bit positions of the previous M-bit code word to obtain a second value, detecting that the first value is opposite to the second value, and decoding the M-bit code word responsive to detecting that the first value is opposite to the second value. An advantage of the present invention is that all the lines taking part in the transmission have the same electrical characteristics, the same meaning and the same kind of loads.
摘要翻译：从在M位线上接收的M位代码产生N比特字，M大于N，M比特码至少包括一个M比特码字和一个前一个M比特码字，所述M位码字在至少两个位位置包括不同电平，并且所述先前的M位码字包括与相应位位置处的不同电平相反的电平，通过比较M-位码字的两位位置处的电平，比特码字以获得第一值，比较前一M比特码字的两个对应比特位置处的电平以获得第二值，检测第一值与第二值相反，并且解码M位响应于检测到第一值与第二值相反的代码字。本发明的优点在于，所有参与变速器的线路具有相同的电特性，相同的含义和相同种类的负载。

59. 发明申请

US20050111275A1 Cost efficient row cache for DRAMs 有权
标题翻译： DRAM高效的行缓存
公开(公告)号：US20050111275A1
公开(公告)日：2005-05-26
申请号：US10967899
申请日：2004-10-18
申请人： Oliver Kiehl
发明人： Oliver Kiehl
IPC分类号： G11C7/06 , G11C7/12 , G11C11/4091 , G11C11/4094 , G11C7/00
CPC分类号： G11C11/4091 , G11C7/06 , G11C7/12 , G11C11/4094 , G11C2207/005
摘要： A memory device includes a pair of complementary bitlines including a first bitline and a second bitline. A bitline precharge block is coupled between the first bitline and the second bitline. A sense amplifier is coupled to both the first bitline and the second bitline and a sense amplifier precharge block is coupled to the sense amplifier. The sense amplifier precharge block can be activated independently from the bitline precharge block. An isolation block is coupled between the pair of complementary bitlines and the bitline precharge block on one side and the sense amplifier and sense amplifier precharge block on another side.
摘要翻译：存储器件包括一对补充位线，包括第一位线和第二位线。位线预充电块耦合在第一位线和第二位线之间。读出放大器耦合到第一位线和第二位线，读出放大器预充电块耦合到读出放大器。读出放大器预充电块可以独立于位线预充电块来激活。隔离块耦合在一对互补位线和一侧的位线预充电块和另一侧的读出放大器和读出放大器预充电块之间。

60. 发明申请

US20050001298A1 Multiple chip semiconductor arrangement having electrical components in separating regions 失效
标题翻译：在分离区域中具有电气部件的多芯片半导体布置
公开(公告)号：US20050001298A1
公开(公告)日：2005-01-06
申请号：US10841162
申请日：2004-05-07
申请人： Manfred Reithinger , Mike Killian , Gerd Frankowsky , Oliver Kiehl , Gerhard Mueller , Ernst Stahl , Hartmud Terletzki , Thomas Vogelsang
发明人： Manfred Reithinger , Mike Killian , Gerd Frankowsky , Oliver Kiehl , Gerhard Mueller , Ernst Stahl , Hartmud Terletzki , Thomas Vogelsang
IPC分类号： H01L21/8242 , H01L23/50 , H01L23/538 , H01L25/18 , H01L27/105 , H01L23/544
CPC分类号： H01L25/18 , H01L23/50 , H01L23/5382 , H01L27/105 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.
摘要翻译：半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。晶片的分数部分具有电连接到芯片的多个电触点。封装还包括其上具有电导体的电介质构件。电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

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