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51. 发明授权

US07003276B2 Subsampling communication receiver architecture with gain control and RSSI generation 有权
标题翻译：采样增益控制和RSSI生成的通信接收机架构
公开(公告)号：US07003276B2
公开(公告)日：2006-02-21
申请号：US10132025
申请日：2002-04-25
申请人： Khurram Muhammad , Dirk Leipold , Kenneth J. Maggio
发明人： Khurram Muhammad , Dirk Leipold , Kenneth J. Maggio
IPC分类号： H04B1/26
CPC分类号： H04B1/0025 , H03H15/00 , H03H19/004 , H04B1/0003 , H04B1/28 , H04L27/24
摘要： A first periodic voltage waveform (20) is downconverted into a second periodic voltage waveform (35, 36). A plurality of temporally distinct samples (SA1, SA2, . . . ) respectively indicative of areas under corresponding fractional-cycles of the first voltage waveform are obtained. The samples are combined to produce the second voltage waveform. The samples can be manipulated to provide gain adjustment to the second voltage waveform. The samples are obtained by charging a sampling capacitance in response to a current waveform that corresponds to the first voltage waveform. The use of different sampling capacitances during respective predetermined time intervals permits the signal strength of the first waveform to be determined from observation of the second waveform.
摘要翻译：第一周期性电压波形（20）被下变频成第二周期性电压波形（35,36）。获得分别表示第一电压波形的相应分数周期下的面积的多个时间上不同的样本（SA 1，SA 2 ...）。将样品组合以产生第二电压波形。可以操作样品以对第二电压波形提供增益调整。通过响应于对应于第一电压波形的电流波形对采样电容进行充电来获得样本。在各个预定时间间隔期间使用不同的采样电容允许通过观察第二波形来确定第一波形的信号强度。

52. 发明申请

US20050287967A1 Low noise high isolation transmit buffer gain control mechanism 有权
标题翻译：低噪声高隔离传输缓冲器增益控制机制
公开(公告)号：US20050287967A1
公开(公告)日：2005-12-29
申请号：US11115815
申请日：2005-04-26
申请人： Chih-Ming Hung , Francis Cruise , Dirk Leipold , Robert Staszewski
发明人： Chih-Ming Hung , Francis Cruise , Dirk Leipold , Robert Staszewski
IPC分类号： H01Q11/12 , H03F1/32 , H03F3/191 , H04B1/04
CPC分类号： H04B1/0483 , H03F1/3241 , H03F1/3294 , H03F3/191 , H03F2200/331
摘要： A novel apparatus for a low noise, high isolation, all digital transmit buffer gain control mechanism. The gain control scheme is presented in the context of an all digital direct digital-to-RF amplitude converter (DRAC), which efficiently combines the traditional transmit chain functions of upconversion, I and Q combining, D/A conversion, filtering, buffering and RF output amplitude control into a single circuit. The transmit buffer is constructed as an array of NMOS switches. The control logic for each NMOS switch comprises a pass-gate type AND gate whose inputs are the phase modulated output of an all digital PLL and the amplitude control word from a digital control block. Power control is accomplished by recognizing the impairments suffered by a pseudo class E pre-power amplifier (PPA) when implemented in a CMOS process. Firstly, the NMOS switches of the array have significant on resistance and thus can only draw a limited current from the an RF choke when the input waveform is high. The significant on resistance of the NMOS switches is exploited in the DRAC circuit to introduce power control of the transmitted waveform and permits a fully digital method of controlling the RF output power.
摘要翻译：一种低噪声，高隔离，全数字发送缓冲增益控制机制的新型设备。增益控制方案在全数字直接数/频幅度转换器（DRAC）的上下文中呈现，该转换器有效地结合了上变频，I和Q组合，D / A转换，滤波，缓冲和 RF输出幅度控制成单个电路。发送缓冲器构造为NMOS开关阵列。每个NMOS开关的控制逻辑包括一个通门型AND门，其输入是全数字PLL的相位调制输出和来自数字控制块的幅度控制字。通过在CMOS工艺中实现时，通过识别伪E类预功率放大器（PPA）所遭受的损伤来实现功率控制。首先，阵列的NMOS开关具有大的导通电阻，因此当输入波形为高时，只能从RF扼流圈画出有限的电流。在DRAC电路中利用NMOS开关的重要导通电阻来引入发射波形的功率控制，并允许控制RF输出功率的全数字方法。

53. 发明授权

US06963732B2 Subsampling communication receiver architecture with relaxed IFA readout timing 有权
标题翻译：采用宽松的IFA读出时序对通信接收机架构进行采样
公开(公告)号：US06963732B2
公开(公告)日：2005-11-08
申请号：US10132436
申请日：2002-04-25
申请人： Khurram Muhammad , Dirk Leipold
发明人： Khurram Muhammad , Dirk Leipold
IPC分类号： H03H15/00 , H03H19/00 , H04B1/28 , H04B1/707 , H04L27/24 , H04B1/00
CPC分类号： H03H15/00 , H03H19/004 , H04B1/0003 , H04B1/0025 , H04B1/28 , H04L27/24
摘要： A first periodic voltage waveform (20) is downconverted into a second periodic voltage waveform (35, 36). A plurality of temporally distinct samples (SA1, SA2, . . . ) respectively indicative of areas under corresponding fractional-cycles of the first voltage waveform are obtained. The samples are combined to produce the second voltage waveform, and are also manipulated to implement a filtering operation such that the second voltage waveform represents a downconverted, filtered version of the first voltage waveform. The second waveform is driven by an amplifier stage (25), and the second waveform can be advantageously constructed so as to permit the amplifier stage to perform internal resets, offset corrections and other ancillary amplifier stage adjustments without losing information in the first waveform.
摘要翻译：第一周期性电压波形（20）被下变频成第二周期性电压波形（35,36）。获得分别表示第一电压波形的相应分数周期下的面积的多个时间上不同的样本（SA 1，SA 2 ...）。将样本组合以产生第二电压波形，并且还被操纵以实现滤波操作，使得第二电压波形表示第一电压波形的下变换的滤波版本。第二波形由放大器级（25）驱动，并且第二波形可以有利地构造成允许放大器级执行内部复位，偏移校正和其它辅助放大器级调整，而不会丢失第一波形中的信息。

54. 发明申请

US20050212606A1 Wireless communications device having type-II all-digital phase-locked loop (PLL) 有权
标题翻译：具有II型全数字锁相环（PLL）的无线通信设备
公开(公告)号：US20050212606A1
公开(公告)日：2005-09-29
申请号：US11122670
申请日：2005-05-04
申请人： Robert Staszewski , Dirk Leipold , Khurram Muhammad
发明人： Robert Staszewski , Dirk Leipold , Khurram Muhammad
IPC分类号： H03F1/02 , H03F1/32 , H03L7/093 , H03L7/099 , H03L7/107 , H03L7/00
CPC分类号： H03L7/1075 , H03F1/0211 , H03F1/3282 , H03L7/093 , H03L7/0991 , H03L7/107 , H03L2207/50
摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a wireless communication device having a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.
摘要翻译：用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。优选实施例包括具有带有比例环路增益路径（比例环路增益电路1115）和积分环路增益块（积分环路增益块1120）的环路滤波器的无线通信设备。在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。

55. 发明申请

US20050130618A1 Sampling mixer with asynchronous clock and signal domains 有权
标题翻译：具有异步时钟和信号域的采样混频器
公开(公告)号：US20050130618A1
公开(公告)日：2005-06-16
申请号：US11028995
申请日：2005-01-03
申请人： Robert Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
发明人： Robert Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
IPC分类号： H03D7/12 , H04B1/10 , H04B1/06 , H04B7/00 , H04L7/00
CPC分类号： H03D7/125 , H04B1/1036
摘要： A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having multiple clock generating hardware significantly increases power consumption and integrated circuit area when the mixer 1100 is integrated into silicon. A method and apparatus 1125 containing a circuit for generating a set of clock signals that can be shared by the different signal paths is presented. Advantage is taken of the significant capacitance difference between different sampling capacitors in the mixer and the superposition property.
摘要翻译：具有多个信号路径的混频器1100通常需要用于每个信号路径的单独的时钟产生硬件。然而，当混合器1100集成到硅中时，具有多个时钟产生硬件的冗余显着地增加了功耗和集成电路面积。提出了一种包含用于生成可由不同信号路径共享的一组时钟信号的电路的方法和装置1125。利用混频器中不同采样电容器之间的显着电容差和叠加特性。

56. 发明授权

US06809598B1 Hybrid of predictive and closed-loop phase-domain digital PLL architecture 有权
标题翻译：预测和闭环相域数字PLL架构的混合
公开(公告)号：US06809598B1
公开(公告)日：2004-10-26
申请号：US09695516
申请日：2000-10-24
申请人： Robert B. Staszewski , Dirk Leipold , Kenneth Maggio
发明人： Robert B. Staszewski , Dirk Leipold , Kenneth Maggio
IPC分类号： H03L706
CPC分类号： H04B1/7156 , H03C3/0925 , H03C3/0941 , H03C3/0966 , H03C3/0975 , H03L7/1806 , H03L2207/50 , H04B2001/71566 , H04L27/12
摘要： A phase-domain digital PLL loop is implemented using a hybrid of predictive and closed-loop architecture that allows direct DCO oscillator transmit modulation in the GFSK modulation scheme of “BLUETOOTH” or GSM, as well as the chip phase modulation of the 802.11b or Wideband-CDMA. The current gain of the DCO oscillator is predicted by observing past phase error responses to previous DCO corrections. DCO control is then augmented with the “open-loop” instantaneous frequency jump estimate of the new frequency control word.
摘要翻译：使用预测和闭环架构的混合来实现相域数字PLL环路，其允许在“蓝牙”或GSM的GFSK调制方案中直接DCO振荡器发送调制，以及802.11b的芯片相位调制或宽带CDMA。 DCO振荡器的当前增益是通过观察对先前DCO校正的过去相位误差响应来预测的。然后用新的频率控制字的“开环”瞬时频率跳跃估计来增加DCO控制。

57. 发明授权

US06593773B2 Power saving circuitry using predictive logic 有权
公开(公告)号：US06593773B2
公开(公告)日：2003-07-15
申请号：US09967275
申请日：2001-09-28
申请人： Robert B. Staszewski , Dirk Leipold
发明人： Robert B. Staszewski , Dirk Leipold
IPC分类号： H03D324
CPC分类号： H03L7/16 , H03K19/0016 , H03L7/085 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/099 , H03L2207/50 , H04L7/0029
摘要： To conserve power in a circuit where a high-speed signal HSIG controls combinational logic (10), while a low-speed signal LCLK drives a logic/memory circuit (12) that samples the output of the combinational logic, predictive logic state machine (14) generates a clock, P_LCLK, which has an active level preceding the active edge of LCLK by a period sufficient to allow the combinational logic to reach the desired state prior to the active edge of LCLK and, preferably, allows for possible jitter in LCLK. Responsive to P_LCLK, the signal suspend circuitry (16) either passes HSIG or gates off HSIG. Further reductions in power can be accomplished by predicting which portions of the logic/memory circuit (12) will be used, and clocking those portions.

58. 发明授权

US06326851B1 Digital phase-domain PLL frequency synthesizer 有权
标题翻译：数字相域PLL频率合成器
公开(公告)号：US06326851B1
公开(公告)日：2001-12-04
申请号：US09603023
申请日：2000-06-26
申请人： Robert B. Staszewski , Dirk Leipold
发明人： Robert B. Staszewski , Dirk Leipold
IPC分类号： H03L7085
CPC分类号： H03L7/18 , H03L7/085
摘要： A frequency synthesizer architecture naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase-domain. Synchronous logic is provided across a digitally controlled VCO and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information.
摘要翻译：频率合成器架构自然地将发射机调制能力与宽带全数字PLL调制方案相结合，以通过在同步相域中操作来最大化数字密集型实现。通过实施与参考计算相关联的定时调整，跨数字控制VCO提供同步逻辑，并且与VCO输出时钟同步，以允许频率控制字包含信道信息和发送调制信息。

59. 发明授权

US08542616B2 Simultaneous multiple signal reception and transmission using frequency multiplexing and shared processing 有权
标题翻译：使用频率复用和共享处理的同时多信号接收和传输
公开(公告)号：US08542616B2
公开(公告)日：2013-09-24
申请号：US12250646
申请日：2008-10-14
申请人： Robert B. Staszewski , Khurram Muhammad , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Dirk Leipold
IPC分类号： H04L5/14
CPC分类号： H04B1/0075 , H03D7/1441 , H03D7/1466 , H03D7/1483 , H03D7/165 , H03D2200/0025 , H03D2200/0047 , H03D2200/0074 , H03D2200/0084 , H03D2200/0088 , H04L5/06 , H04L5/143 , H04L27/3863 , H04L2027/0016
摘要： A novel mechanism for simultaneous multiple signal reception and transmission using frequency multiplexing and shared processing. Multiple RF signals, which may be of various wireless standards, are received using one or more shared processing blocks thereby significantly reducing chip space and power requirements. Shared components include local oscillators, analog to digital converters, digital RX processing and digital baseband processing. In operation, multiple RX front end circuits, one for each desired wireless signal, generate a plurality of IF signals that are frequency multiplexed and combined to create a single combined IF signal. The combined IF signal is processed by a shared processing block. Digital baseband processing is performed on each receive signal to generate respective data outputs. Further, simultaneous full-duplex transmission and reception is performed using a single local oscillator. The phase/frequency modulation of the frequency synthesizer used in the TX is removed from the local oscillator signal for use in the receiver.
摘要翻译：一种使用频率复用和共享处理同时进行多信号接收和传输的新颖机制。可以使用一个或多个共享处理块来接收可能具有各种无线标准的多个RF信号，从而显着减少芯片空间和功率需求。共享组件包括本地振荡器，模数转换器，数字RX处理和数字基带处理。在操作中，针对每个期望的无线信号的多个RX前端电路产生频率多路复用并组合以产生单个组合IF信号的多个IF信号。组合的IF信号由共享处理块处理。对每个接收信号执行数字基带处理，以产生相应的数据输出。此外，使用单个本地振荡器执行同时的全双工发送和接收。在TX中使用的频率合成器的相位/频率调制从本地振荡器信号中去除，以在接收机中使用。

60. 发明授权

US08385476B2 Digital phase locked loop 有权
公开(公告)号：US08385476B2
公开(公告)日：2013-02-26
申请号：US10131523
申请日：2002-04-24
申请人： Robert B. Staszewski , Dirk Leipold
发明人： Robert B. Staszewski , Dirk Leipold
IPC分类号： H03D1/00 , H04L27/06
CPC分类号： H03L7/0992 , H03C3/0966 , H03K19/0016 , H03L7/08 , H03L7/085 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/099 , H03L7/0991 , H03L7/16 , H03L2207/50 , H04L7/0029 , H04L7/0331
摘要： A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.

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