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51. 发明授权

US08362803B2 Mode latching buffer circuit 有权
标题翻译：模式锁存缓冲电路
公开(公告)号：US08362803B2
公开(公告)日：2013-01-29
申请号：US13031176
申请日：2011-02-18
申请人： Peter J. Nicholas , John Christopher Kriz , Dipankar Bhattacharya , James John Bradley
发明人： Peter J. Nicholas , John Christopher Kriz , Dipankar Bhattacharya , James John Bradley
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , H03K3/356182
摘要： A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.
摘要翻译：电压转换器电路包括适于接收参考第一电压源的输入信号的输入级，适于与第二电压源连接并可操作以至少临时存储输入信号的逻辑状态的第一锁存电路，以及电压钳耦合在输入级和第一锁存电路之间。电压钳可用于将输入级两端的最大电压设定到规定的电平。电压转换器电路在形成在第一锁存电路和电压钳之间的结处的第一输出处产生第一输出信号。第二锁存电路以反馈配置连接到第一输出端。第二锁存电路用于将第一输出信号的逻辑状态保持为至少提供给第二锁存电路的第一控制信号的函数，而与第一电压源的状态无关。

52. 发明申请

US20120212256A1 Mode Latching Buffer Circuit 有权
标题翻译：模式锁存缓冲电路
公开(公告)号：US20120212256A1
公开(公告)日：2012-08-23
申请号：US13031176
申请日：2011-02-18
申请人： Peter J. Nicholas , John Christopher Kriz , Dipankar Bhattacharya , James John Bradley
发明人： Peter J. Nicholas , John Christopher Kriz , Dipankar Bhattacharya , James John Bradley
IPC分类号： H03K19/0175 , H03K5/08
CPC分类号： H03K19/018521 , H03K3/356182
摘要： A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.
摘要翻译：电压转换器电路包括适于接收参考第一电压源的输入信号的输入级，适于与第二电压源连接并可操作以至少临时存储输入信号的逻辑状态的第一锁存电路，以及电压钳耦合在输入级和第一锁存电路之间。电压钳可用于将输入级两端的最大电压设定到规定的电平。电压转换器电路在形成在第一锁存电路和电压钳之间的结处的第一输出处产生第一输出信号。第二锁存电路以反馈配置连接到第一输出端。第二锁存电路用于将第一输出信号的逻辑状态保持为至少提供给第二锁存电路的第一控制信号的函数，而与第一电压源的状态无关。

53. 发明申请

US20060092589A1 Electrostatic discharge protection in a semiconductor device 有权
公开(公告)号：US20060092589A1
公开(公告)日：2006-05-04
申请号：US10977881
申请日：2004-10-29
申请人： Dipankar Bhattacharya , John Kriz , Bernard Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , John Kriz , Bernard Morris , Yehuda Smooha
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： An ESD protection circuit for protecting a circuit from an ESD event occurring between a first voltage supply node and a second voltage supply node associated with the circuit to be protected includes an MOS device having a gate terminal, a first source/drain terminal and a second source/drain terminal. The first source/drain terminal is connected to the first voltage supply node and the second source/drain terminal is connected to the second voltage supply node. The ESD protection circuit further includes a trigger circuit coupled to the gate terminal of the MOS device. The trigger circuit is configured to generate a control signal at the gate terminal of the MOS device for activating the MOS device during the ESD event. At least a portion of the trigger circuit is formed in a floating well which becomes biased to a voltage that is substantially equal to a first voltage when the first voltage is supplied to the first voltage supply node or to a second voltage when the second voltage is applied to the second voltage supply node, whichever voltage is greater.

54. 发明申请

US20060066381A1 Voltage level translator circuit with feedback 审中-公开
标题翻译：具有反馈电压电平转换电路
公开(公告)号：US20060066381A1
公开(公告)日：2006-03-30
申请号：US10956000
申请日：2004-09-30
申请人： Dipankar Bhattacharya , John Kriz , Brian Lacey , Bruce McNeill , Bernard Morris
发明人： Dipankar Bhattacharya , John Kriz , Brian Lacey , Bruce McNeill , Bernard Morris
IPC分类号： H03L5/00
CPC分类号： H03K3/356113 , H03K3/356008 , H03K17/223
摘要： A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal and a latch circuit for storing a signal at an output of the latch circuit which is representative of a logical state of the input signal. The latch circuit includes an input coupled to the input stage. The voltage level translator circuit further includes a feedback circuit coupled between the input and the output of the latch circuit. The feedback circuit is operative to maintain a desired logic state of the voltage level translator circuit when the second voltage supply powers up before the first voltage supply. In this manner, the voltage level translator circuit is configured to provide an output signal having a predictable logic state over a wide variation of PVT conditions and/or voltage supply ramp rates.
摘要翻译：用于将参考第一电压源的输入信号转换为参考第二电压源的输出信号的电压电平转换器电路包括用于接收输入信号的输入级和用于在锁存电路的输出端存储信号的锁存电路其代表输入信号的逻辑状态。锁存电路包括耦合到输入级的输入端。电压电平转换器电路还包括耦合在锁存电路的输入和输出之间的反馈电路。当第二电压源在第一电压供应之前加电时，反馈电路可操作以保持电压电平转换器电路的期望逻辑状态。以这种方式，电压电平转换器电路被配置为在PVT条件和/或电压提供斜坡率的宽泛变化上提供具有可预测逻辑状态的输出信号。

55. 发明申请

US20060044028A1 Programmable reset signal that is independent of supply voltage ramp rate 有权
标题翻译：独立于电源电压斜坡率的可编程复位信号
公开(公告)号：US20060044028A1
公开(公告)日：2006-03-02
申请号：US10925613
申请日：2004-08-25
申请人： Dipankar Bhattacharya , John Kriz , Duane Loeper , Antonio Marques
发明人： Dipankar Bhattacharya , John Kriz , Duane Loeper , Antonio Marques
IPC分类号： H03L7/00
CPC分类号： H03K17/223
摘要： A PUR circuit for generating a reset signal includes a first node for receiving a reference voltage and a second node for receiving a supply voltage that is referenced with respect to the reference voltage. The circuit further includes a voltage level detector coupled between the first node and a third node, the voltage level detector being configured to generate a first control signal at the third node. The voltage level detector includes a first transistor having a first threshold voltage associated therewith. A resistance element is coupled between the second node and the third node, the resistance element having a first resistance value associated therewith. The circuit also includes an inverter having an input coupled to the third node and having an output for generating a second control signal in response to the first control signal. The inverter includes a second transistor having a second threshold voltage associated therewith which is lower than the first threshold voltage. The voltage level detector is configured such that the first control signal is substantially equal to the supply voltage when the supply voltage is less than a first voltage, and the first control signal is equal to a second voltage when the supply voltage is substantially equal to or greater than the first voltage. The second voltage is less than a lower switching point of the inverter, the first voltage being based at least in part on the first threshold voltage, the reset signal being a function of the second control signal.
摘要翻译：用于产生复位信号的PUR电路包括用于接收参考电压的第一节点和用于接收相对于参考电压参考的电源电压的第二节点。电路还包括耦合在第一节点和第三节点之间的电压电平检测器，电压电平检测器被配置为在第三节点处产生第一控制信号。电压电平检测器包括具有与其相关联的第一阈值电压的第一晶体管。电阻元件耦合在第二节点和第三节点之间，电阻元件具有与之相关联的第一电阻值。该电路还包括具有耦合到第三节点并具有响应于第一控制信号产生第二控制信号的输出的反相器。逆变器包括具有与其相关联的第二阈值电压的第二晶体管，其低于第一阈值电压。电压电平检测器被配置为使得当电源电压小于第一电压时，第一控制信号基本上等于电源电压，并且当电源电压基本上等于或等于第一控制信号时，第一控制信号等于第二电压大于第一电压。第二电压小于逆变器的较低开关点，第一电压至少部分地基于第一阈值电压，复位信号是第二控制信号的函数。

56. 发明申请

US20050270065A1 Coms buffer having higher and lower voltage operation 审中-公开
标题翻译： Coms缓冲器具有更高和更低的电压操作
公开(公告)号：US20050270065A1
公开(公告)日：2005-12-08
申请号：US10859211
申请日：2004-06-03
申请人： Dipankar Bhattacharya , Brijendra Dobriyal , Bernard Morris
发明人： Dipankar Bhattacharya , Brijendra Dobriyal , Bernard Morris
IPC分类号： H03K3/00 , H03K17/0412 , H03K17/06 , H03K19/0175 , H03K19/0185
CPC分类号： H03K19/018585 , H03K17/04123 , H03K17/063 , H03K19/018521
摘要： A buffer design for an integrated circuit that not only recognizes, but improves upon the skew problem as described above that is particularly problematic in cases where the output buffer supply voltage is particularly close or the same as the voltage of the signals coming from the core of an IC. Translator-up circuits associated with output buffers are implemented in parallel with respective selective bypass circuits, allowing the translator-up circuit to be inserted into or removed from a signal path based on the voltage level of a signal received from the inner core and the voltage level required by the output buffer. When the voltage level of the “higher” voltage side is equal to the “lower” voltage signal level, the translator-up circuits are bypassed through selection by a selective bypass circuit. Thus, a selective bypass circuit is implemented together with a translator-up circuit to eliminate large signal skew, and to generally speed up circuit performance.
摘要翻译：一种用于集成电路的缓冲器设计，其不仅识别但改进了如上所述的偏斜问题，在输出缓冲器电源电压特别接近或相同于来自芯的信号的电压的情况下，这是特别有问题的一个IC 与输出缓冲器相关联的转换电路与相应的选择旁路电路并行实现，允许转换器升高电路基于从内核接收的信号的电压电平和电压插入或从信号路径中去除输出缓冲区所需的电平。当“较高”电压侧的电压电平等于“较低”电压信号电平时，通过选择旁路电路的选择旁路转换器电路。因此，选择性旁路电路与转换器升压电路一起实现，以消除大的信号偏移，并且通常加速电路性能。

57. 发明授权

US07720107B2 Aligning data in a wide, high-speed, source synchronous parallel link 有权
标题翻译：对齐数据在宽，高速，源同步并行链路
公开(公告)号：US07720107B2
公开(公告)日：2010-05-18
申请号：US10989703
申请日：2004-11-15
申请人： Dipankar Bhattacharya , Bangalore Priyadarshan , Jaushin Lee , François Gautier-Le Boulch
发明人： Dipankar Bhattacharya , Bangalore Priyadarshan , Jaushin Lee , François Gautier-Le Boulch
IPC分类号： H04J3/06 , G06F1/04
CPC分类号： G06F13/4291 , H04J3/0632 , H04L7/0008 , H04L7/041 , H04L25/14
摘要： A source-synchronous parallel interface divides a wide data bus into clock-groups including a sub-group of the data lines and a clock line carrying a copy of the transmit clock. The traces in a clock-group are located physically close together to minimize skew between the signals carried on the traces of the clock-group. Deskew logic on the receiver compensates for skew between received clock-group signals.
摘要翻译：源同步并行接口将宽数据总线分为时钟组，包括数据线的子组和携带传输时钟副本的时钟线。时钟组中的迹线物理上靠近在一起，以最小化时钟组迹线上携带的信号之间的偏移。接收机上的偏移校正逻辑补偿接收的时钟组信号之间的偏差。

58. 发明授权

US07139928B1 Method and system for providing redundancy within a network element 有权
标题翻译：在网元中提供冗余的方法和系统
公开(公告)号：US07139928B1
公开(公告)日：2006-11-21
申请号：US10273022
申请日：2002-10-17
申请人： Dipankar Bhattacharya , Michael Roy Smith , Kevin Morishige
发明人： Dipankar Bhattacharya , Michael Roy Smith , Kevin Morishige
IPC分类号： G06F11/00
CPC分类号： H04L49/557 , H04L49/65 , H04Q2213/13003 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13167 , H04Q2213/1334 , H04Q2213/13341
摘要： A network element is disclosed that provides redundancy within the network element that, in turn, provides fault tolerance for the failure of one or more processing units therein. In one embodiment, a network element according to the present invention includes N interface units, M processing units and a number of links. The value of N is an integer greater than 1. Each interface unit is coupled to L+1 processing units. The value of L is an integer greater than 0 and less than N, and the value of M equals N plus L. Each of the links is configured to couple one of the interface units and one of the processing units. Each of the interface units is configured to select one of the links that couples the interface unit and ones of the processing units, and the links include a primary link and a standby link.
摘要翻译：公开了一种在网络元件内提供冗余的网络元件，其进而为其中的一个或多个处理单元的故障提供容错。在一个实施例中，根据本发明的网元包括N个接口单元，M个处理单元和多个链路。 N的值是大于1的整数。每个接口单元耦合到L + 1处理单元。 L的值是大于0且小于N的整数，M的值等于N加L.每个链路被配置为耦合其中一个接口单元和一个处理单元。每个接口单元被配置为选择耦合接口单元和处理单元之一的链路之一，并且链路包括主链路和备用链路。

59. 发明授权

US07047385B1 High-speed memory for use in networking systems 有权
标题翻译：用于网络系统的高速内存
公开(公告)号：US07047385B1
公开(公告)日：2006-05-16
申请号：US10462866
申请日：2003-06-16
申请人： Dipankar Bhattacharya , Jeff Hirschman
发明人： Dipankar Bhattacharya , Jeff Hirschman
IPC分类号： G06F12/00
CPC分类号： G06F13/4291
摘要： A memory integrated circuit includes an array of high-speed memory blocks coupled to the address input interface and data output interface of the integrated circuit by address and data pipelines clocked at the same rate as the high-speed memory blocks. After an initial read latency, data is read from the memory at the same speed it is read from the high-speed memory blocks.
摘要翻译：存储器集成电路包括通过与高速存储器块以相同速率计时的地址和数据管线，耦合到集成电路的地址输入接口和数据输出接口的高速存储器阵列阵列。在初始读取延迟之后，以与从高速存储器块读取的速度相同的速度从存储器读取数据。

60. 发明授权

US5918072A System for controlling variable length PCI burst data using a dummy final data phase and adjusting the burst length during transaction 失效
标题翻译：用于使用虚拟最终数据相位来控制可变长度PCI突发数据的系统，并且在事务期间调整突发长度
公开(公告)号：US5918072A
公开(公告)日：1999-06-29
申请号：US531144
申请日：1995-09-18
申请人： Dipankar Bhattacharya
发明人： Dipankar Bhattacharya
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： A host-bus-to-PCI-bus bridge circuit waits until the PCI-bus clock cycle in which the PCI-bus data transfer corresponding to a current data write access on the originating bus actually takes place, before deciding whether a next data write access is pending on the originating bus and is burstable on the PCI-bus with the current data write access. If so, then the bridge continues the burst with the data of the new data write access. If not, the bridge terminates the PCI-bus burst write transaction by asserting IRDY# and negating FRAME# for the immediately subsequent PCI-bus clock cycle. A final data phase takes place on the PCI-bus in response to these actions, but all data transfer is inhibited because the bridge negates all of the byte-enable signals (BE#(3:0)). An increased likelihood results that successive data write accesses on the originating bus can be collected into a single burst transaction on the PCI-bus.
摘要翻译：主机总线到PCI总线桥接电路等待直到PCI总线时钟周期，其中PCI总线数据传输对应于始发总线上的当前数据写入访问实际上发生，然后才决定是否下一个数据写入访问在始发总线上正在等待，并且可以在PCI总线上使用当前的数据写访问进行突发。如果是这样，则桥接器继续使用新的数据写入访问的数据。如果不是，桥接器将通过断言IRDY＃终止PCI总线突发写入事务，并为紧随其后的PCI总线时钟周期取消FRAME＃。响应于这些动作，在PCI总线上进行最后的数据阶段，但由于桥接器否定了所有字节使能信号（BE＃（3：0）），所有数据传输都被禁止。增加的可能性导致始发总线上的连续数据写访问可以被收集到PCI总线上的单个突发事务中。

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