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51. 发明授权

US08195986B2 Method, system and computer program product for processing error information in a system 有权
标题翻译：用于处理系统中的错误信息的方法，系统和计算机程序产品
公开(公告)号：US08195986B2
公开(公告)日：2012-06-05
申请号：US12036745
申请日：2008-02-25
申请人： Patrick J. Meaney , Mark S. Farrell , Liyong Wang , Rebecca S. Wisniewski
发明人： Patrick J. Meaney , Mark S. Farrell , Liyong Wang , Rebecca S. Wisniewski
IPC分类号： G06F11/00
CPC分类号： G06F11/0769 , G06F11/0721
摘要： A system for processing errors in a processor comprising, a first register having a unique identifier operative to store a first error data, a processor operative to retrieve the first error data from the first register, associate the first error data with the unique identifier, and generate a first uniform error packet including the first error data and the unique identifier and a storage medium operative to store the first uniform error packet.
摘要翻译：一种用于处理处理器中的错误的系统，包括：第一寄存器，具有用于存储第一错误数据的唯一标识符;可操作以从第一寄存器检索第一错误数据的处理器将第一错误数据与唯一标识符相关联;以及产生包括第一错误数据和唯一标识符的第一均匀错误包，以及可操作地存储第一均匀错误包的存储介质。

52. 发明授权

US08135978B2 Performing a perform timing facility function instruction for sychronizing TOD clocks 有权
标题翻译：执行用于同步TOD时钟的执行定时设备功能指令
公开(公告)号：US08135978B2
公开(公告)日：2012-03-13
申请号：US12540261
申请日：2009-08-12
申请人： Eberhard Engler , Mark S. Farrell , Klaus Meissner , Ronald M. Smith, Sr. , Evangelyn K. Smith, legal representative , Mark A. Check
发明人： Eberhard Engler , Mark S. Farrell , Klaus Meissner , Ronald M. Smith, Sr. , Mark A. Check
IPC分类号： G06F1/04 , G04C11/00
CPC分类号： G06F1/14
摘要： A system, method and computer program product for performing a Perform Timing Facility (PTFF) instruction for steering a Time of Day (TOD) clock of the computer system for synchronizing the TOD clock with TOD clocks of other computer systems. The computer system comprises a memory; and, a processor in communications with the computer memory. The processor is capable of performing a PTFF instruction comprising: obtaining a function code specified in a first general register, the function code for identifying any one of a query function or a control function to be performed; obtaining, from a second general register, a memory address of a parameter block; responsive to the function code specifying a query function, storing timing information of the computer system in the parameter block according to the specified query function; responsive to the function code specifying a control function, using timing information obtained from the parameter block to perform the specified control function; and setting a condition code value indicating an outcome of the specified function.
摘要翻译：一种用于执行用于使TOD时钟与其他计算机系统的TOD时钟同步的计算机系统的时间（TOD）时钟的执行定时设备（PTFF）指令的系统，方法和计算机程序产品。计算机系统包括存储器; 以及与计算机存储器通信的处理器。处理器能够执行PTFF指令，包括：获得在第一通用寄存器中指定的功能代码，用于识别要执行的查询功能或控制功能中的任何一个的功能代码; 从第二通用寄存器获取参数块的存储器地址; 响应于指定查询功能的功能代码，根据指定的查询功能将计算机系统的定时信息存储在参数块中; 响应于指定控制功能的功能代码，使用从参数块获得的定时信息来执行指定的控制功能; 并设置指示指定功能的结果的条件代码值。

53. 发明授权

US08078843B2 Facilitating processing in a computing environment using an extended drain instruction 有权
标题翻译：在计算环境中利用扩展的漏极指令促进处理
公开(公告)号：US08078843B2
公开(公告)日：2011-12-13
申请号：US12023155
申请日：2008-01-31
申请人： Khary J. Alexander , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Timothy J. Slegel , Charles F. Webb
发明人： Khary J. Alexander , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F9/30
CPC分类号： G06F9/30079 , G06F9/30145 , G06F9/3867
摘要： An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired. The enhanced DRAIN instruction enables its use to be more granular and to have minimal impact with respect to each individual use.
摘要翻译：扩展DRAIN指令用于在计算环境中停止处理。该指令包括处理被停止的一个或多个处理阶段的指示。它还包括一个控制，允许根据需要使处理停滞在额外的周期。增强的DRAIN指令使其使用更细致，对每个用户的影响最小。

54. 发明申请

US20110296114A1 ATOMIC EXECUTION OVER ACCESSES TO MULTIPLE MEMORY LOCATIONS IN A MULTIPROCESSOR SYSTEM 有权
标题翻译：在多处理器系统中访问多个存储器位置的原子执行
公开(公告)号：US20110296114A1
公开(公告)日：2011-12-01
申请号：US12786787
申请日：2010-05-25
申请人： Mark S. Farrell , Jonathan T. Hsieh , Christian Jacobi , Timothy J. Slegel
发明人： Mark S. Farrell , Jonathan T. Hsieh , Christian Jacobi , Timothy J. Slegel
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F9/30043 , G06F9/30072 , G06F9/3834 , G06F9/528 , G06F12/0815 , G06F2212/62
摘要： A method and central processing unit supporting atomic access of shared data by a sequence of memory access operations. A processor status flag is reset. A processor executes, subsequent to the setting of the processor status flag, a sequence of program instructions with instructions accessing a subset of shared data contained within its local cache. During execution of the sequence of program instructions and in response to a modification by another processor of the subset of shared data, the processor status flag is set. Subsequent to the executing the sequence of program instructions and based upon the state of the processor status flag, either a first program processing or a second program processing is executed. In some examples the first program processing includes storing results data into the local cache and the second program processing includes discarding the results data.
摘要翻译：一种通过一系列存储器访问操作支持共享数据的原子访问的方法和中央处理单元。处理器状态标志被复位。在处理器状态标志的设置之后，处理器执行具有访问包含在其本地高速缓存中的共享数据的子集的指令的程序指令序列。在程序指令序列的执行期间，并且响应于另一个处理器对共享数据子集的修改，处理器状态标志被置位。在执行程序指令序列之后，并且基于处理器状态标志的状态，执行第一程序处理或第二程序处理。在一些示例中，第一程序处理包括将结果数据存储到本地高速缓存中，并且第二程序处理包括丢弃结果数据。

55. 发明授权

US07984275B2 Computer configuration virtual topology discovery and instruction therefore 有权
标题翻译：因此，计算机配置虚拟拓扑发现和指令
公开(公告)号：US07984275B2
公开(公告)日：2011-07-19
申请号：US12779232
申请日：2010-05-13
申请人： Mark S. Farrell , Charles W. Gainey, Jr. , Jeffrey P. Kubala , Donald W. Schmidt
发明人： Mark S. Farrell , Charles W. Gainey, Jr. , Jeffrey P. Kubala , Donald W. Schmidt
IPC分类号： G06F9/34
CPC分类号： H04L41/12 , G06F9/30003 , G06F9/45545 , G06F9/45558 , G06F9/5077 , G06F2009/45566
摘要： In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest configuration comprises a guest processor of the guest configuration fetching and executing a STORE SYSTEM INFORMATION instruction that obtains topology information of the computer configuration. The topology information comprising nesting information of processors of the configuration and the degree of dedication a host processor provides to a corresponding guest processor. The information is preferably stored in a single table in memory.
摘要翻译：在包括主处理器（主机CPU）的逻辑分区的主计算机系统中，用于发现客户配置的一个或多个客户处理器（客户CPU）的拓扑的设施和指令包括访客配置的来宾处理器，以访问和执行存储系统获取计算机配置的拓扑信息的信息指令。所述拓扑信息包括所述配置的处理器的嵌套信息和主处理器向对应的客户处理器提供的奉献程度。该信息优选地存储在存储器中的单个表中。

56. 发明授权

US07734900B2 Computer configuration virtual topology discovery and instruction therefore 有权
标题翻译：因此，计算机配置虚拟拓扑发现和指令
公开(公告)号：US07734900B2
公开(公告)日：2010-06-08
申请号：US11972802
申请日：2008-01-11
申请人： Mark S. Farrell , Charles W. Gainey, Jr. , Jeffrey P. Kubala , Donald W. Schmidt
发明人： Mark S. Farrell , Charles W. Gainey, Jr. , Jeffrey P. Kubala , Donald W. Schmidt
IPC分类号： G06F9/34
CPC分类号： H04L41/12 , G06F9/30003 , G06F9/45545 , G06F9/45558 , G06F9/5077 , G06F2009/45566
摘要： In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest configuration comprises a guest processor of the guest configuration fetching and executing a STORE SYSTEM INFORMATION instruction that obtains topology information of the computer configuration. The topology information comprising nesting information of processors of the configuration and the degree of dedication a host processor provides to a corresponding guest processor. The information is preferably stored in a single table in memory.
摘要翻译：在包括主处理器（主机CPU）的逻辑分区的主计算机系统中，用于发现客户配置的一个或多个客户处理器（客户CPU）的拓扑的设施和指令包括访客配置的访客处理器，其提取和执行存储系统获取计算机配置的拓扑信息的信息指令。所述拓扑信息包括所述配置的处理器的嵌套信息和主处理器向对应的客户处理器提供的奉献程度。该信息优选地存储在存储器中的单个表中。

57. 发明授权

US07712076B2 Register indirect access of program floating point registers by millicode 失效
标题翻译：通过millicode寄存器间接访问程序浮点寄存器
公开(公告)号：US07712076B2
公开(公告)日：2010-05-04
申请号：US11531301
申请日：2006-09-13
申请人： Steven R. Carlough , Mark S. Farrell , Eric M. Schwarz , Timothy J. Slegel , Charles F. Webb
发明人： Steven R. Carlough , Mark S. Farrell , Eric M. Schwarz , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F9/44
CPC分类号： G06F9/3017 , G06F9/35
摘要： Complex floating point instructions are executed under millicode control when it is not cost effective to implement its function in hardware. One of the disadvantages to executing complex instructions using millicode routines is that determining and accessing the instructions operands are costly for millicode performance. To determine what the source and target location are, the instruction text is parsed. Furthermore the millicode instruction stream must be modified to access the operand data from and write the result to the program registers specified by the complex floating point instruction. The invention overcomes these disadvantages by providing millicode with register indirect access to the program floating point registers.
摘要翻译：当在硬件中实现其功能不具有成本效益时，复杂的浮点指令在毫秒控制下执行。使用millicode例程执行复杂指令的一个缺点是确定和访问指令操作数对于millicode性能来说是昂贵的。要确定源和目标位置是什么，解释说明文本。此外，必须修改millicode指令流以访问操作数数据，并将结果写入由复杂浮点指令指定的程序寄存器。本发明通过向编程浮点寄存器提供寄存器间接访问的毫代码来克服这些缺点。

58. 发明申请

US20100095033A1 PERFORMING A CONFIGURATION VIRTUAL TOPOLOGY CHANGE AND INSTRUCTION THEREFORE 有权
标题翻译：执行配置虚拟拓扑变化及其指导
公开(公告)号：US20100095033A1
公开(公告)日：2010-04-15
申请号：US12636200
申请日：2009-12-11
申请人： Mark S. Farrell , Charles W. Gainey, JR. , Jeffrey P. Kubala , Donald W. Schmidt
发明人： Mark S. Farrell , Charles W. Gainey, JR. , Jeffrey P. Kubala , Donald W. Schmidt
IPC分类号： G06F13/00
CPC分类号： G06F9/5077 , G06F9/30003 , G06F9/44505 , G06F15/76
摘要： In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization related to the amount of a host CPU resource is provided to a guest CPU.
摘要翻译：在包括分配到客户配置的多个客体处理器（客户CPU）的主机处理器（主机CPU）的逻辑分区主机计算机系统中，执行拓扑功能指令由客户处理器执行，指定客户配置的拓扑变化。拓扑变化优选地改变客户CPU的极化，与提供给客户CPU的主机CPU资源量相关的极化。

59. 发明申请

US20080126759A1 Register Indirect Access of Program Floating Point Registers by Millicode 失效
标题翻译：通过Millicode寄存器间接访问程序浮点寄存器
公开(公告)号：US20080126759A1
公开(公告)日：2008-05-29
申请号：US11531301
申请日：2006-09-13
申请人： Steven R. Carlough , Mark S. Farrell , Eric M. Schwarz , Timothy J. Slegel , Charles F. Webb
发明人： Steven R. Carlough , Mark S. Farrell , Eric M. Schwarz , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F9/302
CPC分类号： G06F9/3017 , G06F9/35
摘要： Complex floating point instructions are executed under millicode control when it is not cost effective to implement its function in hardware. One of the disadvantages to executing complex instructions using millicode routines is that determining and accessing the instructions operands are costly for millicode performance. To determine what the source and target location are, the instruction text is parsed. Furthermore the millicode instruction stream must be modified to access the operand data from and write the result to the program registers specified by the complex floating point instruction. The invention overcomes these disadvantages by providing millicode with register indirect access to the program floating point registers.
摘要翻译：当在硬件中实现其功能不具有成本效益时，复杂的浮点指令在毫秒控制下执行。使用millicode例程执行复杂指令的一个缺点是确定和访问指令操作数对于millicode性能来说是昂贵的。要确定源和目标位置是什么，解释说明文本。此外，必须修改millicode指令流以访问操作数数据，并将结果写入由复杂浮点指令指定的程序寄存器。本发明通过向编程浮点寄存器提供寄存器间接访问的毫代码来克服这些缺点。

60. 发明授权

US5625808A Read only store as part of cache store for storing frequently used millicode instructions 失效
标题翻译：只读存储作为缓存存储的一部分，用于存储常用的millicode指令
公开(公告)号：US5625808A
公开(公告)日：1997-04-29
申请号：US455820
申请日：1995-05-31
申请人： Charles F. Webb , Mark S. Farrell , Barry W. Krumm , John S. Liptay , Jennifer S. A. Navarro , Steven B. Risch , Mark A. Check
发明人： Charles F. Webb , Mark S. Farrell , Barry W. Krumm , John S. Liptay , Jennifer S. A. Navarro , Steven B. Risch , Mark A. Check
IPC分类号： G06F9/318 , G06F9/38 , G06F9/22
CPC分类号： G06F9/3802 , G06F9/3017
摘要： A read only storage (ROS) array holds a small set of relatively simple millicode instructions; those millicode instruction routines which are most commonly called on in executing common application workloads. The millicode read only store is implemented as a portion of hardware system area (HSA) storage. The cache control includes a register which contains hardware system area address corresponding to the read only store address. When an instruction fetch request is received by the cache control, the absolute address of the instruction fetch request is compared with the read only store address in the register in parallel with the normal cache directory lookup. If the instruction fetch request matches the read only store address, the fetch is made from the read only store independently of the directory lookup result.
摘要翻译：只读存储（ROS）阵列包含一小组相对简单的millicode指令; 那些在执行常见应用程序工作负载中最常调用的那些millicode指令例程。 millicode只读存储器实现为硬件系统区域（HSA）存储的一部分。高速缓存控制包括一个寄存器，该寄存器包含与只读存储地址对应的硬件系统区域地址。当缓存控制接收到指令提取请求时，将指令提取请求的绝对地址与正常缓存目录查找并行地与寄存器中的只读存储地址进行比较。如果指令提取请求与只读存储地址相匹配，则从独立于目录查找结果的只读存储进行读取。

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