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51. 发明授权

US07443726B2 Systems for alternate row-based reading and writing for non-volatile memory 有权
标题翻译：用于非易失性存储器的替代行读和写的系统
公开(公告)号：US07443726B2
公开(公告)日：2008-10-28
申请号：US11321346
申请日：2005-12-29
申请人： Daniel C. Guterman
发明人： Daniel C. Guterman
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/3418 , G11C2211/5622
摘要： A set of storage elements is programmed beginning with a word line WLn adjacent a select gate line for the set. After programming the first word line, the next word line WLn+1 adjacent to the first word line is skipped and the next word line WLn+2 adjacent to WLn+1 is programmed. WLn+1 is then programmed. Programming continues according to the sequence {WLn+4, WLn+3, WLn+6, WLn+5, . . . } until all but the last word line for the set have been programmed. The last word line is then programmed. By programming in this manner, some of the word lines of the set (WLn+1, WLn+3, etc.) have no subsequently programmed neighboring word lines. The memory cells of these word lines will not experience any floating gate to floating gate coupling threshold voltage shift impact due to subsequently programmed neighboring memory cells. The word lines having no subsequently programmed neighbors are read without using offsets or compensations based on neighboring memory cells. The other word lines are read using compensations based on data states within both subsequently programmed neighboring word lines.
摘要翻译：一组存储元件从与集合的选择栅极线相邻的字线WLn开始被编程。在对第一字线进行编程之后，跳过与第一字线相邻的下一个字线WLn + 1，并对与WLn + 1相邻的下一个字线WLn + 2进行编程。然后编程WLn + 1。根据序列{WLn + 4，WLn + 3，WLn + 6，WLn + 5，...，。。 }直到所有集合的最后一个字线都被编程为止。然后编程最后一个字线。通过以这种方式进行编程，组（WLn + 1，WLn + 3等）的一些字线没有随后编程的相邻字线。这些字线的存储单元将不会经历由于随后编程的相邻存储单元而产生的任何漂浮栅极与浮栅耦合阈值电压偏移的影响。在不使用基于相邻存储单元的偏移或补偿的情况下读取没有随后编程的邻居的字线。使用基于随后编程的相邻字线内的数据状态的补偿来读取其他字线。

52. 发明授权

US07397698B2 Reducing floating gate to floating gate coupling effect 有权
标题翻译：降低浮栅耦合效应
公开(公告)号：US07397698B2
公开(公告)日：2008-07-08
申请号：US11735265
申请日：2007-04-13
申请人： Yupin Fong , Daniel C. Guterman
发明人： Yupin Fong , Daniel C. Guterman
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/16
摘要： For a non-volatile memory system, compressing the erase threshold voltage distribution into the lowest threshold voltage state will decrease the valid data threshold voltage window. Decreasing the valid data threshold voltage window reduces the floating gate to floating gate coupling effect. The compression can be performed as part of the erase process or part of the programming operation.
摘要翻译：对于非易失性存储器系统，将擦除阈值电压分布压缩到最低阈值电压状态将降低有效数据阈值电压窗口。降低有效的数据阈值电压窗口可以将浮栅减少到浮栅耦合效应。压缩可以作为擦除过程的一部分或编程操作的一部分来执行。

53. 发明授权

US07392358B2 Delivery of a message to a user of a portable data storage device as a condition of its use 有权
标题翻译：向便携式数据存储设备的用户传递消息作为其使用的条件
公开(公告)号：US07392358B2
公开(公告)日：2008-06-24
申请号：US11035701
申请日：2005-01-14
申请人： Jian Chen , Carlos J. Gonzalez , Daniel C. Guterman
发明人： Jian Chen , Carlos J. Gonzalez , Daniel C. Guterman
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F3/00 , G06F5/00 , G06Q30/00 , G07G1/14
CPC分类号： G06F12/1433 , G06F21/78 , G06F21/79 , G06F2221/2141 , G06Q30/0207 , G06Q30/0277
摘要： A memory card, flash memory drive or other removable re-programmable non-volatile memory device is configured so that at least part of the memory is not available for storage of user data until data of a message stored in the memory is at least read out by the user through a host device to which the memory device is connected. The message may be an advertisement, instructions on using the memory device, or the like, to which the user is at least exposed as a condition of having the full capacity of the memory card available thereafter for use by him or her.
摘要翻译：配置存储卡，闪速存储器驱动器或其他可移动可重新编程的非易失性存储器件，使得至少部分存储器不可用于存储用户数据，直到存储在存储器中的消息的数据至少被读出由用户通过与存储设备连接的主机设备。该消息可以是用户至少暴露于其中的广告，关于使用存储设备的指示等等，作为具有可供其使用的存储卡的全部容量的条件。

54. 发明申请

US20080130364A1 Novel Multi-State Memory 审中-公开
公开(公告)号：US20080130364A1
公开(公告)日：2008-06-05
申请号：US12016045
申请日：2008-01-17
申请人： Daniel C. Guterman , Yupin Kawing Fong
发明人： Daniel C. Guterman , Yupin Kawing Fong
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0425 , G11C16/0441 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/349 , G11C16/3495 , G11C27/005 , G11C29/00 , G11C29/76 , G11C2211/5634 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

55. 发明授权

US07360136B2 Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data 有权
标题翻译：通过使用有关存储数据质量的信息，提高纠错码的有效性和操作多级存储器系统
公开(公告)号：US07360136B2
公开(公告)日：2008-04-15
申请号：US10866554
申请日：2004-06-10
申请人： Daniel C. Guterman , Stephen Jeffrey Gross , Geoffrey S. Gongwer
发明人： Daniel C. Guterman , Stephen Jeffrey Gross , Geoffrey S. Gongwer
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G11C16/3418 , G06F11/1012 , G06F11/1072 , G11C11/56 , G11C11/5621 , G11C16/3431 , G11C29/00 , G11C29/42 , G11C29/76 , G11C2029/0411
摘要： The quality of data stored in a memory system is assessed by different methods, and the memory system is operated according to the assessed quality. The data quality can be assessed during read operations. Subsequent use of an Error Correction Code can utilize the quality indications to detect and reconstruct the data with improved effectiveness. Alternatively, a statistics of data quality can be constructed and digital data values can be associated in a modified manner to prevent data corruption. In both cases the corrective actions can be implemented specifically on the poor quality data, according to suitably chosen schedules, and with improved effectiveness because of the knowledge provided by the qualify indications. These methods can be especially useful in high-density memory systems constructed of multi-level storage memory cells.
摘要翻译：通过不同的方法评估存储在存储器系统中的数据的质量，并且根据评估的质量操作存储器系统。在读取操作期间可以评估数据质量。随后使用纠错码可以利用质量指示来提高检测和重建数据的效率。或者，可以构建数据质量的统计，并且可以以修改的方式将数字数据值相关联以防止数据损坏。在这两种情况下，根据适当选择的时间表，纠正措施可以针对质量差的数据进行具体实施，并且由于资格指示提供的知识，可以提高效率。这些方法对于由多级存储单元构成的高密度存储器系统尤其有用。

56. 发明授权

US07345934B2 Multi-state memory 有权
标题翻译：多状态存储器
公开(公告)号：US07345934B2
公开(公告)日：2008-03-18
申请号：US11105855
申请日：2005-04-14
申请人： Daniel C. Guterman , Yupin Kawing Fong
发明人： Daniel C. Guterman , Yupin Kawing Fong
IPC分类号： G11C7/00
CPC分类号： H01L27/115 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0425 , G11C16/0441 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/349 , G11C16/3495 , G11C27/005 , G11C29/00 , G11C29/76 , G11C2211/5634 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.
摘要翻译：通过灵活，自我一致和自适应的检测方式实现了最大化的多状态压缩和更多的记忆状态容忍度，涵盖了广泛的动态范围。对于高密度多态编码，这种方法接近完全模拟处理，决定了模拟技术，包括A到D型转换，以重构和处理数据。根据本发明的教导，以高保真度读取存储器阵列，而不是提供实际的最终数字数据，而是提供准确地反映模拟存储状态的原始数据，哪些信息被发送到存储器控制器用于分析和检测实际的最终数字数据。

57. 发明授权

US07342279B2 Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements 有权
公开(公告)号：US07342279B2
公开(公告)日：2008-03-11
申请号：US11075423
申请日：2005-03-07
申请人： Eliyahou Harari , George Samachisa , Jack H. Yuan , Daniel C. Guterman
发明人： Eliyahou Harari , George Samachisa , Jack H. Yuan , Daniel C. Guterman
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , B82Y10/00 , G11C11/5671 , G11C16/0466 , G11C16/0475 , G11C16/0483 , G11C16/0491 , G11C2216/06 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/4234 , H01L29/7923 , Y10S438/947
摘要： Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.

58. 发明授权

US07301812B2 Boosting to control programming of non-volatile memory 有权
标题翻译：促进控制非易失性存储器的编程
公开(公告)号：US07301812B2
公开(公告)日：2007-11-27
申请号：US11392901
申请日：2006-03-29
申请人： Daniel C. Guterman , Nima Mokhlesi , Yupin Fong
发明人： Daniel C. Guterman , Nima Mokhlesi , Yupin Fong
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/12 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3454 , G11C16/3459
摘要： A system is disclosed for programming non-volatile memory with greater precision. In one embodiment, the system includes applying a first phase of a boosting signal to one or more unselected word lines for a set of NAND strings, applying a programming level to selected bit lines of the NAND strings while applying the first phase of the boosting signal, and applying an inhibit level to unselected bit lines of the NAND strings while applying the first phase of the boosting signal. Subsequently, a second phase of the boosting signal is applied to the one or more unselected word lines and the signal(s) on the selected bit lines are changed by applying the inhibit level to the selected bit lines so that NAND strings associated with the selected bit lines will be boosted by the second phase of the boosting signal. A program voltage signal is applied to a selected word line in order to program storage elements connected to the selected word line.
摘要翻译：公开了一种更精确地编程非易失性存储器的系统。在一个实施例中，该系统包括将一个升压信号的第一相位应用于一组NAND串的一个或多个未选字线，将编程电平施加到NAND串的选定位线，同时施加升压信号的第一相位并且在施加升压信号的第一相位时将禁止电平施加到NAND串的未选位线。随后，将升压信号的第二相位施加到一个或多个未选字线，并且通过将所述禁止电平施加到所选择的位线来改变所选位线上的信号，使得与所选择的位线相关联的NAND串位线将由升压信号的第二阶段提升。将程序电压信号施加到所选择的字线，以便编程连接到所选字线的存储元件。

59. 发明授权

US07187592B2 Multi-state memory 有权
标题翻译：多状态存储器
公开(公告)号：US07187592B2
公开(公告)日：2007-03-06
申请号：US10921450
申请日：2004-08-18
申请人： Daniel C. Guterman , Yupin Kawing Fong
发明人： Daniel C. Guterman , Yupin Kawing Fong
IPC分类号： G11C7/10
CPC分类号： H01L27/115 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0425 , G11C16/0441 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/349 , G11C16/3495 , G11C27/005 , G11C29/00 , G11C29/76 , G11C2211/5634 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.
摘要翻译：通过灵活，自我一致和自适应的检测方式实现了最大化的多状态压缩和更多的记忆状态容忍度，涵盖了广泛的动态范围。对于高密度多态编码，这种方法接近完全模拟处理，决定了模拟技术，包括A到D型转换，以重构和处理数据。根据本发明的教导，以高保真度读取存储器阵列，而不是提供实际的最终数字数据，而是提供准确地反映模拟存储状态的原始数据，哪些信息被发送到存储器控制器用于分析和检测实际的最终数字数据。

60. 发明授权

US07177195B2 Reducing the effects of noise in non-volatile memories through multiple reads 有权
标题翻译：通过多次读取降低非易失性存储器中噪声的影响
公开(公告)号：US07177195B2
公开(公告)日：2007-02-13
申请号：US11191823
申请日：2005-07-27
申请人： Carlos J. Gonzalez , Daniel C. Guterman
发明人： Carlos J. Gonzalez , Daniel C. Guterman
IPC分类号： G11C11/34
CPC分类号： G11C7/106 , G11C7/1006 , G11C7/1051 , G11C16/12 , G11C16/26 , G11C16/28 , G11C16/3454 , G11C16/3459 , G11C2013/0057
摘要： Storage elements are read multiple times and the results are accumulated and averaged for each storage element to reduce the effects of noise or other transients in the storage elements and associated circuits that may adversely affect the quality of the read. Several techniques may be employed, including: A full read and transfer of the data from the storage device to the controller device for each iteration, with averaging performed by the controller; a full read of the data for each iteration, with the averaging performed by the storage device, and no transfer to the controller until the final results are obtained; one full read followed by a number of faster re-reads exploiting the already established state information to avoid a full read, followed by an intelligent algorithm to guide the state at which the storage element is sensed. These techniques may be used as the normal mode of operation, or invoked upon exception condition, depending on the system characteristics. A similar form of signal averaging may be employed during the verify phase of programming. An embodiment of this technique would use a peak-detection scheme. In this scenario, several verify checks are performed at the state prior to deciding if the storage element has reached the target state. If some predetermined portion of the verifies fail, the storage element receives additional programming. These techniques allow the system to store more states per storage element in the presence of various sources of noise.
摘要翻译：存储元件被读取多次，并且对于每个存储元件累积和平均结果，以减少可能不利地影响读取质量的存储元件和相关电路中的噪声或其他瞬变的影响。可以采用几种技术，其中包括：由控制器对平均数据进行每次迭代从存储设备到控制器设备的完整读取和传输; 对每次迭代的数据进行完全读取，并由存储设备进行平均，并且在获得最终结果之前不转移到控制器; 一次完全读取，然后利用已建立的状态信息进行多次更快的重新读取，以避免完全读取，随后是引导存储元件被感测的状态的智能算法。这些技术可以用作正常操作模式，或者根据异常情况被调用，这取决于系统特性。可以在编程的验证阶段期间采用类似形式的信号平均。该技术的实施例将使用峰值检测方案。在这种情况下，在决定存储元件是否达到目标状态之前，先在状态下执行多个验证检查。如果验证的一些预定部分失败，则存储元件接收另外的编程。这些技术允许系统在存在各种噪声源的情况下存储每个存储元件的更多状态。

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