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51. 发明申请

US20050030792A1 METHOD FOR PROGRAMMING AND ERASING AN NROM CELL 有权
标题翻译： NRM细胞编程和消除方法
公开(公告)号：US20050030792A1
公开(公告)日：2005-02-10
申请号：US10636173
申请日：2003-08-07
申请人： Andrei Mihnea
发明人： Andrei Mihnea
IPC分类号： G11C16/04 , G11C16/10 , G11C11/34
CPC分类号： G11C16/0475 , G11C16/0466 , G11C16/10
摘要： A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions, and a ground potential to the remaining source/drain region. In order to erase the NROM cell, a constant voltage is coupled to the gate input. A constant positive current is input to one of the source/drain regions. The remaining source/drain region is either allowed to float, is coupled to a ground potential, or is coupled to the first source/drain region
摘要翻译：氮化物只读存储器（NROM）单元可以通过向栅极输入施加斜坡电压，对两个源极/漏极区中的一个施加恒定电压，并将剩余的源极/漏极区的接地电位编程。为了擦除NROM单元，将恒定电压耦合到栅极输入端。恒定的正电流被输入到源/漏区之一。剩余的源极/漏极区域被允许浮动，耦合到接地电位，或耦合到第一源极/漏极区域

52. 发明授权

US06795348B2 Method and apparatus for erasing flash memory 有权
标题翻译：擦除闪存的方法和装置
公开(公告)号：US06795348B2
公开(公告)日：2004-09-21
申请号：US10159885
申请日：2002-05-29
申请人： Andrei Mihnea , Chun Chen
发明人： Andrei Mihnea , Chun Chen
IPC分类号： G11C700
CPC分类号： G11C16/16 , G11C16/08 , G11C16/14 , H01L27/115
摘要： Method and apparatus for the erase of non-volatile memory in which holes trapped in the tunnel oxide are reduced.
摘要翻译：用于擦除其中困在隧道氧化物中的空穴减少的非易失性存储器的方法和装置。

53. 发明授权

US08841648B2 Multi-level memory arrays with memory cells that employ bipolar storage elements and methods of forming the same 有权
标题翻译：具有使用双极存储元件的存储器单元的多级存储器阵列及其形成方法
公开(公告)号：US08841648B2
公开(公告)日：2014-09-23
申请号：US12904802
申请日：2010-10-14
申请人： Yung-Tin Chen , Andrei Mihnea , Roy E. Scheuerlein , Luca Fasoli
发明人： Yung-Tin Chen , Andrei Mihnea , Roy E. Scheuerlein , Luca Fasoli
IPC分类号： H01L47/00 , H01L45/00 , H01L27/24 , G11C13/00 , G11C11/56
CPC分类号： H01L27/2481 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.
摘要翻译：在一些实施例中，提供了一种存储器阵列，其包括（1）具有（a）第一导电线的第一存储器单元; （b）形成在第一导线之上的第一双极存储元件; 和（c）形成在所述第一双极存储元件上方的第二导线; 以及（2）形成在所述第一存储单元上方的第二存储单元，并且具有（a）形成在所述第二导线上方的第二双极存储元件; 和（b）形成在第二双极存储元件上方的第三导线。第一和第二存储单元共享第二导线; 第一双极存储元件在第一存储单元内具有第一存储元件极性取向; 所述第二双极存储元件在所述第二存储单元内具有第二存储元件极性取向; 并且第二存储元件极性取向与第一存储元件极性取向相反。提供了许多其他方面。

54. 发明授权

US08624293B2 Carbon/tunneling-barrier/carbon diode 有权
标题翻译：碳/隧道势垒/碳二极管
公开(公告)号：US08624293B2
公开(公告)日：2014-01-07
申请号：US12639840
申请日：2009-12-16
申请人： Abhijit Bandyopadhyay , Franz Kreupl , Andrei Mihnea , Li Xiao
发明人： Abhijit Bandyopadhyay , Franz Kreupl , Andrei Mihnea , Li Xiao
IPC分类号： H01L29/66
CPC分类号： H01L45/00 , H01L27/2418 , H01L27/2463 , H01L29/16 , H01L29/88
摘要： A carbon/tunneling-barrier/carbon diode and method for forming the same are disclosed. The carbon/tunneling-barrier/carbon may be used as a steering element in a memory array. Each memory cell in the memory array may include a reversible resistivity-switching element and a carbon/tunneling-barrier/carbon diode as the steering element. The tunneling-barrier may include a semiconductor or an insulator. Thus, the diode may be a carbon/semiconductor/carbon diode. The semiconductor in the diode may be intrinsic or doped. The semiconductor may be depleted when the diode is under equilibrium conditions. For example, the semiconductor may be lightly doped such that the depletion region extends from one end of the semiconductor region to the other end. The diode may be a carbon/insulator/carbon diode.
摘要翻译：公开了一种碳/隧道势垒/碳二极管及其形成方法。碳/隧道势垒/碳可以用作存储器阵列中的转向元件。存储器阵列中的每个存储单元可以包括可逆电阻率开关元件和作为转向元件的碳/隧道势垒/碳二极管。隧道势垒可以包括半导体或绝缘体。因此，二极管可以是碳/半导体/碳二极管。二极管中的半导体可以是固有的或掺杂的。当二极管处于平衡条件下时，半导体可能耗尽。例如，半导体可以被轻掺杂，使得耗尽区从半导体区的一端延伸到另一端。二极管可以是碳/绝缘体/碳二极管。

55. 发明授权

US08520425B2 Resistive random access memory with low current operation 有权
标题翻译：具有低电流运行的电阻式随机存取存储器
公开(公告)号：US08520425B2
公开(公告)日：2013-08-27
申请号：US13424131
申请日：2012-03-19
申请人： Li Xiao , Chandu Gorla , Abhijit Bandyopadhyay , Andrei Mihnea
发明人： Li Xiao , Chandu Gorla , Abhijit Bandyopadhyay , Andrei Mihnea
IPC分类号： G11C11/00 , G11C13/0002
CPC分类号： G11C13/0007 , G11C5/02 , G11C8/10 , G11C13/0023 , G11C13/0069 , G11C13/0097 , G11C2013/0073 , G11C2013/0083 , G11C2213/32 , G11C2213/33 , G11C2213/71 , G11C2213/72 , G11C2213/76 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/146
摘要： A memory cell in a 3-D read and write memory device has two bipolar resistance-switching layers with different respective switching currents. A low current resistance-switching layer can be switched in set and reset processes while a high current resistance-switching layer remains in a reset state and acts as a protection resistor to prevent excessively high currents on the low current resistance-switching layer. The low and high current resistance-switching layers can be of the same material such as a metal oxide, where the layers differ in terms of thickness, doping, leakiness, metal richness or other variables. Or, the low and high current resistance-switching layers can be of different materials, having one or more layers each. The high current resistance-switching layer can have a switching current which is greater than a switching current of the low current resistance-switching layer by a factor of at least 1.5 or 2.0, for instance.
摘要翻译： 3-D读写存储器件中的存储单元具有两个具有不同开关电流的双极性电阻切换层。低电流电阻切换层可以在置位和复位过程中被切换，而高电流电阻切换层保持复位状态，并且作为保护电阻来防止低电流电阻切换层上的过大电流。低电流和高电流电阻切换层可以是相同的材料，例如金属氧化物，其中层的厚度，掺杂，泄漏，金属浓度等变化不同。或者，低电流和高电流电阻切换层可以是不同的材料，每个具有一个或多个层。高电流电阻切换层例如可以具有比低电流电阻切换层的开关电流大至少1.5或2.0的开关电流。

56. 发明申请

US20120091419A1 MEMORY CELLS HAVING STORAGE ELEMENTS THAT SHARE MATERIAL LAYERS WITH STEERING ELEMENTS AND METHODS OF FORMING THE SAME 有权
标题翻译：具有与转向元件共享材料层的存储元件的存储单元及其形成方法
公开(公告)号：US20120091419A1
公开(公告)日：2012-04-19
申请号：US12905047
申请日：2010-10-14
申请人： Yung-Tin Chen , Chuanbin Pan , Andrei Mihnea , Steven Maxell , Kun Hou
发明人： Yung-Tin Chen , Chuanbin Pan , Andrei Mihnea , Steven Maxell , Kun Hou
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L45/146 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1616 , Y10S438/957
摘要： In some embodiments, a memory cell is provided that includes a storage element formed from an MIM stack including (1) a first conductive layer; (2) an RRS layer formed above the first conductive layer; and (3) a second conductive layer formed above the RRS layer, at least one of the first and second conductive layers comprising a first semiconductor material layer. The memory cell includes a steering element coupled to the storage element, the steering element formed from the first semiconductor material layer of the MIM stack and one or more additional material layers. Numerous other aspects are provided.
摘要翻译：在一些实施例中，提供了一种存储单元，其包括由MIM堆叠形成的存储元件，所述存储元件包括：（1）第一导电层; （2）形成在第一导电层上方的RRS层; 和（3）形成在RRS层之上的第二导电层，第一和第二导电层中的至少一个包括第一半导体材料层。存储单元包括耦合到存储元件的操纵元件，由MIM堆叠的第一半导体材料层形成的操纵元件和一个或多个附加材料层。提供了许多其他方面。

57. 发明申请

US20110140064A1 CARBON/TUNNELING-BARRIER/CARBON DIODE 有权
标题翻译：碳/隧道障碍物/碳二极管
公开(公告)号：US20110140064A1
公开(公告)日：2011-06-16
申请号：US12639840
申请日：2009-12-16
申请人： Abhijit Bandyopadhyay , Franz Kreupl , Andrei Mihnea , Li Xiao
发明人： Abhijit Bandyopadhyay , Franz Kreupl , Andrei Mihnea , Li Xiao
IPC分类号： H01L47/00 , H01L29/885 , H01L21/04 , H01L29/861
CPC分类号： H01L45/00 , H01L27/2418 , H01L27/2463 , H01L29/16 , H01L29/88
摘要： A carbon/tunneling-barrier/carbon diode and method for forming the same are disclosed. The carbon/tunneling-barrier/carbon may be used as a steering element in a memory array. Each memory cell in the memory array may include a reversible resistivity-switching element and a carbon/tunneling-barrier/carbon diode as the steering element. The tunneling-barrier may include a semiconductor or an insulator. Thus, the diode may be a carbon/semiconductor/carbon diode. The semiconductor in the diode may be intrinsic or doped. The semiconductor may be depleted when the diode is under equilibrium conditions. For example, the semiconductor may be lightly doped such that the depletion region extends from one end of the semiconductor region to the other end. The diode may be a carbon/insulator/carbon diode.
摘要翻译：公开了一种碳/隧道势垒/碳二极管及其形成方法。碳/隧道势垒/碳可以用作存储器阵列中的转向元件。存储器阵列中的每个存储单元可以包括可逆电阻率开关元件和作为转向元件的碳/隧道势垒/碳二极管。隧道势垒可以包括半导体或绝缘体。因此，二极管可以是碳/半导体/碳二极管。二极管中的半导体可以是固有的或掺杂的。当二极管处于平衡条件下时，半导体可能耗尽。例如，半导体可以被轻掺杂，使得耗尽区从半导体区的一端延伸到另一端。二极管可以是碳/绝缘体/碳二极管。

58. 发明申请

US20110089391A1 PUNCH-THROUGH DIODE STEERING ELEMENT 有权
标题翻译： PUNCH-THROUGH二极管转向元件
公开(公告)号：US20110089391A1
公开(公告)日：2011-04-21
申请号：US12582509
申请日：2009-10-20
申请人： Andrei Mihnea , Deepak C. Sekar , George Samachisa , Roy Scheuerlein , Li Xiao
发明人： Andrei Mihnea , Deepak C. Sekar , George Samachisa , Roy Scheuerlein , Li Xiao
IPC分类号： H01L29/861 , H01L45/00 , H01L21/70
CPC分类号： G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2213/32 , G11C2213/34 , G11C2213/72 , H01L27/24
摘要： A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P−/N+ device or a P+/N−/P+ device.
摘要翻译：描述了一种用于形成使用穿通二极管作为与可逆电阻率切换元件串联的转向元件的存储系统的存储系统和方法。穿通二极管允许交叉点存储器阵列的双极性操作。穿通二极管可具有对称的非线性电流/电压关系。穿通二极管在选择的电池的高偏压下具有高电流，对于未选择的电池，在低偏压下具有低泄漏电流。因此，它与具有电阻式开关元件的交叉点存储器阵列中的双极开关兼容。穿通二极管可以是N + / P- / N +器件或P + / N- / P +器件。

59. 发明申请

US20110032768A1 ERASE DEGRADATION REDUCTION IN NON-VOLATILE MEMORY 有权
标题翻译：消除非易失性存储器中的降解
公开(公告)号：US20110032768A1
公开(公告)日：2011-02-10
申请号：US12906497
申请日：2010-10-18
申请人： Andrei Mihnea , William Kueber
发明人： Andrei Mihnea , William Kueber
IPC分类号： G11C16/14 , G11C16/34
CPC分类号： G11C16/0483 , G11C16/16 , G11C16/344
摘要： Methods for erasing a memory device and memory systems are provided, such as those including a non-volatile memory device is erased by using an intermediate erase step prior to a normal erase step. The intermediate erase step is comprised of an erase pulse voltage, applied to the semiconductor well of the selected memory block of memory cells, while edge rows of memory cells are biased at a low positive voltage (e.g., 0.2-2V). An erase verify operation is then performed. If the selected memory block is not erased, a normal memory erase step is then performed in which the same erase pulse voltage is used but all of the rows are biased at ground potential as in a normal erase step. If the memory block is still fails the erase verify operation, the erase pulse voltage is increased and the process repeated.
摘要翻译：提供了用于擦除存储器件和存储器系统的方法，诸如包括非易失性存储器件的那些方法在通常擦除步骤之前通过使用中间擦除步骤被擦除。中间擦除步骤包括施加到存储器单元的所选存储块的半导体阱的擦除脉冲电压，而边沿行的存储器单元被偏置在低正电压（例如，0.2-2V）。然后执行擦除验证操作。如果所选择的存储器块未被擦除，则执行正常的存储器擦除步骤，其中使用相同的擦除脉冲电压，但是所有行都像正常擦除步骤那样被偏置在地电位。如果存储器块仍然失效，擦除验证操作，擦除脉冲电压就会增加，重复处理。

60. 发明授权

US07885091B2 Limited charge delivery for programming non-volatile storage elements 有权
标题翻译：用于编程非易失性存储元件的有限充电
公开(公告)号：US07885091B2
公开(公告)日：2011-02-08
申请号：US12472074
申请日：2009-05-26
申请人： Andrei Mihnea , Luca Fasoli
发明人： Andrei Mihnea , Luca Fasoli
IPC分类号： G11C11/00
CPC分类号： G11C5/145 , G11C8/12 , G11C8/18 , G11C13/0038 , G11C2213/71 , G11C2213/72
摘要： A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and a circuit for detecting the setting and resetting of the reversible resistance-switching elements. In one aspect a circuit that has one or more clock inputs is run for a predetermined number of clock cycles. The circuit generates an amount of charge over the predetermined number of clock cycles. At most the amount of charge is provided to non-volatile storage element to program the non-volatile storage element. It is determined whether the non-volatile storage element is programmed to a desired state as a result of providing at most the amount of charge to the non-volatile storage element. Techniques disclosed herein can be applied to program memory cells other than memory cells with reversible resistance-switching elements.
摘要翻译：存储器系统包括衬底，衬底上的控制电路，包括具有可逆电阻切换元件的多个存储单元的三维存储器阵列（衬底上方），以及用于检测可逆电阻的设置和复位的电路开关元件在一个方面，具有一个或多个时钟输入的电路运行预定数量的时钟周期。电路在预定数量的时钟周期内产生一定量的电荷。最多将充电量提供给非易失性存储元件以对非易失性存储元件进行编程。作为对非易失性存储元件的充电量最多提供的结果，确定非易失性存储元件是否被编程到期望状态。本文公开的技术可以应用于具有可逆电阻切换元件的存储单元以外的程序存储单元。

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