会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 55. 发明授权
    • Integrated circuit process monitoring and metrology system
    • 集成电路过程监控与计量系统
    • US06964924B1
    • 2005-11-15
    • US09952790
    • 2001-09-11
    • Peter A. BurkeEric J. KirchnerJames R. B. Elmer
    • Peter A. BurkeEric J. KirchnerJames R. B. Elmer
    • H01L21/302H01L21/3105H01L21/66H01L21/76H01L23/544
    • H01L22/34H01L21/31053
    • A method for monitoring polishing process parameters for an integrated circuit structure on a substrate. A first metrology site is constructed on the substrate. The first metrology site represents a design extreme of a high density integrated circuit structure. The first metrology site is formed by placing a relatively small horizontal surface area trench within a relatively large surface area field of a polish stop material. A second metrology site is also constructed on the substrate. The second metrology site represents a design extreme of a low density integrated circuit structure. The second metrology site is formed by placing a relatively large horizontal surface area trench within a relatively small surface area field of a polish stop material. The substrate is covered with a layer of an insulating material, thereby at least filling the trenches. A target thickness of the insulating material necessary to leave the trenches substantially filled to a top surface of the field of polish stop material is calculated. The substrate is polished until a first thickness of the insulating material in the trench of the first metrology site is no more than the target thickness. A second thickness of the insulating material in the trench of the second metrology site is measured, and values based on the first thickness and the second thickness are monitored as the polishing process parameters for the integrated circuit structure.
    • 一种用于监测基板上的集成电路结构的抛光工艺参数的方法。 第一个计量站点被构建在基板上。 第一个测量站点代表了高密度集成电路结构的设计极限。 第一计量站点是通过在抛光停止材料的相对大的表面区域内放置相对较小的水平表面区域沟槽而形成的。 第二个计量站点也在基板上构建。 第二个测量站点是低密度集成电路结构的设计极限。 第二计量站点通过在抛光停止材料的相对小的表面区域内放置相对较大的水平表面区域沟槽而形成。 衬底被绝缘材料层覆盖,从而至少填充沟槽。 计算出将沟槽基本上填充到抛光停止材料领域的顶表面所需的绝缘材料的目标厚度。 抛光衬底直到第一测量点的沟槽中的绝缘材料的第一厚度不超过目标厚度。 测量第二测量位置的沟槽中的绝缘材料的第二厚度,并且监测基于第一厚度和第二厚度的值作为用于集成电路结构的抛光工艺参数。
    • 56. 发明授权
    • Polishing pads for chemical mechanical planarization
    • 抛光垫用于化学机械平面化
    • US06860802B1
    • 2005-03-01
    • US09608537
    • 2000-06-30
    • Arun VishwanathanDavid B. JamesLee Melbourne CookPeter A. BurkeDavid Shidner
    • Arun VishwanathanDavid B. JamesLee Melbourne CookPeter A. BurkeDavid Shidner
    • B24B37/04B24D3/28B24D13/14B24D11/00
    • B24B37/26B24B37/042B24D3/28
    • An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness. The pad exhibits a stable morphology that can be reproduced easily and consistently. The pad surface resists glazing, thereby requiring less frequent and less aggressive conditioning. The benefits of such a polishing pad are low dishing of metal features, low oxide erosion, reduced pad conditioning, longer pad life, high metal removal rates, good planarization, and lower defectivity (scratches and Light Point Defects).
    • 用于在半导体晶片上抛光金属镶嵌结构的改进的焊盘和工艺。 该方法包括以下步骤:将聚合物片材的表面压在聚合物片材的表面上,并与含有亚微米级颗粒的含水基液体组合,并提供在压力下使晶片和抛光垫片相对运动的装置, 接触导致平面去除所述晶片的表面,其中抛光垫在去除所述负载时具有低的弹性恢复,使得片材的机械响应大大无弹性。 改进的焊盘的特征在于具有高的能量耗散以及高焊盘刚度。 该垫具有稳定的形态,可以容易且一致地再现。 垫表面抵抗玻璃窗,从而需要较少的频繁和较不积极的调理。 这种抛光垫的优点是金属特征的低凹陷,低氧化物侵蚀,减少的焊盘调节,更长的焊盘寿命,高金属去除速率,良好的平坦化和较低的缺陷(划痕和光点缺陷)。
    • 57. 发明授权
    • Inter-layer interconnection structure for large electrical connections
    • 用于大型电气连接的层间互连结构
    • US06642597B1
    • 2003-11-04
    • US10272767
    • 2002-10-16
    • Peter A. BurkeWilliam K. Barth
    • Peter A. BurkeWilliam K. Barth
    • H01L3100
    • H01L23/5226H01L23/53238H01L2924/0002H01L2924/00
    • Embodiments of the invention include an electrical interconnection structure for connection to large electrical contacts. The electrical interconnection includes a semiconductor substrate having a conductive pad layer formed thereon. A dielectric layer having a plurality of elongate trenches is formed over the conductive pad layer such that the elongate trenches extend through the dielectric layer to the underlying conductive pad layer. Elongate conductive contacts are formed in the elongate trenches to establish electrical connections to the underlying conductive pad layer. The long axes of the elongate bar trenches can be arranged substantially parallel to the long axes of the slots formed in the copper pad. Alternatively, the long axes of the bar trenches can be arranged transversely to the long axes of the slots formed in the copper pad. In some embodiments, the conductive contacts are formed such that they establish electrical connection with sidewalls of the underlying conductive pad layer. Other embodiments address the methods of manufacturing the electrical interconnection structures of the present invention.
    • 本发明的实施例包括用于连接到大电触头的电互连结构。 电互连包括其上形成有导电焊盘层的半导体衬底。 具有多个细长沟槽的电介质层形成在导电焊盘层上方,使得细长的沟槽延伸通过介电层延伸到下面的导电焊盘层。 在细长的沟槽中形成细长的导电触点以建立与下面的导电焊盘层的电连接。 细长条沟的长轴可以布置成基本上平行于形成在铜垫中的槽的长轴。 或者,条形沟槽的长轴可以横向于形成在铜垫中的槽的长轴布置。 在一些实施例中,导电触点形成为使得它们与下面的导电焊盘层的侧壁建立电连接。 其他实施例涉及制造本发明的电互连结构的方法。
    • 60. 发明授权
    • Polishing pad with radially extending tapered channels
    • 具有径向延伸锥形通道的抛光垫
    • US5645469A
    • 1997-07-08
    • US709179
    • 1996-09-06
    • Peter A. BurkeBradley J. Yellitz
    • Peter A. BurkeBradley J. Yellitz
    • B24B37/26B24B1/00
    • B24B37/26
    • A polishing pad having a polishing surface with radially extending tapered channels is disclosed. The polishing surface includes an inner radius within an outer radius, and the channels extend from the inner radius to the outer radius. Preferably, the outer radius is spaced from an outer circumferential edge of the polishing surface, the inner radius is an inner circumferential edge of the polishing surface, and the channels taper laterally and vertically at the outer radius. The channels are dimensioned and configured to direct slurry from the inner radius to the outer radius. The channels can be shaped with opposing sidewalls that are parallel in a first portion and diagonally converge in a second portion to form a sunburst pattern, or alternatively, with opposing sidewalls that continuously curve in a first rotational direction to form a starfish pattern. A polishing method includes positioning a wafer over the outer radius while introducing a slurry to facilitate polishing the wafer, and positioning the wafer inside the outer radius while introducing a cleaning fluid to facilitate cleaning the wafer.
    • 公开了具有带径向延伸的锥形通道的抛光表面的抛光垫。 抛光表面包括在外半径内的内半径,并且通道从内半径延伸到外半径。 优选地,外半径与抛光表面的外圆周边缘间隔开,内半径是抛光表面的内圆周边缘,并且通道在外半径处横向和垂直地缩小。 通道的尺寸和构造用于将浆料从内半径引导到外半径。 通道可以被成形为具有在第一部分中平行并且在第二部分中对角地会聚以形成阳光照射图案的相对侧壁,或者可选地,具有在第一旋转方向上连续弯曲以形成海星图案的相对侧壁。 抛光方法包括将晶片定位在外半径上,同时引入浆料以便于抛光晶片,并且将晶片定位在外半径内,同时引入清洁流体以便于清洁晶片。