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51. 发明授权

US08759920B2 Semiconductor device and method of forming the same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US08759920B2
公开(公告)日：2014-06-24
申请号：US13486343
申请日：2012-06-01
申请人： Clement Hsingjen Wann , Chih-Hao Chang , Shou Zen Chang , Chih-Hsin Ko , Yasutoshi Okuno , Andrew Joseph Kelly
发明人： Clement Hsingjen Wann , Chih-Hao Chang , Shou Zen Chang , Chih-Hsin Ko , Yasutoshi Okuno , Andrew Joseph Kelly
IPC分类号： H01L21/70
CPC分类号： H01L21/823814 , H01L21/76897 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L21/823828 , H01L21/823871 , H01L23/485 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions. The semiconductor device further includes a first device disposed in a first device region of the plurality of device regions, the first device including a first gate structure, first gate spacers disposed on sidewalls of the first gate structure, and first source and drain features. The semiconductor device further includes a second device disposed in a second device region of the plurality of device regions, the second device including a second gate structure, second gate spacers disposed on sidewalls of the second gate structure, and second source and drain features. The second and first source and drain features having a source and drain feature and a contact feature in common. The common contact feature being a self-aligned contact.
摘要翻译：公开了一种用于制造半导体器件的半导体器件和方法。示例性半导体器件包括包括包括多个器件区域的有源区的半导体衬底。半导体器件还包括设置在多个器件区域的第一器件区域中的第一器件，第一器件包括第一栅极结构，设置在第一栅极结构的侧壁上的第一栅极间隔区以及第一源极和漏极特征。半导体器件还包括设置在多个器件区域的第二器件区域中的第二器件，第二器件包括第二栅极结构，设置在第二栅极结构的侧壁上的第二栅极间隔区以及第二源极和漏极特征。第二和第一源极和漏极特征具有源极和漏极特征以及共同的接触特征。常见的接触特征是自对准接触。

52. 发明授权

US08629478B2 Fin structure for high mobility multiple-gate transistor 有权
标题翻译：用于高迁移率多栅极晶体管的鳍结构
公开(公告)号：US08629478B2
公开(公告)日：2014-01-14
申请号：US12797839
申请日：2010-06-10
申请人： Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/267 , H01L29/66795 , H01L29/7842
摘要： A vertical fin structure for a semiconductor transistor includes a semiconductor substrate, a fin layer on top of the substrate, a capping layer overlaying the fin layer, wherein the substrate comprises group IV semiconductor material, the fin layer comprises group IV semiconductor material, the capping layer comprises semiconductor compound from group III-V. The fin layer can comprise Ge, SiGe, SiC, or any combinations thereof. The semiconductor substrate can comprise Si, Ge, SiGe, or SiC. The capping layer can comprise GaAs, InGaAs, InAs, InSb, GaSb, GaN, InP, or any combinations thereof. The capping layer can provide more than a 4 percent lattice mismatch with the semiconductor substrate. The fin layer can be located in between shallow trench insulation (STI) layers that provide isolation from adjacent devices. The vertical fin structure can further include a high-k dielectric layer overlaying the capping layer and a metal gate layer overlaying the high-k dielectric layer.
摘要翻译：用于半导体晶体管的垂直翅片结构包括半导体衬底，衬底顶部的翅片层，覆盖翅片层的覆盖层，其中衬底包括IV族半导体材料，鳍层包括IV族半导体材料，封盖层包含III-V族的半导体化合物。鳍层可以包括Ge，SiGe，SiC或其任何组合。半导体衬底可以包括Si，Ge，SiGe或SiC。覆盖层可以包括GaAs，InGaAs，InAs，InSb，GaSb，GaN，InP或其任何组合。覆盖层可以提供与半导体衬底超过4％的晶格失配。翅片层可以位于提供与相邻装置隔离的浅沟槽绝缘（STI）层之间。垂直翅片结构还可以包括覆盖覆盖层的高k电介质层和覆盖高k电介质层的金属栅极层。

53. 发明授权

US08623718B2 Tilt implantation for forming FinFETs 有权
标题翻译：用于形成FinFET的倾斜植入
公开(公告)号：US08623718B2
公开(公告)日：2014-01-07
申请号：US13247570
申请日：2011-09-28
申请人： Feng Yuan , Tsung-Lin Lee , Shao-Ming Yu , Clement Hsingjen Wann
发明人： Feng Yuan , Tsung-Lin Lee , Shao-Ming Yu , Clement Hsingjen Wann
IPC分类号： H01L21/00
CPC分类号： H01L29/66803
摘要： In a method for forming FinFETs, a photo resist is formed to cover a first semiconductor fin in a wafer, wherein a second semiconductor fin adjacent to the first semiconductor fin is not covered by the photo resist. An edge of the photo resist between and parallel to the first and the second semiconductor fins is closer to the first semiconductor fin than to the second semiconductor fin. A tilt implantation is performed to form a lightly-doped source/drain region in the second semiconductor fin, wherein the first tilt implantation is tilted from the second semiconductor fin toward the first semiconductor fin.
摘要翻译：在形成FinFET的方法中，形成光致抗蚀剂以覆盖晶片中的第一半导体鳍片，其中与第一半导体鳍片相邻的第二半导体鳍片不被光致抗蚀剂覆盖。第一半导体鳍片和第二半导体鳍片之间的平行于第一和第二半导体鳍片的光刻胶的边缘比第二半导体鳍片更靠近第一半导体鳍片。进行倾斜注入以在第二半导体鳍片中形成轻掺杂的源极/漏极区域，其中第一倾斜注入从第二半导体鳍片向第一半导体鳍片倾斜。

54. 发明授权

US08603924B2 Methods of forming gate dielectric material 有权
标题翻译：形成栅介质材料的方法
公开(公告)号：US08603924B2
公开(公告)日：2013-12-10
申请号：US13004309
申请日：2011-01-11
申请人： Liang-Gi Yao , Chia-Cheng Chen , Clement Hsingjen Wann
发明人： Liang-Gi Yao , Chia-Cheng Chen , Clement Hsingjen Wann
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L29/4983 , H01L21/28185 , H01L21/28211 , H01L21/283 , H01L29/49 , H01L29/51 , H01L29/513 , H01L29/6659 , H01L29/7833
摘要： A method of forming gate dielectric material includes forming a silicon oxide gate layer over a substrate. The silicon oxide gate layer is treated with a first ozone-containing gas. After treating the silicon oxide gate layer, a high dielectric constant (high-k) gate dielectric layer is formed over the treated silicon oxide gate layer.
摘要翻译：形成栅极电介质材料的方法包括在衬底上形成氧化硅栅极层。用第一含臭氧气体处理氧化硅栅极层。在处理氧化硅栅极层之后，在经处理的氧化硅栅极层上形成高介电常数（高k）栅极电介质层。

55. 发明申请

US20130248948A1 Source/Drain Profile for FinFET 有权
公开(公告)号：US20130248948A1
公开(公告)日：2013-09-26
申请号：US13426106
申请日：2012-03-21
申请人： Ta-Chun Ma , Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Ta-Chun Ma , Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/02639 , H01L21/30604 , H01L21/3083 , H01L29/045 , H01L29/0688 , H01L29/1037 , H01L29/66636 , H01L29/66681 , H01L29/66795 , H01L29/7816 , H01L29/7833 , H01L29/7851 , H01L29/7853
摘要： An embodiment is a FinFET device. The FinFET device comprises a fin, a first source/drain region, a second source/drain region, and a channel region. The fin is raised above a substrate. The first source/drain region and the second source/drain region are in the fin. The channel region is laterally between the first and second source/drain regions. The channel region has facets that are not parallel and not perpendicular to a top surface of the substrate.

56. 发明申请

US20130168771A1 Method of Forming CMOS FinFET Device 有权
标题翻译： CMOS FinFET器件的形成方法
公开(公告)号：US20130168771A1
公开(公告)日：2013-07-04
申请号：US13340937
申请日：2011-12-30
申请人： Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L27/12 , H01L21/84 , H01L21/8238 , H01L27/092
CPC分类号： H01L27/1211 , H01L21/823821 , H01L21/8258 , H01L21/845 , H01L29/1054 , H01L29/267
摘要： A CMOS FinFET device and method for fabricating a CMOS FinFET device is disclosed. An exemplary CMOS FinFET device includes a substrate including a first region and a second region. The CMOS FinFET further includes a fin structure disposed over the substrate including a first fin in the first region and a second fin in the second region. The CMOS FinFET further includes a first portion of the first fin comprising a material that is the same material as the substrate and a second portion of the first fin comprising a III-V semiconductor material deposited over the first portion of the first fin. The CMOS FinFET further includes a first portion of the second fin comprising a material that is the same material as the substrate and a second portion of the second fin comprising a germanium (Ge) material deposited over the first portion of the second fin.
摘要翻译：公开了一种用于制造CMOS FinFET器件的CMOS FinFET器件和方法。示例性的CMOS FinFET器件包括包括第一区域和第二区域的衬底。 CMOS FinFET还包括布置在衬底上的翅片结构，其包括在第一区域中的第一鳍片和在第二区域中的第二鳍片。 CMOS FinFET还包括第一鳍片的第一部分，其包括与衬底相同的材料的材料，以及第一鳍片的第二部分，其包括沉积在第一鳍片的第一部分上的III-V半导体材料。 CMOS FinFET还包括第二鳍片的第一部分，其包括与衬底相同的材料，第二鳍片的第二部分包括沉积在第二鳍片的第一部分上的锗（Ge）材料。

57. 发明授权

US08455860B2 Reducing source/drain resistance of III-V based transistors 有权
标题翻译：降低III-V晶体管的源极/漏极电阻
公开(公告)号：US08455860B2
公开(公告)日：2013-06-04
申请号：US12616073
申请日：2009-11-10
申请人： Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L29/12
CPC分类号： H01L29/78 , H01L21/22 , H01L29/41775 , H01L29/66462 , H01L29/7783
摘要： An integrated circuit structure includes a substrate; a channel layer over the substrate, wherein the channel layer is formed of a first III-V compound semiconductor material; a highly doped semiconductor layer over the channel layer; a gate dielectric penetrating through and contacting a sidewall of the highly doped semiconductor layer; and a gate electrode on a bottom portion of the gate dielectric. The gate dielectric includes a sidewall portion on a sidewall of the gate electrode.
摘要翻译：集成电路结构包括：基板; 在所述衬底上的沟道层，其中所述沟道层由第一III-V族化合物半导体材料形成; 在沟道层上的高掺杂半导体层; 栅介质穿透并接触高掺杂半导体层的侧壁; 以及在栅极电介质的底部上的栅电极。栅极电介质包括在栅电极的侧壁上的侧壁部分。

58. 发明申请

US20130078772A1 Tilt Implantation for Forming FinFETs 有权
标题翻译：用于形成FinFET的倾斜植入
公开(公告)号：US20130078772A1
公开(公告)日：2013-03-28
申请号：US13247570
申请日：2011-09-28
申请人： Feng Yuan , Tsung-Lin Lee , Shao-Ming Yu , Clement Hsingjen Wann
发明人： Feng Yuan , Tsung-Lin Lee , Shao-Ming Yu , Clement Hsingjen Wann
IPC分类号： H01L21/336
CPC分类号： H01L29/66803
摘要： In a method for forming FinFETs, a photo resist is formed to cover a first semiconductor fin in a wafer, wherein a second semiconductor fin adjacent to the first semiconductor fin is not covered by the photo resist. An edge of the photo resist between and parallel to the first and the second semiconductor fins is closer to the first semiconductor fin than to the second semiconductor fin. A tilt implantation is performed to form a lightly-doped source/drain region in the second semiconductor fin, wherein the first tilt implantation is tilted from the second semiconductor fin toward the first semiconductor fin.
摘要翻译：在形成FinFET的方法中，形成光致抗蚀剂以覆盖晶片中的第一半导体鳍片，其中与第一半导体鳍片相邻的第二半导体鳍片不被光致抗蚀剂覆盖。第一半导体鳍片和第二半导体鳍片之间的平行于第一和第二半导体鳍片的光刻胶的边缘比第二半导体鳍片更靠近第一半导体鳍片。进行倾斜注入以在第二半导体鳍片中形成轻掺杂的源极/漏极区域，其中第一倾斜注入从第二半导体鳍片向第一半导体鳍片倾斜。

59. 发明申请

US20130075818A1 3D Semiconductor Device and Method of Manufacturing Same 审中-公开
标题翻译： 3D半导体器件及其制造方法相同
公开(公告)号：US20130075818A1
公开(公告)日：2013-03-28
申请号：US13243723
申请日：2011-09-23
申请人： Tsung-Lin Lee , Feng Yuan , Chih Chieh Yeh , Clement Hsingjen Wann
发明人： Tsung-Lin Lee , Feng Yuan , Chih Chieh Yeh , Clement Hsingjen Wann
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L21/28088 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/0886 , H01L27/0924 , H01L27/1211 , H01L29/66545 , H01L29/7845 , H01L29/785
摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate and a 3D structure disposed over the substrate. The semiconductor device further includes a dielectric layer disposed over the 3D structure, a WFMG layer disposed over the dielectric layer, and a gate structure disposed over the WFMG layer. The gate structure traverses the 3D structure and separates a source region and a drain region of the 3D structure. The source and drain region define a channel region therebetween. The gate structure induces a stress in the channel region.
摘要翻译：公开了一种用于制造半导体器件的半导体器件和方法。示例性的半导体器件包括衬底和设置在衬底上的3D结构。半导体器件还包括设置在3D结构上的电介质层，设置在电介质层上的WFMG层，以及设置在WFMG层上的栅极结构。栅极结构横穿3D结构并分离3D结构的源极区域和漏极区域。源极和漏极区域在其间限定沟道区域。栅极结构在沟道区域中引起应力。

60. 发明申请

US20130034948A1 Method of Manufacturing a Semiconductor Device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130034948A1
公开(公告)日：2013-02-07
申请号：US13204352
申请日：2011-08-05
申请人： Gin-Chen Huang , Yi-An Lin , Ching-Hong Jiang , Neng-Kuo Chen , Sey-Ping Sun , Clement Hsingjen Wann
发明人： Gin-Chen Huang , Yi-An Lin , Ching-Hong Jiang , Neng-Kuo Chen , Sey-Ping Sun , Clement Hsingjen Wann
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/3081 , H01L21/31053 , H01L21/31055
摘要： A method for fabricating a semiconductor device is disclosed. An exemplary method includes a providing substrate. A dielectric layer is formed over the semiconductor substrate and a stop layer is formed over the dielectric layer. The stop layer and the dielectric layer comprise a different material. The method further includes forming a patterned hard mask layer over the stop layer and etching the semiconductor substrate through the patterned hard mask layer to form a plurality of trenches. The method also includes depositing an isolation material on the semiconductor substrate and substantially filling the plurality of trenches. Thereafter, performing a CMP process on the semiconductor substrate, wherein the CMP process stops on the stop layer.
摘要翻译：公开了一种制造半导体器件的方法。一种示例性方法包括提供衬底。在半导体衬底上形成电介质层，并在电介质层上形成阻挡层。阻挡层和电介质层包括不同的材料。该方法还包括在停止层上形成图案化的硬掩模层，并通过图案化的硬掩模层蚀刻半导体衬底以形成多个沟槽。该方法还包括在半导体衬底上沉积隔离材料并基本上填充多个沟槽。此后，在半导体衬底上执行CMP处理，其中CMP处理在停止层上停止。

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