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51. 发明授权

US08386712B2 Structure for supporting simultaneous storage of trace and standard cache lines 失效
标题翻译：用于支持跟踪和标准缓存行同时存储的结构
公开(公告)号：US08386712B2
公开(公告)日：2013-02-26
申请号：US12116676
申请日：2008-05-07
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0864 , G06F12/0875 , G06F12/0897 , G06F2212/6082
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.
摘要翻译：体现在用于设计，制造和/或测试用于单个统一级别的一个指令高速缓存的机器可读存储介质中的设计结构，其中一些行可以包含跟踪和相同同余类中的其他行的设计可以包含一致的指令块提供常规的高速缓存线。描述了一种用于索引到缓存中并选择所需行的机制。对缓存中包含哪些行进行控制。当在标签比较步骤中匹配时，提供在轨迹线和常规线之间的选择。

52. 发明授权

US07996618B2 Apparatus and method for using branch prediction heuristics for determination of trace formation readiness 失效
公开(公告)号：US07996618B2
公开(公告)日：2011-08-09
申请号：US13016144
申请日：2011-01-28
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F Robinson , Sumedh W Sathaye , Jeffrey R Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F Robinson , Sumedh W Sathaye , Jeffrey R Summers
IPC分类号： G06F9/40 , G06F12/08
CPC分类号： G06F12/0862 , G06F12/0875 , G06F2212/6028
摘要： A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.

53. 发明授权

US07792873B2 Data structure supporting random delete and timer function 失效
标题翻译：数据结构支持随机删除和定时功能
公开(公告)号：US07792873B2
公开(公告)日：2010-09-07
申请号：US12015198
申请日：2008-01-16
申请人： Gordon T. Davis , Marco Heddes , Dongming Hwang
发明人： Gordon T. Davis , Marco Heddes , Dongming Hwang
IPC分类号： G06F17/30 , G06F7/00
CPC分类号： G06F17/30955 , Y10S707/99933 , Y10S707/99942
摘要： A procedure is used to provide data structures that handle large numbers of active data entries and a high rate of additions and deletions of active entries. The procedure utilizes one or more of the following modifications. Timers are removed from individual session table entries and are linked via pointers. Bilateral links are established between the session table and the timer structure. Aging/timer checks are applied to the timer control block (TCB). A chain of TCBs, optionally including an excess of blocks, may be used along with packing of multiple TCBs into a single memory location. This excess of blocks permits a terminated session to continue to occupy a TCB until the timer process progresses to that block location in the chain of blocks.
摘要翻译：一个过程用于提供处理大量活动数据条目的数据结构以及高活动条目的添加和删除率。该过程利用以下一个或多个修改。定时器从单个会话表条目中删除，并通过指针进行链接。在会话表和定时器结构之间建立双向链路。老化/定时器检查应用于定时器控制块（TCB）。可以使用可选地包括多余块的TCB链，以及将多个TCB打包到单个存储器位置中。这个多余的块允许终止的会话继续占用TCB，直到定时器进程前进到块链中的块位置。

54. 发明申请

US20080133467A1 DATA STRUCTURE SUPPORTING RANDOM DELETE AND TIMER FUNCTION 失效
标题翻译：数据结构支持随机删除和定时器功能
公开(公告)号：US20080133467A1
公开(公告)日：2008-06-05
申请号：US12015198
申请日：2008-01-16
申请人： Gordon T. Davis , Marco Heddes , Dongming Hwang
发明人： Gordon T. Davis , Marco Heddes , Dongming Hwang
IPC分类号： G06F7/10 , G06F17/30 , G06F7/00
CPC分类号： G06F17/30955 , Y10S707/99933 , Y10S707/99942
摘要： A procedure is used to provide data structures that handle large numbers of active data entries and a high rate of additions and deletions of active entries. The procedure utilizes one or more of the following modifications. Timers are removed from individual session table entries and are linked via pointers. Bilateral links are established between the session table and the timer structure. Aging/timer checks are applied to the timer control block (TCB). A chain of TCBs, optionally including an excess of blocks, may be used along with packing of multiple TCBs into a single memory location. This excess of blocks permits a terminated session to continue to occupy a TCB until the timer process progresses to that block location in the chain of blocks.
摘要翻译：一个过程用于提供处理大量活动数据条目的数据结构以及高活动条目的添加和删除率。该过程利用以下一个或多个修改。定时器从单个会话表条目中删除，并通过指针进行链接。在会话表和定时器结构之间建立双向链路。老化/定时器检查应用于定时器控制块（TCB）。可以使用可选地包括多余块的TCB链，以及将多个TCB打包到单个存储器位置中。这个多余的块允许终止的会话继续占用TCB，直到定时器进程前进到块链中的块位置。

55. 发明授权

US07380065B2 Performance of a cache by detecting cache lines that have been reused 有权
标题翻译：通过检测已被重用的高速缓存行来执行缓存的性能
公开(公告)号：US07380065B2
公开(公告)日：2008-05-27
申请号：US11094399
申请日：2005-03-30
申请人： Gordon T. Davis , Santiago A. Leon , Hans-Werner Tast
发明人： Gordon T. Davis , Santiago A. Leon , Hans-Werner Tast
IPC分类号： G06F13/00
CPC分类号： G06F12/127
摘要： A method and system for improving the performance of a cache. The cache may include an array of tag entries where each tag entry includes an additional bit (“reused bit”) used to indicate whether its associated cache line has been reused, i.e., has been requested or referenced by the processor. By tracking whether a cache line has been reused, data (cache line) that may not be reused may be replaced with the new incoming cache line prior to replacing data (cache line) that may be reused. By replacing data in the cache memory that might not be reused prior to replacing data that might be reused, the cache hit may be improved thereby improving performance.
摘要翻译：一种用于提高缓存性能的方法和系统。高速缓存可以包括标签条目的阵列，其中每个标签条目包括用于指示其相关联的高速缓存行是否被重用，即被处理器请求或引用的附加位（“重用位”）。通过跟踪高速缓存行是否被重用，在替换可被重用的数据（高速缓存行）之前，可以用新的传入高速缓存行替换可能不被重用的数据（高速缓存行）。通过在替换可能被重用的数据之前替换高速缓冲存储器中可能不被重用的数据，可以提高高速缓存命中，从而提高性能。

56. 发明申请

US20080114964A1 Apparatus and Method for Cache Maintenance 审中-公开
标题翻译：缓存维护的设备和方法
公开(公告)号：US20080114964A1
公开(公告)日：2008-05-15
申请号：US11559512
申请日：2006-11-14
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F9/305
CPC分类号： G06F12/0893 , G06F9/3808 , G06F9/3844 , G06F12/0862
摘要： A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Control is exercised over which lines are contained within the cache. This invention avoids inefficiencies in the cache by removing trace lines experiencing early exits from the cache, or trace lines that are short, by maintaining a few bits of information about the accuracy of the control flow in a trace cache line and using that information in addition to the LRU (Least Recently Used) bits that maintain the recency information of a cache line, in order to make a replacement decision.
摘要翻译：单个统一的一级指令高速缓存，其中一些行可以包含跟踪和同一同余类中的其他行可以包含与常规高速缓存行一致的指令块。对缓存中包含哪些行进行控制。本发明通过在跟踪高速缓存行中维护关于控制流的准确度的几位信息并且使用该信息来避免高速缓存中的低效率，通过删除经历来自缓存的早期退出的跟踪线或短路的跟踪线到保持高速缓存行的新近度信息的LRU（最近使用的）位，以便进行替换判定。

57. 发明授权

US5459843A RISC-type pipeline processor having N slower execution units operating in parallel interleaved and phase offset manner with a faster fetch unit and a faster decoder 失效
标题翻译：具有N个较慢执行单元的RISC型流水线处理器以并行交错和相位偏移方式工作，具有更快的提取单元和更快的解码器
公开(公告)号：US5459843A
公开(公告)日：1995-10-17
申请号：US282412
申请日：1994-07-28
申请人： Gordon T. Davis , Sebastian T. Ventrone , John J. Reilly , Baiju D. Mandalia , Michael G. Holung , William R. Robinson, Jr.
发明人： Gordon T. Davis , Sebastian T. Ventrone , John J. Reilly , Baiju D. Mandalia , Michael G. Holung , William R. Robinson, Jr.
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3885 , G06F9/3851
摘要： A pipelined, RISC-type processor operated in parallel mode and its associated processing methods for separately handling instructions from multiple program instruction sets. The pipelined processor includes an instruction fetch unit, an instruction decode unit and n execution units. Each execution unit operates at substantially the same process cycle time, while the speed of operation of the instruction fetch unit and instruction decode unit is at least n times the cycle time of the execution units such that each phase of the pipeline separately processes n instructions substantially within one machine cycle. Timing and control circuitry is coupled to each of the principle elemental units for controlling the timing and sequence of operations on instructions.
摘要翻译：以并行模式运行的流水线RISC型处理器及其相关处理方法，用于分别处理来自多个程序指令集的指令。流水线处理器包括指令提取单元，指令解码单元和n个执行单元。每个执行单元以基本上相同的处理周期时间操作，而指令获取单元和指令解码单元的操作速度至少为执行单元的周期时间的n倍，使得流水线的每个相分别基本上处理n个指令在一个机器周期内。定时和控制电路耦合到每个主要元件单元，用于控制指令上的操作的时序和顺序。

58. 发明授权

US5010476A Time multiplexed system for tightly coupling pipelined processors to separate shared instruction and data storage units 失效
标题翻译：时间复用系统，用于紧密耦合流水线处理器以分离共享指令和数据存储单元
公开(公告)号：US5010476A
公开(公告)日：1991-04-23
申请号：US876625
申请日：1986-06-20
申请人： Gordon T. Davis
发明人： Gordon T. Davis
IPC分类号： G06F15/167 , G06F12/00 , G06F13/16 , G06F13/18
CPC分类号： G06F9/3885 , G06F13/1663 , G06F9/3867
摘要： This invention speeds up the execution of instructions in an information processing system by tightly coupling two or more processors to a random access storage mechanism in such a manner that no arbitration is required and no processor is forced to wait while another processor accesses the storage mechanism. This is accomplished by coupling the processors to the storage mechanism in a time multiplexed manner which enables each processor to have a periodic regularly occurring turn at accessing the storage mechanism.
摘要翻译：本发明通过将两个或更多个处理器紧密地耦合到随机存取存储机制来加速信息处理系统中的指令的执行，使得不需要仲裁并且在另一个处理器访问存储机制时不强制处理器等待。这通过以时间复用方式将处理器耦合到存储机构来实现，这使得每个处理器能够在访问存储机制时具有周期性的定期发生的转弯。

59. 发明授权

US4972342A Programmable priority branch circuit 失效
标题翻译：可编程优先支路
公开(公告)号：US4972342A
公开(公告)日：1990-11-20
申请号：US254985
申请日：1988-10-07
申请人： Gordon T. Davis , Baiju D. Mandalia
发明人： Gordon T. Davis , Baiju D. Mandalia
IPC分类号： G06F9/32 , G06F9/38 , G06F9/48
CPC分类号： G06F9/3885 , G06F9/30058 , G06F9/30094 , G06F9/3804
摘要： A special purpose circuit unit, responsive to a special BBD instruction, provides for more efficient execution of program branches required in poll and test type routines used by data processors. This unit can easily be added to almost any contemporary processing system to speed up performance of priority branch operations. It includes: a stack of registers loadable with branch addresses designating locations of branch target instructions, an input register for holding bits representing branch conditions accessible from immediate (programmable) storage, and a programmable priority encoder responsive to the BBD instruction to select an address from the stack in accordance with the position in the input register of a highest priority one of the bits representing an active request for instruction branching. The selected address is used to fetch an instruction representing the start of a program segment for attending to the selected branch condition. Contents of the branch address stack are alterable by program to allow for varying selections of branch routines to fulfill conditions denotable by different sets of bits loadable into the input register. The priority encoder includes a stack of selection control registers which are also loadable by programs, to allow for variability in the priority ordering accorded to the bit positions of the input register. By dynamically loading information into the branch address and priority selection stacks, subject BBD unit can be shared dynamically for resolving sequence branching relative to multiple different classes of conditions or events depending on system requirements. The unit is configurable to execute its priority and branch address selection operations together in a single clock cycle of the system. In pipelined systems, the BBD function can be conveniently accommodated in parallel with other system functions.

60. 发明授权

US07934081B2 Apparatus and method for using branch prediction heuristics for determination of trace formation readiness 失效
标题翻译：使用分支预测启发式方法确定痕量形成准备的装置和方法
公开(公告)号：US07934081B2
公开(公告)日：2011-04-26
申请号：US11538831
申请日：2006-10-05
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F9/40 , G06F12/08
CPC分类号： G06F12/0862 , G06F12/0875 , G06F2212/6028
摘要： A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.
摘要翻译：单个统一的一级指令高速缓存，其中一些行可以包含跟踪和同一同余类中的其他行可以包含与常规高速缓存行一致的指令块。缓存中的跟踪行的形成在系统的初始操作中被延迟，以确保存储的跟踪线的质量。

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