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51. 发明授权

US08736014B2 High mechanical strength additives for porous ultra low-k material 有权
标题翻译：用于多孔超低k材料的高机械强度添加剂
公开(公告)号：US08736014B2
公开(公告)日：2014-05-27
申请号：US12271617
申请日：2008-11-14
申请人： Bo-Jiun Lin , Ching-Yu Lo , Hai-Ching Chen , Tien-I Bao , Chen-Hua Yu
发明人： Bo-Jiun Lin , Ching-Yu Lo , Hai-Ching Chen , Tien-I Bao , Chen-Hua Yu
IPC分类号： H01L21/31
CPC分类号： H01L21/3121 , C23C18/1212 , C23C18/122 , C23C18/1254 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/02304
摘要： A semiconductor device and method for making such that provides improved mechanical strength is disclosed. The semiconductor device comprises a semiconductor substrate; an adhesion layer disposed over the semiconductor substrate; and a porous low-k film disposed over the semiconductor substrate, wherein the porous low-k film comprises a porogen and a composite bonding structure including at least one Si—O—Si bonding group and at least one bridging organic functional group.
摘要翻译：公开了一种提供改进的机械强度的半导体器件和制造方法。半导体器件包括半导体衬底; 设置在半导体衬底上的粘附层; 以及设置在所述半导体衬底上的多孔低k膜，其中所述多孔低k膜包含致孔剂和包含至少一个Si-O-Si键合基团和至少一个桥连有机官能团的复合键合结构。

52. 发明授权

US08710660B2 Hybrid interconnect scheme including aluminum metal line in low-k dielectric 有权
公开(公告)号：US08710660B2
公开(公告)日：2014-04-29
申请号：US13554817
申请日：2012-07-20
申请人： Chen-Hua Yu , Tien-I Bao
发明人： Chen-Hua Yu , Tien-I Bao
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76807 , H01L21/7682 , H01L21/76834 , H01L21/76843 , H01L21/76877 , H01L21/76885 , H01L23/53219 , H01L23/53223 , H01L23/53233 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k dielectric layer, and an aluminum-containing metal line over and electrically coupled to the copper-containing via. The aluminum-containing metal line is in the second low-k dielectric layer.

53. 发明授权

US08264066B2 Liner formation in 3DIC structures 有权
标题翻译： 3DIC结构中的衬垫形成
公开(公告)号：US08264066B2
公开(公告)日：2012-09-11
申请号：US12617900
申请日：2009-11-13
申请人： Ching-Yu Lo , Hung-Jung Tu , Hai-Ching Chen , Tien-I Bao , Wen-Chih Chiou , Chen-Hua Yu
发明人： Ching-Yu Lo , Hung-Jung Tu , Hai-Ching Chen , Tien-I Bao , Wen-Chih Chiou , Chen-Hua Yu
IPC分类号： H01L29/40
CPC分类号： H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/02 , H01L2221/68372 , H01L2224/0557 , H01L2924/00014 , H01L2924/0002 , H01L2924/01019 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2224/05552 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner.
摘要翻译：集成电路结构包括半导体衬底; 贯穿半导体衬底的贯通半导体通孔（TSV）开口; 和TSV开口的TSV衬管。 TSV衬套包括在TSV开口的侧壁上的侧壁部分和TSV开口底部的底部。 TSV衬管的底部部分的底部高度大于TSV衬套的侧壁部分的中间厚度。

54. 发明授权

US07465676B2 Method for forming dielectric film to improve adhesion of low-k film 有权
标题翻译：用于形成介电膜以改善低k膜的粘附性的方法
公开(公告)号：US07465676B2
公开(公告)日：2008-12-16
申请号：US11409658
申请日：2006-04-24
申请人： Fang Wen Tsai , I-I Chen , Zhen-Cheng Wu , Chih-Lung Lin , Tien-I Bao , Shwang-Ming Jeng , Chen-Hua Yu
发明人： Fang Wen Tsai , I-I Chen , Zhen-Cheng Wu , Chih-Lung Lin , Tien-I Bao , Shwang-Ming Jeng , Chen-Hua Yu
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/76832 , H01L21/76843
摘要： A semiconductor structure having improved adhesion between a low-k dielectric layer and the underlying layer and a method for forming the same are provided. The semiconductor substrate includes a dielectric layer over a semiconductor substrate, an adhesion layer on the dielectric layer wherein the adhesion layer comprises a transition sub-layer over an initial sub-layer, and wherein the transition sub-layer has a composition that gradually changes from a lower portion to an upper portion. A low-k dielectric layer is formed on the adhesion layer. Damascene openings are formed in the low-k dielectric layer. A top portion of the transition sub-layer has a composition substantially similar to a composition of the low-k dielectric layer. A bottom portion of the transition sub-layer has a composition substantially similar to a composition of the initial sub-layer.
摘要翻译：提供了具有改善的低k电介质层和下层之间的粘附性的半导体结构及其形成方法。所述半导体衬底包括半导体衬底上的电介质层，所述电介质层上的粘合层，其中所述粘合层包含初始子层上的过渡子层，并且其中所述过渡子层具有逐渐从下部到上部。在粘合层上形成低k电介质层。在低k电介质层中形成镶嵌开口。过渡子层的顶部具有与低k电介质层的组成基本相似的组成。过渡子层的底部具有与初始子层的组成基本相似的组成。

55. 发明申请

US20080188074A1 Peeling-free porous capping material 审中-公开
标题翻译：无剥离多孔封盖材料
公开(公告)号：US20080188074A1
公开(公告)日：2008-08-07
申请号：US11728623
申请日：2007-03-27
申请人： I-I Chen , Fang Wen Tsai , Zhen-Cheng Wu , Tien-I Bao , Shwang-Ming Jeng , Chen-Hua Yu
发明人： I-I Chen , Fang Wen Tsai , Zhen-Cheng Wu , Tien-I Bao , Shwang-Ming Jeng , Chen-Hua Yu
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76829 , H01L21/76835 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a cap layer for an interconnect structure is provided. The method includes providing a substrate; depositing a low-k dielectric layer comprising a first porogen over the substrate; depositing a low-k cap layer comprising a second porogen on the low-k dielectric layer; and curing the low-k dielectric layer and the low-k cap layer simultaneously to remove the first and the second porogens, so that a first porosity in the low-k dielectric layer and a second porosity in the low-k cap layer are created. The second porosity is preferably less than the first porosity. Preferably, the low-k dielectric layer and the low-k cap layer comprise a common set of precursors and porogens, and are in-situ performed.
摘要翻译：提供一种用于形成互连结构的盖层的方法。该方法包括提供基板; 在衬底上沉积包含第一致孔剂的低k电介质层; 在低k电介质层上沉积包含第二致孔剂的低k覆盖层; 并且同时固化低k电介质层和低k覆盖层以除去第一和第二致孔剂，从而产生低k电介质层中的第一孔隙和低k覆盖层中的第二孔隙率。第二孔隙率优选小于第一孔隙率。优选地，低k电介质层和低k覆盖层包含一组共同的前体和致孔剂，并且原位进行。

56. 发明授权

US06181013B2 Method for selective growth of Cu3Ge or Cu5Si for passivation of damascene copper structures and device manufactured thereby 有权
标题翻译：选择性生长Cu3Ge或Cu5Si用于钝化镶嵌铜结构的方法及其制造的器件
公开(公告)号：US06181013B2
公开(公告)日：2001-01-30
申请号：US09524521
申请日：2000-03-13
申请人： Chung-Shi Liu , Chen-Hua Yu , Tien-I Bao , Syun-Ming Jang
发明人： Chung-Shi Liu , Chen-Hua Yu , Tien-I Bao , Syun-Ming Jang
IPC分类号： H01L2348
CPC分类号： H01L21/76867 , H01L21/7684 , H01L21/76849
摘要： Form a dielectric layer on a surface of a conductive substrate with a trench through the top surface down to the substrate. Form a barrier layer over the dielectric layer including the exposed surface of the conductive substrate and the exposed sidewalls of the dielectric layer. Form a copper conductor over the barrier layer and overfilling the narrow hole in the trench. Etch away material from the surface of the copper conductor by a CMP process lowering the copper leaving a thin layer of copper over the barrier layer above the dielectric layer aside from the hole. Form a copper passivation by combining an element selected from silicon and germanium with copper on the exposed surfaces of the copper surfaces forming an interface in the narrower hole between the copper and the copper compound located below the dielectric top level. Etch away material from the surface of the copper compound and the barrier layer to planarize the copper compound by etching down to the dielectric top level leaving a thin layer of the copper passivation compound covering the copper conductor in the narrower hole.
摘要翻译：在具有沟槽的导电基底的表面上形成电介质层，通过顶表面向下延伸到衬底。在包括导电基板的暴露表面和电介质层的暴露的侧壁的电介质层上形成阻挡层。在阻挡层上形成一个铜导体，并且填充沟槽中的窄孔。通过CMP工艺从铜表面蚀刻掉材料，在除了孔之外的电介质层之上的阻挡层上方，降低铜，从而留下薄的铜层。通过将选自硅和锗的元素与铜的暴露表面上的铜组合形成铜钝化，在铜和化合物之间的较窄的孔中形成界面，位于电介质顶层之下。从铜化合物的表面和阻挡层的表面蚀刻掉材料以通过蚀刻到电介质顶部水平来平坦化铜化合物，留下覆盖较窄孔中的铜导体的铜钝化化合物的薄层。

57. 发明授权

US06046108A Method for selective growth of Cu.sub.3 Ge or Cu.sub.5 Si for passivation of damascene copper structures and device manufactured thereby 有权
标题翻译：选择性生长Cu3Ge或Cu5Si用于钝化镶嵌铜结构的方法及其制造的器件
公开(公告)号：US06046108A
公开(公告)日：2000-04-04
申请号：US344402
申请日：1999-06-25
申请人： Chung-Shi Liu , Chen-Hua Yu , Tien-I Bao , Syun-Ming Jang
发明人： Chung-Shi Liu , Chen-Hua Yu , Tien-I Bao , Syun-Ming Jang
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76867 , H01L21/7684 , H01L21/76849
摘要： Form a dielectric layer on a surface of a conductive substrate with a trench through the top surface down to the substrate. Form a barrier layer over the dielectric layer including the exposed surface of the conductive substrate and the exposed sidewalls of the dielectric layer. Form a copper conductor over the barrier layer and overfilling the narrow hole in the trench. Etch away material from the surface of the copper conductor by a CMP process lowering the copper leaving a thin layer of copper over the barrier layer above the dielectric layer aside from the hole. Form a copper passivation by combining an element selected from silicon and germanium with copper on the exposed surfaces of the copper surfaces forming an interface in the narrower hole between the copper and the copper compound located below the dielectric top level. Etch away material from the surface of the copper compound and the barrier layer to planiarize the copper compound by etching down to the dielectric top level leaving a thin layer of the copper passivation compound covering the copper conductor in the narrower hole.
摘要翻译：在具有沟槽的导电基底的表面上形成电介质层，通过顶表面向下延伸到衬底。在包括导电基底的暴露表面和电介质层暴露的侧壁的电介质层上形成阻挡层。在阻挡层上形成一个铜导体，并且填充沟槽中的窄孔。通过CMP工艺从铜表面蚀刻掉材料，在除了孔之外的电介质层之上的阻挡层上方，降低铜，从而留下薄的铜层。通过将选自硅和锗的元素与铜的暴露表面上的铜组合形成铜钝化，在铜和化合物之间的较窄的孔中形成界面，位于电介质顶层之下。从铜化合物的表面和阻挡层的表面蚀刻掉材料，以通过蚀刻到电介质顶层来平面化铜化合物，留下在较窄的孔中覆盖铜导体的铜钝化化合物的薄层。

58. 发明申请

US20120282768A1 Schemes for Forming Barrier Layers for Copper in Interconnect Structures 有权
标题翻译：在互连结构中形成铜屏障层的方案
公开(公告)号：US20120282768A1
公开(公告)日：2012-11-08
申请号：US13551500
申请日：2012-07-17
申请人： Chen-Hua Yu , Hai-Ching Chen , Tien-I Bao
发明人： Chen-Hua Yu , Hai-Ching Chen , Tien-I Bao
IPC分类号： H01L21/768
CPC分类号： H01L23/53238 , H01L21/322 , H01L21/76843 , H01L21/76849 , H01L21/76867 , H01L21/76877 , H01L21/76883 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.
摘要翻译：形成半导体结构的方法包括提供基板; 在衬底上形成低k电介质层; 将导电布线嵌入到低k电介质层中; 并且将导电布线热浸在含碳硅烷类化学品中以在导电布线上形成阻挡层。在用于嵌入导电布线的开口中形成衬里阻挡层。衬里阻挡层可以包括与阻挡层相同的材料，并且衬里阻挡层可以在形成阻挡层之前被凹入，并且可以包含可以被硅化的金属。

59. 发明授权

US07482265B2 UV curing of low-k porous dielectrics 有权
标题翻译：低k多孔电介质的UV固化
公开(公告)号：US07482265B2
公开(公告)日：2009-01-27
申请号：US11328596
申请日：2006-01-10
申请人： I-I Chen , Tien-I Bao , Shwang-Ming Cheug , Chen-Hua Yu
发明人： I-I Chen , Tien-I Bao , Shwang-Ming Cheug , Chen-Hua Yu
IPC分类号： H01L21/469
CPC分类号： H01L21/76826 , H01L21/7682 , H01L21/76825 , H01L2221/1047
摘要： A method of manufacturing a semiconductor device having a low-k dielectric layer is provided. An embodiment comprises forming a dielectric layer on a substrate, wherein the layer comprises a pore generating material dispersed in an uncured matrix. A second step comprises forming pores in the uncured matrix by irradiating the layer with radiation having a first wavelength. After pore forming, a third step comprises cross-linking the dielectric by irradiating it at a second wavelength, the second being less than the first. In an embodiment, the irradiating wavelengths comprise ultra-violet radiation. Embodiments may further include repairing processing damage wherein the damage includes dangling bonds or silanol formation. The repairing includes annealing in a carbon-containing ambient such as C2H4, C3H6, or hexamethyldisilazane (HMDS).
摘要翻译：提供一种制造具有低k电介质层的半导体器件的方法。一个实施方案包括在基底上形成介电层，其中该层包含分散在未固化的基质中的孔产生材料。第二步骤包括通过用具有第一波长的辐射照射该层来在未固化的基质中形成孔。在成孔之后，第三步骤包括通过以第二波长照射电介质来交换电介质，第二步小于第一波长。在一个实施例中，照射波长包括紫外辐射。实施方案可以进一步包括修复处理损伤，其中损伤包括悬挂键或硅烷醇形成。修复包括在含碳环境如C2H4，C3H6或六甲基二硅氮烷（HMDS）中的退火。

60. 发明申请

US20140065782A1 METHOD OF MAKING A FINFET DEVICE 有权
标题翻译：制造FINFET器件的方法
公开(公告)号：US20140065782A1
公开(公告)日：2014-03-06
申请号：US13599393
申请日：2012-08-30
申请人： Chih Wei Lu , Chung-Ju Lee , Hsiang-Huan Lee , Tien-I Bao
发明人： Chih Wei Lu , Chung-Ju Lee , Hsiang-Huan Lee , Tien-I Bao
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L29/66795 , H01L21/3065 , H01L21/76224 , H01L21/823814 , H01L21/823821 , H01L21/823864 , H01L21/823878 , H01L27/0924 , H01L29/0653 , H01L29/41766 , H01L29/41791 , H01L29/6656 , H01L29/785 , H01L29/7851
摘要： A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate and fin structures on the substrate. A sidewall spacer is formed along sidewall of fin structures in the precursor. A portion of fin structure is recessed to form a recessing trench with the sidewall spacer as its upper portion. A semiconductor is epitaxially grown in the recessing trench and continually grown above the recessing trench to form an epitaxial structure.
摘要翻译：通过首先接收FinFET前体来制造FinFET器件。 FinFET前体包括衬底和衬底上的翅片结构。在前体中翅片结构的侧壁上形成侧壁间隔物。翅片结构的一部分被凹入以形成具有侧壁间隔件作为其上部的凹陷沟槽。在凹槽中外延生长半导体，并在凹陷沟槽上方持续生长以形成外延结构。

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