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51. 发明申请

US20130032955A1 Low-K Dielectric Layer and Porogen 有权
公开(公告)号：US20130032955A1
公开(公告)日：2013-02-07
申请号：US13204507
申请日：2011-08-05
申请人： Joung-Wei Liou , Hui-Chun Yang , Yu-Yun Peng , Keng-Chu Lin
发明人： Joung-Wei Liou , Hui-Chun Yang , Yu-Yun Peng , Keng-Chu Lin
IPC分类号： H01L21/31 , H01L23/29 , H01L21/28
CPC分类号： H01L21/76879 , H01L21/02123 , H01L21/02203 , H01L21/02211 , H01L21/02274 , H01L21/02321 , H01L21/76801 , H01L21/7682 , H01L21/76829 , H01L23/31 , H01L23/481 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5.

52. 发明授权

US08258629B2 Curing low-k dielectrics for improving mechanical strength 有权
标题翻译：固化低k电介质以提高机械强度
公开(公告)号：US08258629B2
公开(公告)日：2012-09-04
申请号：US12060999
申请日：2008-04-02
申请人： Joung-Wei Liou , Keng-Chu Lin , Shwang-Ming Jeng
发明人： Joung-Wei Liou , Keng-Chu Lin , Shwang-Ming Jeng
IPC分类号： H01L23/48
CPC分类号： H01L23/522 , H01L21/02348 , H01L21/31 , H01L21/76825 , H01L23/53295 , H01L23/562 , H01L24/05 , H01L2224/04042 , H01L2224/05 , H01L2224/05553 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105
摘要： An integrated circuit structure including reflective metal pads is provided. The integrated circuit structure includes a semiconductor substrate; a first low-k dielectric layer overlying the semiconductor substrate, wherein the first low-k dielectric layer is a top low-k dielectric layer; a second low-k dielectric layer immediately underlying the first low-k dielectric layer; and a reflective metal pad in the second low-k dielectric layer.
摘要翻译：提供了包括反射金属焊盘的集成电路结构。集成电路结构包括半导体衬底; 覆盖半导体衬底的第一低k电介质层，其中第一低k电介质层是顶部低k电介质层; 位于第一低k电介质层下面的第二低k电介质层; 以及第二低k电介质层中的反射金属焊盘。

53. 再颁专利

USRE42514E1 Extreme low-K dielectric film scheme for advanced interconnects 有权
标题翻译：用于高级互连的极低K电介质膜方案
公开(公告)号：USRE42514E1
公开(公告)日：2011-07-05
申请号：US12943479
申请日：2010-11-10
申请人： Fang-Wen Tsai , Kuan-Chen Wang , Keng-Chu Lin , Chih-Lung Lin , Shwang-Ming Jeng
发明人： Fang-Wen Tsai , Kuan-Chen Wang , Keng-Chu Lin , Chih-Lung Lin , Shwang-Ming Jeng
IPC分类号： H01L23/58 , H01L23/48 , H01L29/40
CPC分类号： H01L23/53295 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An extreme low-k (ELK) dielectric film scheme for advanced interconnects includes an upper ELK dielectric layer and a lower ELK dielectric with different refractive indexes. The refractive index of the upper ELK dielectric layer is greater than the refractive index of the lower ELK dielectric layer.
摘要翻译：用于高级互连的极低k（ELK）电介质膜方案包括上ELK电介质层和具有不同折射率的下ELK电介质。上部ELK介电层的折射率大于下部ELK介电层的折射率。

54. 再颁专利

USRE41935E1 Method for preventing low-k dielectric layer cracking in multi-layered dual damascene metallization layers 有权
标题翻译：用于防止多层双镶嵌金属化层中低k电介质层开裂的方法
公开(公告)号：USRE41935E1
公开(公告)日：2010-11-16
申请号：US11655743
申请日：2007-01-19
申请人： Shing-Chyang Pan , Keng-Chu Lin , Wen-Chih Chiou , Shwang-Ming Jeng
发明人： Shing-Chyang Pan , Keng-Chu Lin , Wen-Chih Chiou , Shwang-Ming Jeng
IPC分类号： H01L21/26 , H01L21/324 , H01L21/42 , H01L21/4763 , H01L21/477
CPC分类号： H01L21/76814 , H01L21/3003 , H01L21/31116 , H01L21/31127 , H01L21/76807 , H01L21/76843
摘要： A method for plasma treatment of anisotropically etched openings to improve a crack initiation and propagation resistance including providing a semiconductor wafer having a process surface including anisotropically etched openings extending at least partially through a dielectric insulating layer; plasma treating in at least one plasma treatment the process surface including the anisotropically etched openings to improve an adhesion of a subsequently deposited refractory metal adhesion/barrier layer thereover; and, blanket depositing at least one refractory metal adhesion/barrier layer to line the anisotropically etched openings.
摘要翻译：一种用于等离子体处理各向异性蚀刻的开口以改善裂纹起始和传播阻力的方法，包括提供具有包括各向异性蚀刻的开口的半导体晶片，所述工艺表面包括至少部分延伸穿过介电绝缘层的工艺表面; 在至少一个等离子体处理等离子体处理包括各向异性蚀刻的开口的工艺表面，以改善随后沉积的难熔金属粘合/阻挡层在其上的粘附; 并且毯子沉积至少一个难熔金属粘合/阻挡层以对各向异性蚀刻的开口进行排列。

55. 发明申请

US20090250792A1 Curing Low-k Dielectrics for Improving Mechanical Strength 有权
标题翻译：固化低k电介质，提高机械强度
公开(公告)号：US20090250792A1
公开(公告)日：2009-10-08
申请号：US12060999
申请日：2008-04-02
申请人： Joung-Wei Liou , Keng-Chu Lin , Shwang-Ming Jeng
发明人： Joung-Wei Liou , Keng-Chu Lin , Shwang-Ming Jeng
IPC分类号： H01L23/544
CPC分类号： H01L23/522 , H01L21/02348 , H01L21/31 , H01L21/76825 , H01L23/53295 , H01L23/562 , H01L24/05 , H01L2224/04042 , H01L2224/05 , H01L2224/05553 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105
摘要： An integrated circuit structure including reflective metal pads is provided. The integrated circuit structure includes a semiconductor substrate; a first low-k dielectric layer overlying the semiconductor substrate, wherein the first low-k dielectric layer is a top low-k dielectric layer; a second low-k dielectric layer immediately underlying the first low-k dielectric layer; and a reflective metal pad in the second low-k dielectric layer.
摘要翻译：提供了包括反射金属焊盘的集成电路结构。集成电路结构包括半导体衬底; 覆盖半导体衬底的第一低k电介质层，其中第一低k电介质层是顶部低k电介质层; 位于第一低k电介质层下面的第二低k电介质层; 以及第二低k电介质层中的反射金属焊盘。

56. 发明授权

US07230596B2 Active organic electroluminescence display panel module and driving module thereof 有权
标题翻译：主动有机电致发光显示面板模块及其驱动模块
公开(公告)号：US07230596B2
公开(公告)日：2007-06-12
申请号：US11061333
申请日：2005-02-18
申请人： Hong-Ru Guo , Keng-Chu Lin , Chen-Chung Yang
发明人： Hong-Ru Guo , Keng-Chu Lin , Chen-Chung Yang
IPC分类号： G09G3/30
CPC分类号： G09G3/3233 , G09G2300/0809 , G09G2320/0233 , G09G2320/029 , G09G2320/041
摘要： An active organic electroluminescence display panel module comprising a substrate, a plurality of organic light-emitting devices, a light-emitting device driving unit and a temperature sensor unit are provided. The light-emitting device driving unit is electrically connected to the organic light-emitting devices for driving them. The temperature sensor unit is disposed on the substrate for sensing the temperature of the active organic electroluminescence display panel. The temperature sensor unit is also electrically connected to the light-emitting device driving unit for providing a signal to the light-emitting device driving unit in response to the sensed temperature. Accordingly, the light-emitting device driving unit can adjust the driving voltage of the organic light-emitting devices in the active organic electroluminescence display panel to reduce overall power consumption and provide an accurate grayscale to improve the quality of displayed images.
摘要翻译：提供一种有源电致发光显示面板模块，其包括基板，多个有机发光器件，发光器件驱动单元和温度传感器单元。发光器件驱动单元电连接到用于驱动它们的有机发光器件。温度传感器单元设置在用于感测活性有机电致发光显示面板的温度的基板上。温度传感器单元还电连接到发光器件驱动单元，用于响应于感测到的温度向发光器件驱动单元提供信号。因此，发光器件驱动单元可以调节活性有机电致发光显示面板中的有机发光器件的驱动电压，以降低整体功耗，并提供准确的灰度级以提高显示图像的质量。

57. 发明申请

US20050269957A1 Driving circuits, compensation circuits and signal compensation method for pixel of active organic electro-luminescence device 审中-公开
标题翻译：用于有源有机电致发光器件像素的驱动电路，补偿电路和信号补偿方法
公开(公告)号：US20050269957A1
公开(公告)日：2005-12-08
申请号：US11056303
申请日：2005-02-11
申请人： Hong-Ru Guo , Keng-Chu Lin , Chen-Chung Yang , Chia-Tin Chung
发明人： Hong-Ru Guo , Keng-Chu Lin , Chen-Chung Yang , Chia-Tin Chung
IPC分类号： G09G3/10
CPC分类号： G09G3/3233 , G09G3/3291 , G09G2320/0233
摘要： A driving circuit of a pixel of an active organic electro-luminescence device for driving an emitting device in the pixel of the active organic electro-luminescence device is provided. A voltage sensor is adapted for sensing the voltage of the emitting device and sending out the signal according to the voltage. A compensation unit is adapted for receiving the signal output from the voltage sensor. A compensating signal is sent to an emitting device driving unit for compensating the data signal input into the pixel of active organic electro-luminescence device so as to improve uniformity in the brightness of the active organic electro-luminescence device.
摘要翻译：提供了用于驱动有源有机电致发光器件的像素中的发光器件的有源有机电致发光器件的像素的驱动电路。电压传感器适于感测发射装置的电压并根据电压发出信号。补偿单元适于接收从电压传感器输出的信号。补偿信号被发送到发射器件驱动单元，用于补偿输入到有源有机电致发光器件的像素中的数据信号，以便改善有源有机电致发光器件的亮度的均匀性。

58. 发明授权

US06638853B1 Method for avoiding photoresist resist residue on semioconductor feature sidewalls 有权
标题翻译：在半导体特征侧壁上避免光致抗蚀剂残留物的方法
公开(公告)号：US06638853B1
公开(公告)日：2003-10-28
申请号：US10190148
申请日：2002-07-03
申请人： Hung-Wen Sue , Chung-Shi Liu , Wen-Chin Chiou , Keng-Chu Lin
发明人： Hung-Wen Sue , Chung-Shi Liu , Wen-Chin Chiou , Keng-Chu Lin
IPC分类号： H01L214763
CPC分类号： H01L21/76808
摘要： A method for improving a photolithographic patterning process to avoid undeveloped photoresist contamination in a semiconductor manufacturing process including providing a semiconductor wafer having a process surface including a first anisotropically etched opening extending through a semiconductor wafer thickness portion including an underlying dielectric insulating layer; blanket depositing a polymeric resinous layer over the semiconductor wafer process surface to include filling the first anisotropically etched opening; curing the polymeric resinous layer by exposing the polymeric resinous layer to at least one of thermal or photonic energy to initiate polymer cross linking; chemically mechanically polishing (CMP) the polymeric resinous layer to substantially remove the polymeric resinous layer thickness above the process surface; and, forming a photolithographically patterned photoresist layer over the process surface for forming a second anisotropically etched opening overlying and encompassing the first anisotropically etched opening.
摘要翻译：一种用于改善光刻图案化工艺以避免半导体制造工艺中未发展的光致抗蚀剂污染的方法，包括提供具有工艺表面的半导体晶片，所述工艺表面包括延伸穿过包括下面的介电绝缘层的半导体晶片厚度部分的第一各向异性蚀刻的开口; 在所述半导体晶片工艺表面上覆盖沉积聚合物树脂层以包括填充所述第一各向异性蚀刻的开口; 通过将聚合物树脂层暴露于热能或光子能中的至少一种以引发聚合物交联来固化聚合物树脂层; 化学机械抛光（CMP）聚合物树脂层以基本上去除工艺表面上方的聚合树脂层厚度; 以及在所述工艺表面上形成光刻图案化的光致抗蚀剂层，以形成覆盖并包围所述第一各向异性蚀刻的开口的第二各向异性蚀刻的开口。

59. 发明授权

US6136688A High stress oxide to eliminate BPSG/SiN cracking 有权
标题翻译：高应力氧化物消除BPSG / SiN开裂
公开(公告)号：US6136688A
公开(公告)日：2000-10-24
申请号：US421508
申请日：1999-10-20
申请人： Keng-Chu Lin , Kuang-Chao Chen , Rong-Wu Chien , Lian-Fa Hung , Pang-Yen Tsai , Ching-Chang Chang
发明人： Keng-Chu Lin , Kuang-Chao Chen , Rong-Wu Chien , Lian-Fa Hung , Pang-Yen Tsai , Ching-Chang Chang
IPC分类号： H01L21/316 , H01L21/318 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/02126 , H01L21/02129 , H01L21/02274 , H01L21/02362 , H01L21/31625 , H01L21/76829 , H01L21/76834 , H01L21/3185
摘要： The present invention is a method of capping with a high compressive stress oxide, a boron phospho-silicate glass (BPSG) interlayer dielectric (ILD) gapfill that has been deposited on a topographic silicon substrate, in order to eliminate the formation of cracks in subsequently deposited silicon nitride (SiN) layers, other subsequently deposited high tensile stress layers and cracks that result from other post-BPSG deposition high temperature processes.
摘要翻译：本发明是一种用高压缩应力氧化物覆盖的方法，已经沉积在地形硅衬底上的硼磷硅酸盐玻璃（BPSG）层间电介质（ILD）间隙填料，以便于随后消除裂纹的形成沉积的氮化硅（SiN）层，其它随后沉积的高拉伸应力层和由其他后BPSG沉积高温工艺引起的裂纹。

60. 发明授权

US09349689B2 Semiconductor devices including conductive features with capping layers and methods of forming the same 有权
标题翻译：包括具有封盖层的导电特征的半导体器件及其形成方法
公开(公告)号：US09349689B2
公开(公告)日：2016-05-24
申请号：US13452446
申请日：2012-04-20
申请人： Hui-Chun Yang , Mei-Ling Chen , Keng-Chu Lin , Joung-Wei Liou
发明人： Hui-Chun Yang , Mei-Ling Chen , Keng-Chu Lin , Joung-Wei Liou
IPC分类号： H01L21/4763 , H01L23/532 , H01L21/285 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/28562 , H01L21/76802 , H01L21/76807 , H01L21/7681 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/7684 , H01L21/76843 , H01L21/76849 , H01L21/7685 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices, methods of manufacture thereof, and methods of forming conductive features thereof are disclosed. A semiconductor device includes an insulating material layer disposed over a workpiece. The insulating material layer includes a silicon-containing material comprising about 13% or greater of carbon (C). A conductive feature is disposed within the insulating material layer. The conductive feature includes a capping layer disposed on a top surface thereof.
摘要翻译：公开了半导体器件，其制造方法以及形成其导电特征的方法。半导体器件包括设置在工件上方的绝缘材料层。绝缘材料层包括含有约13％或更多碳（C）的含硅材料。导电特征设置在绝缘材料层内。导电特征包括设置在其顶表面上的覆盖层。

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